Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	218704923	436	0	0
StatusRise_A	218704923	436	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218704923	436	0	0
T1	88551	0	0	0
T7	3111	5	0	0
T24	3459	0	0	0
T25	3150	0	0	0
T26	7113	0	0	0
T27	4062	0	0	0
T28	4311	0	0	0
T29	7269	0	0	0
T30	6414	0	0	0
T39	0	14	0	0
T40	0	6	0	0
T67	2079	0	0	0
T155	0	6	0	0
T156	0	2	0	0
T157	0	3	0	0
T158	0	15	0	0
T159	0	5	0	0
T160	0	3	0	0
T161	0	11	0	0
T162	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218704923	436	0	0
T1	88551	0	0	0
T7	3111	5	0	0
T24	3459	0	0	0
T25	3150	0	0	0
T26	7113	0	0	0
T27	4062	0	0	0
T28	4311	0	0	0
T29	7269	0	0	0
T30	6414	0	0	0
T39	0	14	0	0
T40	0	6	0	0
T67	2079	0	0	0
T155	0	6	0	0
T156	0	2	0	0
T157	0	3	0	0
T158	0	15	0	0
T159	0	5	0	0
T160	0	3	0	0
T161	0	11	0	0
T162	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	72901641	149	0	0
StatusRise_A	72901641	149	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	149	0	0
T1	29517	0	0	0
T7	1037	1	0	0
T24	1153	0	0	0
T25	1050	0	0	0
T26	2371	0	0	0
T27	1354	0	0	0
T28	1437	0	0	0
T29	2423	0	0	0
T30	2138	0	0	0
T39	0	6	0	0
T40	0	2	0	0
T67	693	0	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	6	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	149	0	0
T1	29517	0	0	0
T7	1037	1	0	0
T24	1153	0	0	0
T25	1050	0	0	0
T26	2371	0	0	0
T27	1354	0	0	0
T28	1437	0	0	0
T29	2423	0	0	0
T30	2138	0	0	0
T39	0	6	0	0
T40	0	2	0	0
T67	693	0	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	6	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	72901641	132	0	0
StatusRise_A	72901641	132	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	132	0	0
T1	29517	0	0	0
T7	1037	1	0	0
T24	1153	0	0	0
T25	1050	0	0	0
T26	2371	0	0	0
T27	1354	0	0	0
T28	1437	0	0	0
T29	2423	0	0	0
T30	2138	0	0	0
T39	0	4	0	0
T40	0	2	0	0
T67	693	0	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	1	0	0
T161	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	132	0	0
T1	29517	0	0	0
T7	1037	1	0	0
T24	1153	0	0	0
T25	1050	0	0	0
T26	2371	0	0	0
T27	1354	0	0	0
T28	1437	0	0	0
T29	2423	0	0	0
T30	2138	0	0	0
T39	0	4	0	0
T40	0	2	0	0
T67	693	0	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	1	0	0
T161	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	72901641	155	0	0
StatusRise_A	72901641	155	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	155	0	0
T1	29517	0	0	0
T7	1037	3	0	0
T24	1153	0	0	0
T25	1050	0	0	0
T26	2371	0	0	0
T27	1354	0	0	0
T28	1437	0	0	0
T29	2423	0	0	0
T30	2138	0	0	0
T39	0	4	0	0
T40	0	2	0	0
T67	693	0	0	0
T155	0	2	0	0
T157	0	1	0	0
T158	0	6	0	0
T159	0	2	0	0
T160	0	1	0	0
T161	0	5	0	0
T162	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	155	0	0
T1	29517	0	0	0
T7	1037	3	0	0
T24	1153	0	0	0
T25	1050	0	0	0
T26	2371	0	0	0
T27	1354	0	0	0
T28	1437	0	0	0
T29	2423	0	0	0
T30	2138	0	0	0
T39	0	4	0	0
T40	0	2	0	0
T67	693	0	0	0
T155	0	2	0	0
T157	0	1	0	0
T158	0	6	0	0
T159	0	2	0	0
T160	0	1	0	0
T161	0	5	0	0
T162	0	1	0	0