Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T2,T4
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	33846	0	0
CgEnOn_A	2147483647	25083	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33846	0	0
T1	1062621	0	0	0
T2	0	5	0	0
T5	9608	3	0	0
T6	9528	44	0	0
T7	62664	12	0	0
T11	0	65	0	0
T20	0	6	0	0
T24	45966	3	0	0
T25	47086	3	0	0
T26	26210	3	0	0
T27	61302	3	0	0
T28	15940	3	0	0
T29	38038	3	0	0
T30	23100	7	0	0
T39	0	20	0	0
T40	0	10	0	0
T67	24956	0	0	0
T155	0	10	0	0
T156	0	5	0	0
T157	0	5	0	0
T158	0	15	0	0
T159	0	10	0	0
T160	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	25083	0	0
T1	1062621	0	0	0
T2	0	69	0	0
T3	0	9	0	0
T6	9528	41	0	0
T7	62664	9	0	0
T11	0	234	0	0
T12	0	285	0	0
T15	0	31	0	0
T20	0	6	0	0
T24	45966	0	0	0
T25	47086	0	0	0
T26	26210	0	0	0
T27	61302	0	0	0
T28	15940	0	0	0
T29	38038	0	0	0
T30	23100	4	0	0
T39	0	20	0	0
T40	0	10	0	0
T67	31184	10	0	0
T77	0	25	0	0
T78	0	4	0	0
T155	0	10	0	0
T156	0	5	0	0
T157	0	5	0	0
T158	0	15	0	0
T159	0	10	0	0
T160	0	5	0	0
T161	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T2,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	109955818	134	0	0
CgEnOn_A	109955818	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109955818	134	0	0
T1	59023	0	0	0
T7	2833	1	0	0
T11	0	1	0	0
T24	2010	0	0	0
T25	2049	0	0	0
T26	1290	0	0	0
T27	2793	0	0	0
T28	698	0	0	0
T29	1827	0	0	0
T30	983	0	0	0
T39	0	4	0	0
T40	0	2	0	0
T67	1376	0	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109955818	134	0	0
T1	59023	0	0	0
T7	2833	1	0	0
T11	0	1	0	0
T24	2010	0	0	0
T25	2049	0	0	0
T26	1290	0	0	0
T27	2793	0	0	0
T28	698	0	0	0
T29	1827	0	0	0
T30	983	0	0	0
T39	0	4	0	0
T40	0	2	0	0
T67	1376	0	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T2,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	54977509	134	0	0
CgEnOn_A	54977509	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54977509	134	0	0
T1	29511	0	0	0
T7	1416	1	0	0
T11	0	1	0	0
T24	1005	0	0	0
T25	1024	0	0	0
T26	644	0	0	0
T27	1395	0	0	0
T28	349	0	0	0
T29	911	0	0	0
T30	491	0	0	0
T39	0	4	0	0
T40	0	2	0	0
T67	688	0	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54977509	134	0	0
T1	29511	0	0	0
T7	1416	1	0	0
T11	0	1	0	0
T24	1005	0	0	0
T25	1024	0	0	0
T26	644	0	0	0
T27	1395	0	0	0
T28	349	0	0	0
T29	911	0	0	0
T30	491	0	0	0
T39	0	4	0	0
T40	0	2	0	0
T67	688	0	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T2,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	54977509	134	0	0
CgEnOn_A	54977509	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54977509	134	0	0
T1	29511	0	0	0
T7	1416	1	0	0
T11	0	1	0	0
T24	1005	0	0	0
T25	1024	0	0	0
T26	644	0	0	0
T27	1395	0	0	0
T28	349	0	0	0
T29	911	0	0	0
T30	491	0	0	0
T39	0	4	0	0
T40	0	2	0	0
T67	688	0	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54977509	134	0	0
T1	29511	0	0	0
T7	1416	1	0	0
T11	0	1	0	0
T24	1005	0	0	0
T25	1024	0	0	0
T26	644	0	0	0
T27	1395	0	0	0
T28	349	0	0	0
T29	911	0	0	0
T30	491	0	0	0
T39	0	4	0	0
T40	0	2	0	0
T67	688	0	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T2,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	54977509	134	0	0
CgEnOn_A	54977509	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54977509	134	0	0
T1	29511	0	0	0
T7	1416	1	0	0
T11	0	1	0	0
T24	1005	0	0	0
T25	1024	0	0	0
T26	644	0	0	0
T27	1395	0	0	0
T28	349	0	0	0
T29	911	0	0	0
T30	491	0	0	0
T39	0	4	0	0
T40	0	2	0	0
T67	688	0	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54977509	134	0	0
T1	29511	0	0	0
T7	1416	1	0	0
T11	0	1	0	0
T24	1005	0	0	0
T25	1024	0	0	0
T26	644	0	0	0
T27	1395	0	0	0
T28	349	0	0	0
T29	911	0	0	0
T30	491	0	0	0
T39	0	4	0	0
T40	0	2	0	0
T67	688	0	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T2,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	221350909	134	0	0
CgEnOn_A	221350909	132	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221350909	134	0	0
T1	118070	0	0	0
T7	5786	1	0	0
T11	0	1	0	0
T24	4100	0	0	0
T25	4204	0	0	0
T26	2276	0	0	0
T27	5420	0	0	0
T28	1421	0	0	0
T29	3323	0	0	0
T30	2072	0	0	0
T39	0	4	0	0
T40	0	2	0	0
T67	2776	0	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221350909	132	0	0
T1	118070	0	0	0
T7	5786	1	0	0
T24	4100	0	0	0
T25	4204	0	0	0
T26	2276	0	0	0
T27	5420	0	0	0
T28	1421	0	0	0
T29	3323	0	0	0
T30	2072	0	0	0
T39	0	4	0	0
T40	0	2	0	0
T67	2776	0	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	1	0	0
T161	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T2,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	236483738	150	0	0
CgEnOn_A	236483738	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236483738	150	0	0
T1	122993	0	0	0
T7	5698	1	0	0
T24	4271	0	0	0
T25	4380	0	0	0
T26	2371	0	0	0
T27	5646	0	0	0
T28	1481	0	0	0
T29	3462	0	0	0
T30	2159	0	0	0
T39	0	6	0	0
T40	0	2	0	0
T41	0	1	0	0
T67	2892	0	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	6	0	0
T159	0	1	0	0
T160	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236483738	149	0	0
T1	122993	0	0	0
T7	5698	1	0	0
T24	4271	0	0	0
T25	4380	0	0	0
T26	2371	0	0	0
T27	5646	0	0	0
T28	1481	0	0	0
T29	3462	0	0	0
T30	2159	0	0	0
T39	0	6	0	0
T40	0	2	0	0
T67	2892	0	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	6	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T2,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	236483738	150	0	0
CgEnOn_A	236483738	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236483738	150	0	0
T1	122993	0	0	0
T7	5698	1	0	0
T24	4271	0	0	0
T25	4380	0	0	0
T26	2371	0	0	0
T27	5646	0	0	0
T28	1481	0	0	0
T29	3462	0	0	0
T30	2159	0	0	0
T39	0	6	0	0
T40	0	2	0	0
T41	0	1	0	0
T67	2892	0	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	6	0	0
T159	0	1	0	0
T160	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236483738	149	0	0
T1	122993	0	0	0
T7	5698	1	0	0
T24	4271	0	0	0
T25	4380	0	0	0
T26	2371	0	0	0
T27	5646	0	0	0
T28	1481	0	0	0
T29	3462	0	0	0
T30	2159	0	0	0
T39	0	6	0	0
T40	0	2	0	0
T67	2892	0	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	6	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T2,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	113377980	158	0	0
CgEnOn_A	113377980	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113377980	158	0	0
T1	59037	0	0	0
T7	2787	3	0	0
T24	2050	0	0	0
T25	2102	0	0	0
T26	1138	0	0	0
T27	2710	0	0	0
T28	710	0	0	0
T29	1661	0	0	0
T30	1036	0	0	0
T39	0	4	0	0
T40	0	2	0	0
T67	1388	0	0	0
T69	0	1	0	0
T155	0	2	0	0
T157	0	1	0	0
T158	0	6	0	0
T159	0	2	0	0
T160	0	1	0	0
T161	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113377980	155	0	0
T1	59037	0	0	0
T7	2787	3	0	0
T24	2050	0	0	0
T25	2102	0	0	0
T26	1138	0	0	0
T27	2710	0	0	0
T28	710	0	0	0
T29	1661	0	0	0
T30	1036	0	0	0
T39	0	4	0	0
T40	0	2	0	0
T67	1388	0	0	0
T155	0	2	0	0
T157	0	1	0	0
T158	0	6	0	0
T159	0	2	0	0
T160	0	1	0	0
T161	0	5	0	0
T162	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T39,T40
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	54977509	5684	0	0
CgEnOn_A	54977509	3497	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54977509	5684	0	0
T5	1092	1	0	0
T6	1045	15	0	0
T7	1416	2	0	0
T24	1005	1	0	0
T25	1024	1	0	0
T26	644	1	0	0
T27	1395	1	0	0
T28	349	1	0	0
T29	911	1	0	0
T30	491	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54977509	3497	0	0
T2	0	22	0	0
T6	1045	14	0	0
T7	1416	1	0	0
T11	0	57	0	0
T12	0	79	0	0
T15	0	13	0	0
T24	1005	0	0	0
T25	1024	0	0	0
T26	644	0	0	0
T27	1395	0	0	0
T28	349	0	0	0
T29	911	0	0	0
T30	491	1	0	0
T67	688	4	0	0
T77	0	8	0	0
T78	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T39,T40
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	109955818	5703	0	0
CgEnOn_A	109955818	3516	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109955818	5703	0	0
T5	2185	1	0	0
T6	2091	14	0	0
T7	2833	2	0	0
T24	2010	1	0	0
T25	2049	1	0	0
T26	1290	1	0	0
T27	2793	1	0	0
T28	698	1	0	0
T29	1827	1	0	0
T30	983	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109955818	3516	0	0
T2	0	21	0	0
T6	2091	13	0	0
T7	2833	1	0	0
T11	0	56	0	0
T12	0	84	0	0
T15	0	14	0	0
T24	2010	0	0	0
T25	2049	0	0	0
T26	1290	0	0	0
T27	2793	0	0	0
T28	698	0	0	0
T29	1827	0	0	0
T30	983	1	0	0
T67	1376	3	0	0
T77	0	9	0	0
T78	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T39,T40
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	221350909	5720	0	0
CgEnOn_A	221350909	3531	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221350909	5720	0	0
T5	4221	1	0	0
T6	4261	15	0	0
T7	5786	2	0	0
T24	4100	1	0	0
T25	4204	1	0	0
T26	2276	1	0	0
T27	5420	1	0	0
T28	1421	1	0	0
T29	3323	1	0	0
T30	2072	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221350909	3531	0	0
T2	0	21	0	0
T3	0	1	0	0
T6	4261	14	0	0
T7	5786	1	0	0
T11	0	57	0	0
T12	0	81	0	0
T24	4100	0	0	0
T25	4204	0	0	0
T26	2276	0	0	0
T27	5420	0	0	0
T28	1421	0	0	0
T29	3323	0	0	0
T30	2072	1	0	0
T67	2776	3	0	0
T77	0	8	0	0
T78	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T39,T40
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	113377980	5744	0	0
CgEnOn_A	113377980	3555	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113377980	5744	0	0
T5	2110	1	0	0
T6	2131	16	0	0
T7	2787	4	0	0
T24	2050	1	0	0
T25	2102	1	0	0
T26	1138	1	0	0
T27	2710	1	0	0
T28	710	1	0	0
T29	1661	1	0	0
T30	1036	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113377980	3555	0	0
T2	0	21	0	0
T6	2131	15	0	0
T7	2787	3	0	0
T11	0	59	0	0
T12	0	84	0	0
T15	0	12	0	0
T24	2050	0	0	0
T25	2102	0	0	0
T26	1138	0	0	0
T27	2710	0	0	0
T28	710	0	0	0
T29	1661	0	0	0
T30	1036	1	0	0
T67	1388	4	0	0
T77	0	8	0	0
T78	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T2,T4
1	0	Covered	T30,T2,T20
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	236483738	2439	0	0
CgEnOn_A	236483738	2438	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236483738	2439	0	0
T1	122993	0	0	0
T2	0	5	0	0
T3	0	8	0	0
T7	5698	1	0	0
T11	0	60	0	0
T12	0	41	0	0
T15	0	4	0	0
T20	0	6	0	0
T24	4271	0	0	0
T25	4380	0	0	0
T26	2371	0	0	0
T27	5646	0	0	0
T28	1481	0	0	0
T29	3462	0	0	0
T30	2159	1	0	0
T32	0	3	0	0
T67	2892	0	0	0
T78	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236483738	2438	0	0
T1	122993	0	0	0
T2	0	5	0	0
T3	0	8	0	0
T7	5698	1	0	0
T11	0	60	0	0
T12	0	41	0	0
T15	0	4	0	0
T20	0	6	0	0
T24	4271	0	0	0
T25	4380	0	0	0
T26	2371	0	0	0
T27	5646	0	0	0
T28	1481	0	0	0
T29	3462	0	0	0
T30	2159	1	0	0
T32	0	3	0	0
T67	2892	0	0	0
T78	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T2,T4
1	0	Covered	T30,T2,T20
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	236483738	2476	0	0
CgEnOn_A	236483738	2475	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236483738	2476	0	0
T1	122993	0	0	0
T2	0	6	0	0
T3	0	6	0	0
T7	5698	1	0	0
T11	0	56	0	0
T12	0	51	0	0
T15	0	5	0	0
T20	0	1	0	0
T24	4271	0	0	0
T25	4380	0	0	0
T26	2371	0	0	0
T27	5646	0	0	0
T28	1481	0	0	0
T29	3462	0	0	0
T30	2159	1	0	0
T32	0	2	0	0
T67	2892	0	0	0
T78	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236483738	2475	0	0
T1	122993	0	0	0
T2	0	6	0	0
T3	0	6	0	0
T7	5698	1	0	0
T11	0	56	0	0
T12	0	51	0	0
T15	0	5	0	0
T20	0	1	0	0
T24	4271	0	0	0
T25	4380	0	0	0
T26	2371	0	0	0
T27	5646	0	0	0
T28	1481	0	0	0
T29	3462	0	0	0
T30	2159	1	0	0
T32	0	2	0	0
T67	2892	0	0	0
T78	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T2,T4
1	0	Covered	T30,T2,T20
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	236483738	2490	0	0
CgEnOn_A	236483738	2489	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236483738	2490	0	0
T1	122993	0	0	0
T2	0	3	0	0
T3	0	5	0	0
T7	5698	1	0	0
T11	0	60	0	0
T12	0	49	0	0
T15	0	4	0	0
T20	0	2	0	0
T24	4271	0	0	0
T25	4380	0	0	0
T26	2371	0	0	0
T27	5646	0	0	0
T28	1481	0	0	0
T29	3462	0	0	0
T30	2159	1	0	0
T32	0	2	0	0
T67	2892	0	0	0
T78	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236483738	2489	0	0
T1	122993	0	0	0
T2	0	3	0	0
T3	0	5	0	0
T7	5698	1	0	0
T11	0	60	0	0
T12	0	49	0	0
T15	0	4	0	0
T20	0	2	0	0
T24	4271	0	0	0
T25	4380	0	0	0
T26	2371	0	0	0
T27	5646	0	0	0
T28	1481	0	0	0
T29	3462	0	0	0
T30	2159	1	0	0
T32	0	2	0	0
T67	2892	0	0	0
T78	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T2,T4
1	0	Covered	T30,T2,T20
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	236483738	2462	0	0
CgEnOn_A	236483738	2461	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236483738	2462	0	0
T1	122993	0	0	0
T2	0	3	0	0
T3	0	10	0	0
T7	5698	1	0	0
T11	0	47	0	0
T12	0	42	0	0
T15	0	5	0	0
T20	0	1	0	0
T24	4271	0	0	0
T25	4380	0	0	0
T26	2371	0	0	0
T27	5646	0	0	0
T28	1481	0	0	0
T29	3462	0	0	0
T30	2159	1	0	0
T32	0	3	0	0
T67	2892	0	0	0
T78	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236483738	2461	0	0
T1	122993	0	0	0
T2	0	3	0	0
T3	0	10	0	0
T7	5698	1	0	0
T11	0	47	0	0
T12	0	42	0	0
T15	0	5	0	0
T20	0	1	0	0
T24	4271	0	0	0
T25	4380	0	0	0
T26	2371	0	0	0
T27	5646	0	0	0
T28	1481	0	0	0
T29	3462	0	0	0
T30	2159	1	0	0
T32	0	3	0	0
T67	2892	0	0	0
T78	0	1	0	0