Unified Coverage Report :: Module :: prim_generic_clock_div

Module : prim_generic_clock_div

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic	0.00	0.00	0.00			0.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_no_scan_io_div2_div

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_div2.u_div2	0.00	0.00				0.00
gen_div2.u_inv	0.00	0.00
gen_div2.u_step_down_mux	0.00	0.00	0.00
u_clk_div_buf	0.00	0.00
u_clk_mux	0.00	0.00	0.00

---

Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_no_scan_io_div4_div

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_clk_div_buf	0.00	0.00
u_clk_mux	0.00	0.00	0.00

Line Coverage for Module : prim_generic_clock_div ( parameter Divisor=2,ResetValue=0 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		5	0	0.00
CONT_ASSIGN	27	1	0	0.00
ALWAYS	55	3	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' or '../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
27	0	1
55	0	1
56	0	1
58	0	1
72	0	1

---

Line Coverage for Module : prim_generic_clock_div ( parameter Divisor=4,ResetValue=0,gen_div.ToggleCnt=2,gen_div.CntWidth=1 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		12	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	81	1	0	0.00
ALWAYS	85	7	0	0.00
ALWAYS	97	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' or '../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
27	0	1
81	0	1
85	0	1
86	0	1
87	0	1
88	0	1
89	0	1
90	0	1
92	0	1
97	0	1
98	0	1
100	0	1

---

Cond Coverage for Module : prim_generic_clock_div ( parameter Divisor=2,ResetValue=0 )
Cond Coverage for Module self-instances :

SCORE	COND
0.00	0.00

tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	2	0	0.00
Logical	2	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       27
 EXPRESSION (test_en_i ? '0 : step_down_req_i)
             ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Cond Coverage for Module : prim_generic_clock_div ( parameter Divisor=4,ResetValue=0,gen_div.ToggleCnt=2,gen_div.CntWidth=1 )
Cond Coverage for Module self-instances :

SCORE	COND
0.00	0.00

tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	4	0	0.00
Logical	4	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       27
 EXPRESSION (test_en_i ? '0 : step_down_req_i)
             ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       81
 EXPRESSION (((!step_down_req)) ? (1'((gen_div.ToggleCnt - 1))) : ((((gen_div.ToggleCnt / 2) == 2) ? '0 : 1'(((gen_div.ToggleCnt / 2) - 1)))))
             ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Module : prim_generic_clock_div ( parameter Divisor=2,ResetValue=0 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
0.00	0.00

tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	0	0.00
TERNARY	27	2	0	0.00
IF	55	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' or '../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	27	(test_en_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

---

Branch Coverage for Module : prim_generic_clock_div ( parameter Divisor=4,ResetValue=0,gen_div.ToggleCnt=2,gen_div.CntWidth=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
0.00	0.00

tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		9	0	0.00
TERNARY	27	2	0	0.00
TERNARY	81	2	0	0.00
IF	85	3	0	0.00
IF	97	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' or '../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	27	(test_en_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	81	((!step_down_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	85	if ((!rst_ni))
-2-:	88	if ((gen_div.cnt >= gen_div.limit))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	97	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		5	0	0.00
CONT_ASSIGN	27	1	0	0.00
ALWAYS	55	3	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' or '../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
27	0	1
55	0	1
56	0	1
58	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	2	0	0.00
Logical	2	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       27
 EXPRESSION (test_en_i ? '0 : step_down_req_i)
             ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	0	0.00
TERNARY	27	2	0	0.00
IF	55	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' or '../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	27	(test_en_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		12	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	81	1	0	0.00
ALWAYS	85	7	0	0.00
ALWAYS	97	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' or '../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
27	0	1
81	0	1
85	0	1
86	0	1
87	0	1
88	0	1
89	0	1
90	0	1
92	0	1
97	0	1
98	0	1
100	0	1

---

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	4	0	0.00
Logical	4	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       27
 EXPRESSION (test_en_i ? '0 : step_down_req_i)
             ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       81
 EXPRESSION (((!step_down_req)) ? (1'((gen_div.ToggleCnt - 1))) : ((((gen_div.ToggleCnt / 2) == 2) ? '0 : 1'(((gen_div.ToggleCnt / 2) - 1)))))
             ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		9	0	0.00
TERNARY	27	2	0	0.00
TERNARY	81	2	0	0.00
IF	85	3	0	0.00
IF	97	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' or '../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	27	(test_en_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	81	((!step_down_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	85	if ((!rst_ni))
-2-:	88	if ((gen_div.cnt >= gen_div.limit))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	97	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered