Unified Coverage Report :: Module :: prim_clock_meas

Module : prim_clock_meas

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_io_meas.u_meas	0.00	0.00	0.00		0.00	0.00
tb.dut.u_io_div2_meas.u_meas	0.00	0.00	0.00		0.00	0.00
tb.dut.u_io_div4_meas.u_meas	0.00	0.00	0.00		0.00	0.00
tb.dut.u_main_meas.u_meas	0.00	0.00	0.00		0.00	0.00
tb.dut.u_usb_meas.u_meas	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.u_io_meas.u_meas

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_io_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
ack_sync	0.00	0.00				0.00
gen_clk_timeout_chk.u_timeout_ref_to_clk	0.00	0.00	0.00			0.00
u_ref_meas_en_sync	0.00	0.00				0.00
u_sync_ref	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_io_div2_meas.u_meas

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_io_div2_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
ack_sync	0.00	0.00				0.00
gen_clk_timeout_chk.u_timeout_ref_to_clk	0.00	0.00	0.00			0.00
u_ref_meas_en_sync	0.00	0.00				0.00
u_sync_ref	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_io_div4_meas.u_meas

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_io_div4_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
ack_sync	0.00	0.00				0.00
gen_clk_timeout_chk.u_timeout_ref_to_clk	0.00	0.00	0.00			0.00
u_ref_meas_en_sync	0.00	0.00				0.00
u_sync_ref	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_main_meas.u_meas

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_main_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
ack_sync	0.00	0.00				0.00
gen_clk_timeout_chk.u_timeout_ref_to_clk	0.00	0.00	0.00			0.00
u_ref_meas_en_sync	0.00	0.00				0.00
u_sync_ref	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_usb_meas.u_meas

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_usb_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
ack_sync	0.00	0.00				0.00
gen_clk_timeout_chk.u_timeout_ref_to_clk	0.00	0.00	0.00			0.00
u_ref_meas_en_sync	0.00	0.00				0.00
u_sync_ref	0.00	0.00	0.00			0.00

Line Coverage for Module : prim_clock_meas

	Line No.	Total	Covered	Percent
TOTAL		32	0	0.00
ALWAYS	88	3	0	0.00
ALWAYS	100	12	0	0.00
CONT_ASSIGN	163	1	0	0.00
ALWAYS	183	13	0	0.00
CONT_ASSIGN	199	1	0	0.00
CONT_ASSIGN	200	1	0	0.00
CONT_ASSIGN	201	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	0	1
89	0	1
91	0	1
100	0	1
101	0	1
103	0	1
106	0	1
107	0	1
			==> MISSING_ELSE
112	0	1
113	0	1
			==> MISSING_ELSE
118	0	1
119	0	1
120	0	1
			==> MISSING_ELSE
125	0	1
126	0	1
			==> MISSING_ELSE
163	0	1
183	0	1
184	0	1
185	0	1
186	0	1
187	0	1
188	0	1
189	0	1
190	0	1
191	0	1
192	0	1
193	0	1
194	0	1
195	0	1
			==> MISSING_ELSE
199	0	1
200	0	1
201	0	1

---

Cond Coverage for Module : prim_clock_meas

	Total	Covered	Percent
Conditions	15	0	0.00
Logical	15	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       186
 EXPRESSION (((!cnt_en)) && ((|cnt)))
             -----1-----    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       199
 EXPRESSION (valid & ((|cnt)))
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       200
 EXPRESSION (valid_o & ((cnt > max_cnt) | cnt_ovfl))
             ---1---   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       200
 SUB-EXPRESSION ((cnt > max_cnt) | cnt_ovfl)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       201
 EXPRESSION (valid_o & (cnt < min_cnt))
             ---1---   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

FSM Coverage for Module : prim_clock_meas

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	0	0.00	(Not included in score)
Transitions	4	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StDisable	126	Not Covered
StDisabling	120	Not Covered
StEnable	113	Not Covered
StEnabling	107	Not Covered

transitions	Line No.	Covered	Tests
StDisable->StEnabling	107	Not Covered
StDisabling->StDisable	126	Not Covered
StEnable->StDisabling	120	Not Covered
StEnabling->StEnable	113	Not Covered

---

Branch Coverage for Module : prim_clock_meas

	Line No.	Total	Covered	Percent
Branches		16	0	0.00
IF	88	2	0	0.00
CASE	103	8	0	0.00
IF	183	6	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	103	case (state_q)
-2-:	106	if (en_i)
-3-:	112	if (en_ref_sync)
-4-:	119	if ((!en_i))
-5-:	125	if ((!en_ref_sync))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StDisable	1	-	-	-	Not Covered
StDisable	0	-	-	-	Not Covered
StEnabling	-	1	-	-	Not Covered
StEnabling	-	0	-	-	Not Covered
StEnable	-	-	1	-	Not Covered
StEnable	-	-	0	-	Not Covered
StDisabling	-	-	-	1	Not Covered
StDisabling	-	-	-	0	Not Covered

	LineNo.	Expression
-1-:	183	if ((!rst_ni))
-2-:	186	if (((!cnt_en) && (|cnt)))
-3-:	189	if (valid_o)
-4-:	192	if (cnt_ovfl)
-5-:	194	if (cnt_en)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Not Covered
0	1	-	-	-	Not Covered
0	0	1	-	-	Not Covered
0	0	0	1	-	Not Covered
0	0	0	0	1	Not Covered
0	0	0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_io_meas.u_meas

	Line No.	Total	Covered	Percent
TOTAL		32	0	0.00
ALWAYS	88	3	0	0.00
ALWAYS	100	12	0	0.00
CONT_ASSIGN	163	1	0	0.00
ALWAYS	183	13	0	0.00
CONT_ASSIGN	199	1	0	0.00
CONT_ASSIGN	200	1	0	0.00
CONT_ASSIGN	201	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	0	1
89	0	1
91	0	1
100	0	1
101	0	1
103	0	1
106	0	1
107	0	1
			==> MISSING_ELSE
112	0	1
113	0	1
			==> MISSING_ELSE
118	0	1
119	0	1
120	0	1
			==> MISSING_ELSE
125	0	1
126	0	1
			==> MISSING_ELSE
163	0	1
183	0	1
184	0	1
185	0	1
186	0	1
187	0	1
188	0	1
189	0	1
190	0	1
191	0	1
192	0	1
193	0	1
194	0	1
195	0	1
			==> MISSING_ELSE
199	0	1
200	0	1
201	0	1

---

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas

	Total	Covered	Percent
Conditions	15	0	0.00
Logical	15	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       186
 EXPRESSION (((!cnt_en)) && ((|cnt)))
             -----1-----    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       199
 EXPRESSION (valid & ((|cnt)))
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       200
 EXPRESSION (valid_o & ((cnt > max_cnt) | cnt_ovfl))
             ---1---   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       200
 SUB-EXPRESSION ((cnt > max_cnt) | cnt_ovfl)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       201
 EXPRESSION (valid_o & (cnt < min_cnt))
             ---1---   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

FSM Coverage for Instance : tb.dut.u_io_meas.u_meas

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	0	0.00	(Not included in score)
Transitions	4	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StDisable	126	Not Covered
StDisabling	120	Not Covered
StEnable	113	Not Covered
StEnabling	107	Not Covered

transitions	Line No.	Covered	Tests
StDisable->StEnabling	107	Not Covered
StDisabling->StDisable	126	Not Covered
StEnable->StDisabling	120	Not Covered
StEnabling->StEnable	113	Not Covered

---

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas

	Line No.	Total	Covered	Percent
Branches		16	0	0.00
IF	88	2	0	0.00
CASE	103	8	0	0.00
IF	183	6	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	103	case (state_q)
-2-:	106	if (en_i)
-3-:	112	if (en_ref_sync)
-4-:	119	if ((!en_i))
-5-:	125	if ((!en_ref_sync))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StDisable	1	-	-	-	Not Covered
StDisable	0	-	-	-	Not Covered
StEnabling	-	1	-	-	Not Covered
StEnabling	-	0	-	-	Not Covered
StEnable	-	-	1	-	Not Covered
StEnable	-	-	0	-	Not Covered
StDisabling	-	-	-	1	Not Covered
StDisabling	-	-	-	0	Not Covered

	LineNo.	Expression
-1-:	183	if ((!rst_ni))
-2-:	186	if (((!cnt_en) && (|cnt)))
-3-:	189	if (valid_o)
-4-:	192	if (cnt_ovfl)
-5-:	194	if (cnt_en)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Not Covered
0	1	-	-	-	Not Covered
0	0	1	-	-	Not Covered
0	0	0	1	-	Not Covered
0	0	0	0	1	Not Covered
0	0	0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas

	Line No.	Total	Covered	Percent
TOTAL		32	0	0.00
ALWAYS	88	3	0	0.00
ALWAYS	100	12	0	0.00
CONT_ASSIGN	163	1	0	0.00
ALWAYS	183	13	0	0.00
CONT_ASSIGN	199	1	0	0.00
CONT_ASSIGN	200	1	0	0.00
CONT_ASSIGN	201	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	0	1
89	0	1
91	0	1
100	0	1
101	0	1
103	0	1
106	0	1
107	0	1
			==> MISSING_ELSE
112	0	1
113	0	1
			==> MISSING_ELSE
118	0	1
119	0	1
120	0	1
			==> MISSING_ELSE
125	0	1
126	0	1
			==> MISSING_ELSE
163	0	1
183	0	1
184	0	1
185	0	1
186	0	1
187	0	1
188	0	1
189	0	1
190	0	1
191	0	1
192	0	1
193	0	1
194	0	1
195	0	1
			==> MISSING_ELSE
199	0	1
200	0	1
201	0	1

---

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas

	Total	Covered	Percent
Conditions	15	0	0.00
Logical	15	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       186
 EXPRESSION (((!cnt_en)) && ((|cnt)))
             -----1-----    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       199
 EXPRESSION (valid & ((|cnt)))
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       200
 EXPRESSION (valid_o & ((cnt > max_cnt) | cnt_ovfl))
             ---1---   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       200
 SUB-EXPRESSION ((cnt > max_cnt) | cnt_ovfl)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       201
 EXPRESSION (valid_o & (cnt < min_cnt))
             ---1---   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

FSM Coverage for Instance : tb.dut.u_io_div2_meas.u_meas

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	0	0.00	(Not included in score)
Transitions	4	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StDisable	126	Not Covered
StDisabling	120	Not Covered
StEnable	113	Not Covered
StEnabling	107	Not Covered

transitions	Line No.	Covered	Tests
StDisable->StEnabling	107	Not Covered
StDisabling->StDisable	126	Not Covered
StEnable->StDisabling	120	Not Covered
StEnabling->StEnable	113	Not Covered

---

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas

	Line No.	Total	Covered	Percent
Branches		16	0	0.00
IF	88	2	0	0.00
CASE	103	8	0	0.00
IF	183	6	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	103	case (state_q)
-2-:	106	if (en_i)
-3-:	112	if (en_ref_sync)
-4-:	119	if ((!en_i))
-5-:	125	if ((!en_ref_sync))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StDisable	1	-	-	-	Not Covered
StDisable	0	-	-	-	Not Covered
StEnabling	-	1	-	-	Not Covered
StEnabling	-	0	-	-	Not Covered
StEnable	-	-	1	-	Not Covered
StEnable	-	-	0	-	Not Covered
StDisabling	-	-	-	1	Not Covered
StDisabling	-	-	-	0	Not Covered

	LineNo.	Expression
-1-:	183	if ((!rst_ni))
-2-:	186	if (((!cnt_en) && (|cnt)))
-3-:	189	if (valid_o)
-4-:	192	if (cnt_ovfl)
-5-:	194	if (cnt_en)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Not Covered
0	1	-	-	-	Not Covered
0	0	1	-	-	Not Covered
0	0	0	1	-	Not Covered
0	0	0	0	1	Not Covered
0	0	0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas

	Line No.	Total	Covered	Percent
TOTAL		32	0	0.00
ALWAYS	88	3	0	0.00
ALWAYS	100	12	0	0.00
CONT_ASSIGN	163	1	0	0.00
ALWAYS	183	13	0	0.00
CONT_ASSIGN	199	1	0	0.00
CONT_ASSIGN	200	1	0	0.00
CONT_ASSIGN	201	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	0	1
89	0	1
91	0	1
100	0	1
101	0	1
103	0	1
106	0	1
107	0	1
			==> MISSING_ELSE
112	0	1
113	0	1
			==> MISSING_ELSE
118	0	1
119	0	1
120	0	1
			==> MISSING_ELSE
125	0	1
126	0	1
			==> MISSING_ELSE
163	0	1
183	0	1
184	0	1
185	0	1
186	0	1
187	0	1
188	0	1
189	0	1
190	0	1
191	0	1
192	0	1
193	0	1
194	0	1
195	0	1
			==> MISSING_ELSE
199	0	1
200	0	1
201	0	1

---

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas

	Total	Covered	Percent
Conditions	15	0	0.00
Logical	15	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       186
 EXPRESSION (((!cnt_en)) && ((|cnt)))
             -----1-----    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       199
 EXPRESSION (valid & ((|cnt)))
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       200
 EXPRESSION (valid_o & ((cnt > max_cnt) | cnt_ovfl))
             ---1---   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       200
 SUB-EXPRESSION ((cnt > max_cnt) | cnt_ovfl)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       201
 EXPRESSION (valid_o & (cnt < min_cnt))
             ---1---   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

FSM Coverage for Instance : tb.dut.u_io_div4_meas.u_meas

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	0	0.00	(Not included in score)
Transitions	4	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StDisable	126	Not Covered
StDisabling	120	Not Covered
StEnable	113	Not Covered
StEnabling	107	Not Covered

transitions	Line No.	Covered	Tests
StDisable->StEnabling	107	Not Covered
StDisabling->StDisable	126	Not Covered
StEnable->StDisabling	120	Not Covered
StEnabling->StEnable	113	Not Covered

---

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas

	Line No.	Total	Covered	Percent
Branches		16	0	0.00
IF	88	2	0	0.00
CASE	103	8	0	0.00
IF	183	6	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	103	case (state_q)
-2-:	106	if (en_i)
-3-:	112	if (en_ref_sync)
-4-:	119	if ((!en_i))
-5-:	125	if ((!en_ref_sync))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StDisable	1	-	-	-	Not Covered
StDisable	0	-	-	-	Not Covered
StEnabling	-	1	-	-	Not Covered
StEnabling	-	0	-	-	Not Covered
StEnable	-	-	1	-	Not Covered
StEnable	-	-	0	-	Not Covered
StDisabling	-	-	-	1	Not Covered
StDisabling	-	-	-	0	Not Covered

	LineNo.	Expression
-1-:	183	if ((!rst_ni))
-2-:	186	if (((!cnt_en) && (|cnt)))
-3-:	189	if (valid_o)
-4-:	192	if (cnt_ovfl)
-5-:	194	if (cnt_en)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Not Covered
0	1	-	-	-	Not Covered
0	0	1	-	-	Not Covered
0	0	0	1	-	Not Covered
0	0	0	0	1	Not Covered
0	0	0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_main_meas.u_meas

	Line No.	Total	Covered	Percent
TOTAL		32	0	0.00
ALWAYS	88	3	0	0.00
ALWAYS	100	12	0	0.00
CONT_ASSIGN	163	1	0	0.00
ALWAYS	183	13	0	0.00
CONT_ASSIGN	199	1	0	0.00
CONT_ASSIGN	200	1	0	0.00
CONT_ASSIGN	201	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	0	1
89	0	1
91	0	1
100	0	1
101	0	1
103	0	1
106	0	1
107	0	1
			==> MISSING_ELSE
112	0	1
113	0	1
			==> MISSING_ELSE
118	0	1
119	0	1
120	0	1
			==> MISSING_ELSE
125	0	1
126	0	1
			==> MISSING_ELSE
163	0	1
183	0	1
184	0	1
185	0	1
186	0	1
187	0	1
188	0	1
189	0	1
190	0	1
191	0	1
192	0	1
193	0	1
194	0	1
195	0	1
			==> MISSING_ELSE
199	0	1
200	0	1
201	0	1

---

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas

	Total	Covered	Percent
Conditions	15	0	0.00
Logical	15	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       186
 EXPRESSION (((!cnt_en)) && ((|cnt)))
             -----1-----    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       199
 EXPRESSION (valid & ((|cnt)))
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       200
 EXPRESSION (valid_o & ((cnt > max_cnt) | cnt_ovfl))
             ---1---   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       200
 SUB-EXPRESSION ((cnt > max_cnt) | cnt_ovfl)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       201
 EXPRESSION (valid_o & (cnt < min_cnt))
             ---1---   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

FSM Coverage for Instance : tb.dut.u_main_meas.u_meas

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	0	0.00	(Not included in score)
Transitions	4	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StDisable	126	Not Covered
StDisabling	120	Not Covered
StEnable	113	Not Covered
StEnabling	107	Not Covered

transitions	Line No.	Covered	Tests
StDisable->StEnabling	107	Not Covered
StDisabling->StDisable	126	Not Covered
StEnable->StDisabling	120	Not Covered
StEnabling->StEnable	113	Not Covered

---

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas

	Line No.	Total	Covered	Percent
Branches		16	0	0.00
IF	88	2	0	0.00
CASE	103	8	0	0.00
IF	183	6	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	103	case (state_q)
-2-:	106	if (en_i)
-3-:	112	if (en_ref_sync)
-4-:	119	if ((!en_i))
-5-:	125	if ((!en_ref_sync))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StDisable	1	-	-	-	Not Covered
StDisable	0	-	-	-	Not Covered
StEnabling	-	1	-	-	Not Covered
StEnabling	-	0	-	-	Not Covered
StEnable	-	-	1	-	Not Covered
StEnable	-	-	0	-	Not Covered
StDisabling	-	-	-	1	Not Covered
StDisabling	-	-	-	0	Not Covered

	LineNo.	Expression
-1-:	183	if ((!rst_ni))
-2-:	186	if (((!cnt_en) && (|cnt)))
-3-:	189	if (valid_o)
-4-:	192	if (cnt_ovfl)
-5-:	194	if (cnt_en)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Not Covered
0	1	-	-	-	Not Covered
0	0	1	-	-	Not Covered
0	0	0	1	-	Not Covered
0	0	0	0	1	Not Covered
0	0	0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas

	Line No.	Total	Covered	Percent
TOTAL		32	0	0.00
ALWAYS	88	3	0	0.00
ALWAYS	100	12	0	0.00
CONT_ASSIGN	163	1	0	0.00
ALWAYS	183	13	0	0.00
CONT_ASSIGN	199	1	0	0.00
CONT_ASSIGN	200	1	0	0.00
CONT_ASSIGN	201	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	0	1
89	0	1
91	0	1
100	0	1
101	0	1
103	0	1
106	0	1
107	0	1
			==> MISSING_ELSE
112	0	1
113	0	1
			==> MISSING_ELSE
118	0	1
119	0	1
120	0	1
			==> MISSING_ELSE
125	0	1
126	0	1
			==> MISSING_ELSE
163	0	1
183	0	1
184	0	1
185	0	1
186	0	1
187	0	1
188	0	1
189	0	1
190	0	1
191	0	1
192	0	1
193	0	1
194	0	1
195	0	1
			==> MISSING_ELSE
199	0	1
200	0	1
201	0	1

---

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas

	Total	Covered	Percent
Conditions	15	0	0.00
Logical	15	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       186
 EXPRESSION (((!cnt_en)) && ((|cnt)))
             -----1-----    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       199
 EXPRESSION (valid & ((|cnt)))
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       200
 EXPRESSION (valid_o & ((cnt > max_cnt) | cnt_ovfl))
             ---1---   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       200
 SUB-EXPRESSION ((cnt > max_cnt) | cnt_ovfl)
                 -------1-------   ----2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       201
 EXPRESSION (valid_o & (cnt < min_cnt))
             ---1---   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

FSM Coverage for Instance : tb.dut.u_usb_meas.u_meas

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	0	0.00	(Not included in score)
Transitions	4	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StDisable	126	Not Covered
StDisabling	120	Not Covered
StEnable	113	Not Covered
StEnabling	107	Not Covered

transitions	Line No.	Covered	Tests
StDisable->StEnabling	107	Not Covered
StDisabling->StDisable	126	Not Covered
StEnable->StDisabling	120	Not Covered
StEnabling->StEnable	113	Not Covered

---

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas

	Line No.	Total	Covered	Percent
Branches		16	0	0.00
IF	88	2	0	0.00
CASE	103	8	0	0.00
IF	183	6	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	103	case (state_q)
-2-:	106	if (en_i)
-3-:	112	if (en_ref_sync)
-4-:	119	if ((!en_i))
-5-:	125	if ((!en_ref_sync))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StDisable	1	-	-	-	Not Covered
StDisable	0	-	-	-	Not Covered
StEnabling	-	1	-	-	Not Covered
StEnabling	-	0	-	-	Not Covered
StEnable	-	-	1	-	Not Covered
StEnable	-	-	0	-	Not Covered
StDisabling	-	-	-	1	Not Covered
StDisabling	-	-	-	0	Not Covered

	LineNo.	Expression
-1-:	183	if ((!rst_ni))
-2-:	186	if (((!cnt_en) && (|cnt)))
-3-:	189	if (valid_o)
-4-:	192	if (cnt_ovfl)
-5-:	194	if (cnt_en)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Not Covered
0	1	-	-	-	Not Covered
0	0	1	-	-	Not Covered
0	0	0	1	-	Not Covered
0	0	0	0	1	Not Covered
0	0	0	0	0	Not Covered