| T178 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_stress_all_with_rand_reset.4160180878 |
|
|
Feb 09 08:19:59 AM UTC 25 |
Feb 09 08:30:09 AM UTC 25 |
41103207102 ps |
| T804 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_extclk.2120500690 |
|
|
Feb 09 08:30:06 AM UTC 25 |
Feb 09 08:30:10 AM UTC 25 |
113632503 ps |
| T805 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_peri.1059780958 |
|
|
Feb 09 08:30:10 AM UTC 25 |
Feb 09 08:30:14 AM UTC 25 |
166063551 ps |
| T806 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/47.clkmgr_stress_all.3243270816 |
|
|
Feb 09 08:29:42 AM UTC 25 |
Feb 09 08:30:16 AM UTC 25 |
4472564787 ps |
| T807 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/48.clkmgr_frequency_timeout.3873495825 |
|
|
Feb 09 08:29:48 AM UTC 25 |
Feb 09 08:30:16 AM UTC 25 |
2056215498 ps |
| T808 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_frequency.2923009490 |
|
|
Feb 09 08:30:07 AM UTC 25 |
Feb 09 08:30:17 AM UTC 25 |
943205100 ps |
| T809 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_stress_all_with_rand_reset.2559907462 |
|
|
Feb 09 08:18:10 AM UTC 25 |
Feb 09 08:30:17 AM UTC 25 |
53145656780 ps |
| T810 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_trans.2379841354 |
|
|
Feb 09 08:30:14 AM UTC 25 |
Feb 09 08:30:18 AM UTC 25 |
20552566 ps |
| T811 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_frequency_timeout.1537368784 |
|
|
Feb 09 08:30:10 AM UTC 25 |
Feb 09 08:30:20 AM UTC 25 |
1246814471 ps |
| T812 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_clk_status.1685133210 |
|
|
Feb 09 08:30:24 AM UTC 25 |
Feb 09 08:30:26 AM UTC 25 |
37048665 ps |
| T813 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.356053113 |
|
|
Feb 09 08:30:24 AM UTC 25 |
Feb 09 08:30:27 AM UTC 25 |
39351330 ps |
| T814 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_div_intersig_mubi.192045882 |
|
|
Feb 09 08:30:24 AM UTC 25 |
Feb 09 08:30:27 AM UTC 25 |
55218461 ps |
| T815 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_idle_intersig_mubi.1614704948 |
|
|
Feb 09 08:30:24 AM UTC 25 |
Feb 09 08:30:27 AM UTC 25 |
90382079 ps |
| T816 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.3233153568 |
|
|
Feb 09 08:30:24 AM UTC 25 |
Feb 09 08:30:27 AM UTC 25 |
78887732 ps |
| T817 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.3096586000 |
|
|
Feb 09 08:30:24 AM UTC 25 |
Feb 09 08:30:27 AM UTC 25 |
81465184 ps |
| T818 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_alert_test.3327237400 |
|
|
Feb 09 08:30:27 AM UTC 25 |
Feb 09 08:30:30 AM UTC 25 |
16912830 ps |
| T819 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_regwen.937628925 |
|
|
Feb 09 08:30:24 AM UTC 25 |
Feb 09 08:30:37 AM UTC 25 |
1495429194 ps |
| T820 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/48.clkmgr_stress_all.3987731009 |
|
|
Feb 09 08:30:01 AM UTC 25 |
Feb 09 08:30:52 AM UTC 25 |
6169946757 ps |
| T821 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/25.clkmgr_stress_all_with_rand_reset.1178175454 |
|
|
Feb 09 08:23:23 AM UTC 25 |
Feb 09 08:31:13 AM UTC 25 |
26174881651 ps |
| T822 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/22.clkmgr_stress_all_with_rand_reset.2268718533 |
|
|
Feb 09 08:22:37 AM UTC 25 |
Feb 09 08:31:15 AM UTC 25 |
28080023844 ps |
| T823 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_stress_all_with_rand_reset.4034333387 |
|
|
Feb 09 08:18:24 AM UTC 25 |
Feb 09 08:31:23 AM UTC 25 |
145757279440 ps |
| T824 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/33.clkmgr_stress_all_with_rand_reset.2765550048 |
|
|
Feb 09 08:25:54 AM UTC 25 |
Feb 09 08:31:41 AM UTC 25 |
17713020826 ps |
| T825 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_stress_all.975055839 |
|
|
Feb 09 08:30:27 AM UTC 25 |
Feb 09 08:31:43 AM UTC 25 |
8660002675 ps |
| T826 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_stress_all_with_rand_reset.2756505350 |
|
|
Feb 09 08:17:28 AM UTC 25 |
Feb 09 08:31:52 AM UTC 25 |
131399590807 ps |
| T179 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/40.clkmgr_stress_all_with_rand_reset.1867846324 |
|
|
Feb 09 08:27:49 AM UTC 25 |
Feb 09 08:32:21 AM UTC 25 |
16305479564 ps |
| T827 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/24.clkmgr_stress_all_with_rand_reset.1427067345 |
|
|
Feb 09 08:23:12 AM UTC 25 |
Feb 09 08:32:23 AM UTC 25 |
27660204237 ps |
| T828 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/21.clkmgr_stress_all_with_rand_reset.2971908090 |
|
|
Feb 09 08:22:27 AM UTC 25 |
Feb 09 08:33:10 AM UTC 25 |
54526123436 ps |
| T829 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/38.clkmgr_stress_all_with_rand_reset.3336724544 |
|
|
Feb 09 08:27:24 AM UTC 25 |
Feb 09 08:33:26 AM UTC 25 |
16917542428 ps |
| T830 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/29.clkmgr_stress_all_with_rand_reset.3977375582 |
|
|
Feb 09 08:24:46 AM UTC 25 |
Feb 09 08:34:32 AM UTC 25 |
31508598241 ps |
| T180 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/48.clkmgr_stress_all_with_rand_reset.2965900216 |
|
|
Feb 09 08:29:59 AM UTC 25 |
Feb 09 08:34:48 AM UTC 25 |
18967964834 ps |
| T831 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/19.clkmgr_stress_all_with_rand_reset.4165758434 |
|
|
Feb 09 08:21:37 AM UTC 25 |
Feb 09 08:35:16 AM UTC 25 |
39823462898 ps |
| T181 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/47.clkmgr_stress_all_with_rand_reset.874591757 |
|
|
Feb 09 08:29:41 AM UTC 25 |
Feb 09 08:35:54 AM UTC 25 |
52512601017 ps |
| T832 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/30.clkmgr_stress_all_with_rand_reset.2378897643 |
|
|
Feb 09 08:25:02 AM UTC 25 |
Feb 09 08:35:58 AM UTC 25 |
83250991407 ps |
| T833 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/32.clkmgr_stress_all_with_rand_reset.2862412781 |
|
|
Feb 09 08:25:38 AM UTC 25 |
Feb 09 08:36:40 AM UTC 25 |
29883784966 ps |
| T834 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/27.clkmgr_stress_all_with_rand_reset.4242328636 |
|
|
Feb 09 08:23:57 AM UTC 25 |
Feb 09 08:37:13 AM UTC 25 |
72070091639 ps |
| T182 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_stress_all_with_rand_reset.40198248 |
|
|
Feb 09 08:20:41 AM UTC 25 |
Feb 09 08:38:06 AM UTC 25 |
169332434463 ps |
| T183 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/41.clkmgr_stress_all_with_rand_reset.3619743333 |
|
|
Feb 09 08:28:00 AM UTC 25 |
Feb 09 08:38:42 AM UTC 25 |
94286803899 ps |
| T835 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_stress_all_with_rand_reset.1297255778 |
|
|
Feb 09 08:18:40 AM UTC 25 |
Feb 09 08:39:01 AM UTC 25 |
157476930387 ps |
| T836 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/23.clkmgr_stress_all_with_rand_reset.1136504441 |
|
|
Feb 09 08:22:56 AM UTC 25 |
Feb 09 08:39:03 AM UTC 25 |
59134441378 ps |
| T837 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/35.clkmgr_stress_all_with_rand_reset.3006263183 |
|
|
Feb 09 08:26:32 AM UTC 25 |
Feb 09 08:39:10 AM UTC 25 |
55698312621 ps |
| T838 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/28.clkmgr_stress_all_with_rand_reset.2341133814 |
|
|
Feb 09 08:24:14 AM UTC 25 |
Feb 09 08:39:43 AM UTC 25 |
92761541779 ps |
| T839 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/42.clkmgr_stress_all_with_rand_reset.2473100421 |
|
|
Feb 09 08:28:16 AM UTC 25 |
Feb 09 08:40:07 AM UTC 25 |
98136769723 ps |
| T184 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_stress_all_with_rand_reset.26254983 |
|
|
Feb 09 08:20:23 AM UTC 25 |
Feb 09 08:40:16 AM UTC 25 |
115062692561 ps |
| T185 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/46.clkmgr_stress_all_with_rand_reset.3710645601 |
|
|
Feb 09 08:29:24 AM UTC 25 |
Feb 09 08:40:55 AM UTC 25 |
40336365452 ps |
| T840 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_stress_all_with_rand_reset.3587974108 |
|
|
Feb 09 08:19:00 AM UTC 25 |
Feb 09 08:40:57 AM UTC 25 |
221139428707 ps |
| T841 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/36.clkmgr_stress_all_with_rand_reset.694414213 |
|
|
Feb 09 08:26:48 AM UTC 25 |
Feb 09 08:41:44 AM UTC 25 |
74219464416 ps |
| T842 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_stress_all_with_rand_reset.556593733 |
|
|
Feb 09 08:30:27 AM UTC 25 |
Feb 09 08:42:52 AM UTC 25 |
36303377553 ps |
| T843 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/37.clkmgr_stress_all_with_rand_reset.830397842 |
|
|
Feb 09 08:27:15 AM UTC 25 |
Feb 09 08:46:29 AM UTC 25 |
54254062586 ps |
| T844 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/44.clkmgr_stress_all_with_rand_reset.3828490511 |
|
|
Feb 09 08:28:47 AM UTC 25 |
Feb 09 08:46:32 AM UTC 25 |
47434673393 ps |
| T845 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/39.clkmgr_stress_all_with_rand_reset.2649271639 |
|
|
Feb 09 08:27:37 AM UTC 25 |
Feb 09 08:46:43 AM UTC 25 |
166699452610 ps |
| T846 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/43.clkmgr_stress_all_with_rand_reset.3909120378 |
|
|
Feb 09 08:28:30 AM UTC 25 |
Feb 09 08:47:06 AM UTC 25 |
257674016558 ps |
| T847 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/45.clkmgr_stress_all_with_rand_reset.1573504451 |
|
|
Feb 09 08:29:03 AM UTC 25 |
Feb 09 08:50:27 AM UTC 25 |
101054088964 ps |
| T848 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/34.clkmgr_stress_all_with_rand_reset.744890095 |
|
|
Feb 09 08:26:20 AM UTC 25 |
Feb 09 08:54:25 AM UTC 25 |
314008747013 ps |
| T849 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/31.clkmgr_stress_all_with_rand_reset.2047402077 |
|
|
Feb 09 08:25:19 AM UTC 25 |
Feb 09 08:57:33 AM UTC 25 |
368782660203 ps |
| T850 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/26.clkmgr_stress_all_with_rand_reset.1634245243 |
|
|
Feb 09 08:23:39 AM UTC 25 |
Feb 09 09:35:49 AM UTC 25 |
805310821168 ps |
| T78 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.787562386 |
|
|
Feb 09 08:30:28 AM UTC 25 |
Feb 09 08:30:32 AM UTC 25 |
198910962 ps |
| T123 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1869780782 |
|
|
Feb 09 08:30:31 AM UTC 25 |
Feb 09 08:30:35 AM UTC 25 |
70908572 ps |
| T851 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_intr_test.3554159753 |
|
|
Feb 09 08:30:33 AM UTC 25 |
Feb 09 08:30:35 AM UTC 25 |
19181366 ps |
| T79 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.879341447 |
|
|
Feb 09 08:30:28 AM UTC 25 |
Feb 09 08:30:36 AM UTC 25 |
547655258 ps |
| T852 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_tl_errors.27453560 |
|
|
Feb 09 08:30:29 AM UTC 25 |
Feb 09 08:30:38 AM UTC 25 |
759438501 ps |
| T107 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_rw.3755302611 |
|
|
Feb 09 08:30:36 AM UTC 25 |
Feb 09 08:30:38 AM UTC 25 |
17831772 ps |
| T853 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.4208681592 |
|
|
Feb 09 08:30:36 AM UTC 25 |
Feb 09 08:30:39 AM UTC 25 |
43867075 ps |
| T854 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.2627611125 |
|
|
Feb 09 08:30:37 AM UTC 25 |
Feb 09 08:30:44 AM UTC 25 |
214447930 ps |
| T108 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.3224375675 |
|
|
Feb 09 08:30:49 AM UTC 25 |
Feb 09 08:30:52 AM UTC 25 |
95025441 ps |
| T855 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.2787329818 |
|
|
Feb 09 08:30:49 AM UTC 25 |
Feb 09 08:30:53 AM UTC 25 |
173285818 ps |
| T856 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_aliasing.484724460 |
|
|
Feb 09 08:30:49 AM UTC 25 |
Feb 09 08:30:53 AM UTC 25 |
114961542 ps |
| T857 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_tl_errors.516129293 |
|
|
Feb 09 08:30:50 AM UTC 25 |
Feb 09 08:30:53 AM UTC 25 |
21110402 ps |
| T80 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.3772827481 |
|
|
Feb 09 08:30:50 AM UTC 25 |
Feb 09 08:30:54 AM UTC 25 |
86895119 ps |
| T858 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_intr_test.813807062 |
|
|
Feb 09 08:30:53 AM UTC 25 |
Feb 09 08:30:56 AM UTC 25 |
12513774 ps |
| T859 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.607252302 |
|
|
Feb 09 08:30:53 AM UTC 25 |
Feb 09 08:30:56 AM UTC 25 |
14512770 ps |
| T83 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.327073871 |
|
|
Feb 09 08:30:50 AM UTC 25 |
Feb 09 08:30:56 AM UTC 25 |
238588383 ps |
| T109 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_rw.456300270 |
|
|
Feb 09 08:30:54 AM UTC 25 |
Feb 09 08:30:57 AM UTC 25 |
40746327 ps |
| T124 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_tl_intg_err.1645099304 |
|
|
Feb 09 08:30:53 AM UTC 25 |
Feb 09 08:30:59 AM UTC 25 |
141133162 ps |
| T110 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_aliasing.2513130169 |
|
|
Feb 09 08:30:55 AM UTC 25 |
Feb 09 08:30:59 AM UTC 25 |
134116627 ps |
| T111 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.3171664270 |
|
|
Feb 09 08:30:57 AM UTC 25 |
Feb 09 08:31:00 AM UTC 25 |
50914230 ps |
| T860 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.1136577562 |
|
|
Feb 09 08:30:57 AM UTC 25 |
Feb 09 08:31:00 AM UTC 25 |
104700669 ps |
| T84 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.2854188303 |
|
|
Feb 09 08:30:57 AM UTC 25 |
Feb 09 08:31:01 AM UTC 25 |
129949260 ps |
| T861 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.1387712075 |
|
|
Feb 09 08:30:55 AM UTC 25 |
Feb 09 08:31:03 AM UTC 25 |
321322077 ps |
| T86 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.1925786532 |
|
|
Feb 09 08:30:58 AM UTC 25 |
Feb 09 08:31:03 AM UTC 25 |
144366229 ps |
| T862 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_intr_test.2407197257 |
|
|
Feb 09 08:31:01 AM UTC 25 |
Feb 09 08:31:04 AM UTC 25 |
13540230 ps |
| T863 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.4039956680 |
|
|
Feb 09 08:31:01 AM UTC 25 |
Feb 09 08:31:05 AM UTC 25 |
168317393 ps |
| T125 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3998694327 |
|
|
Feb 09 08:31:00 AM UTC 25 |
Feb 09 08:31:05 AM UTC 25 |
229232978 ps |
| T112 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_rw.4080021858 |
|
|
Feb 09 08:31:03 AM UTC 25 |
Feb 09 08:31:05 AM UTC 25 |
19967105 ps |
| T864 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_tl_errors.3826200862 |
|
|
Feb 09 08:31:00 AM UTC 25 |
Feb 09 08:31:05 AM UTC 25 |
89472814 ps |
| T113 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.65294621 |
|
|
Feb 09 08:31:05 AM UTC 25 |
Feb 09 08:31:08 AM UTC 25 |
83214385 ps |
| T865 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_aliasing.2744441637 |
|
|
Feb 09 08:31:04 AM UTC 25 |
Feb 09 08:31:08 AM UTC 25 |
113204682 ps |
| T866 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.3771133706 |
|
|
Feb 09 08:31:07 AM UTC 25 |
Feb 09 08:31:09 AM UTC 25 |
24190487 ps |
| T81 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.2251515990 |
|
|
Feb 09 08:31:07 AM UTC 25 |
Feb 09 08:31:10 AM UTC 25 |
130109656 ps |
| T867 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_intr_test.3219299379 |
|
|
Feb 09 08:31:09 AM UTC 25 |
Feb 09 08:31:11 AM UTC 25 |
27959775 ps |
| T88 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.1848011817 |
|
|
Feb 09 08:31:07 AM UTC 25 |
Feb 09 08:31:11 AM UTC 25 |
198999189 ps |
| T868 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.3914898707 |
|
|
Feb 09 08:31:10 AM UTC 25 |
Feb 09 08:31:12 AM UTC 25 |
14379685 ps |
| T869 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_tl_errors.649407556 |
|
|
Feb 09 08:31:07 AM UTC 25 |
Feb 09 08:31:14 AM UTC 25 |
460936083 ps |
| T130 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_tl_intg_err.239835774 |
|
|
Feb 09 08:31:09 AM UTC 25 |
Feb 09 08:31:14 AM UTC 25 |
98412556 ps |
| T870 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_rw.1494494153 |
|
|
Feb 09 08:31:11 AM UTC 25 |
Feb 09 08:31:14 AM UTC 25 |
35414555 ps |
| T871 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.3265155945 |
|
|
Feb 09 08:31:04 AM UTC 25 |
Feb 09 08:31:14 AM UTC 25 |
712054944 ps |
| T872 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_aliasing.420475837 |
|
|
Feb 09 08:31:13 AM UTC 25 |
Feb 09 08:31:16 AM UTC 25 |
44116872 ps |
| T873 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.3722492221 |
|
|
Feb 09 08:31:15 AM UTC 25 |
Feb 09 08:31:17 AM UTC 25 |
22018135 ps |
| T874 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_tl_errors.538580105 |
|
|
Feb 09 08:31:27 AM UTC 25 |
Feb 09 08:31:31 AM UTC 25 |
28726885 ps |
| T875 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.1341678681 |
|
|
Feb 09 08:31:15 AM UTC 25 |
Feb 09 08:31:18 AM UTC 25 |
39193125 ps |
| T876 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_intr_test.3295371209 |
|
|
Feb 09 08:31:16 AM UTC 25 |
Feb 09 08:31:18 AM UTC 25 |
24997831 ps |
| T138 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.2554617891 |
|
|
Feb 09 08:31:15 AM UTC 25 |
Feb 09 08:31:18 AM UTC 25 |
57002895 ps |
| T877 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_tl_errors.3433768385 |
|
|
Feb 09 08:31:15 AM UTC 25 |
Feb 09 08:31:18 AM UTC 25 |
74759737 ps |
| T878 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.3776371600 |
|
|
Feb 09 08:31:17 AM UTC 25 |
Feb 09 08:31:20 AM UTC 25 |
92448529 ps |
| T87 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.1457776255 |
|
|
Feb 09 08:31:15 AM UTC 25 |
Feb 09 08:31:21 AM UTC 25 |
360390485 ps |
| T879 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.411533605 |
|
|
Feb 09 08:31:13 AM UTC 25 |
Feb 09 08:31:21 AM UTC 25 |
277842992 ps |
| T129 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_tl_intg_err.3747007634 |
|
|
Feb 09 08:31:16 AM UTC 25 |
Feb 09 08:31:21 AM UTC 25 |
94095888 ps |
| T880 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_rw.2998373509 |
|
|
Feb 09 08:31:20 AM UTC 25 |
Feb 09 08:31:22 AM UTC 25 |
50407235 ps |
| T881 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_aliasing.2391296486 |
|
|
Feb 09 08:31:20 AM UTC 25 |
Feb 09 08:31:23 AM UTC 25 |
136472951 ps |
| T882 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.604873006 |
|
|
Feb 09 08:31:20 AM UTC 25 |
Feb 09 08:31:23 AM UTC 25 |
100996943 ps |
| T883 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.2281054146 |
|
|
Feb 09 08:31:20 AM UTC 25 |
Feb 09 08:31:24 AM UTC 25 |
242364411 ps |
| T82 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.1865764356 |
|
|
Feb 09 08:31:21 AM UTC 25 |
Feb 09 08:31:25 AM UTC 25 |
122888850 ps |
| T884 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.1234320159 |
|
|
Feb 09 08:31:20 AM UTC 25 |
Feb 09 08:31:26 AM UTC 25 |
141038631 ps |
| T885 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_tl_intg_err.1849033418 |
|
|
Feb 09 08:31:22 AM UTC 25 |
Feb 09 08:31:26 AM UTC 25 |
57776128 ps |
| T886 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_intr_test.2275267209 |
|
|
Feb 09 08:31:24 AM UTC 25 |
Feb 09 08:31:26 AM UTC 25 |
14624816 ps |
| T887 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_csr_rw.2638500758 |
|
|
Feb 09 08:31:24 AM UTC 25 |
Feb 09 08:31:26 AM UTC 25 |
26613481 ps |
| T888 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.1509610301 |
|
|
Feb 09 08:31:24 AM UTC 25 |
Feb 09 08:31:27 AM UTC 25 |
72044051 ps |
| T889 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.1419236700 |
|
|
Feb 09 08:31:24 AM UTC 25 |
Feb 09 08:31:27 AM UTC 25 |
62330486 ps |
| T85 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.3669005359 |
|
|
Feb 09 08:31:22 AM UTC 25 |
Feb 09 08:31:28 AM UTC 25 |
160275711 ps |
| T890 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_intr_test.2925975028 |
|
|
Feb 09 08:31:27 AM UTC 25 |
Feb 09 08:31:29 AM UTC 25 |
14849464 ps |
| T891 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_tl_errors.3214058133 |
|
|
Feb 09 08:31:22 AM UTC 25 |
Feb 09 08:31:29 AM UTC 25 |
640393698 ps |
| T892 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_csr_rw.3746928616 |
|
|
Feb 09 08:31:27 AM UTC 25 |
Feb 09 08:31:30 AM UTC 25 |
23307375 ps |
| T139 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.582673974 |
|
|
Feb 09 08:31:25 AM UTC 25 |
Feb 09 08:31:30 AM UTC 25 |
149167488 ps |
| T150 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.2403785764 |
|
|
Feb 09 08:31:27 AM UTC 25 |
Feb 09 08:31:31 AM UTC 25 |
96249350 ps |
| T140 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.268616082 |
|
|
Feb 09 08:31:28 AM UTC 25 |
Feb 09 08:31:32 AM UTC 25 |
98140010 ps |
| T893 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.1211769090 |
|
|
Feb 09 08:31:28 AM UTC 25 |
Feb 09 08:31:32 AM UTC 25 |
88307386 ps |
| T894 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_tl_intg_err.2058688 |
|
|
Feb 09 08:31:27 AM UTC 25 |
Feb 09 08:31:32 AM UTC 25 |
117258782 ps |
| T895 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.1214922529 |
|
|
Feb 09 08:31:28 AM UTC 25 |
Feb 09 08:31:32 AM UTC 25 |
115011401 ps |
| T896 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_intr_test.1029493629 |
|
|
Feb 09 08:31:34 AM UTC 25 |
Feb 09 08:31:37 AM UTC 25 |
16063526 ps |
| T897 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_csr_rw.716494406 |
|
|
Feb 09 08:31:34 AM UTC 25 |
Feb 09 08:31:37 AM UTC 25 |
13645938 ps |
| T898 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.3834963301 |
|
|
Feb 09 08:31:34 AM UTC 25 |
Feb 09 08:31:38 AM UTC 25 |
37154735 ps |
| T146 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.919618936 |
|
|
Feb 09 08:31:34 AM UTC 25 |
Feb 09 08:31:38 AM UTC 25 |
139020969 ps |
| T899 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.178650867 |
|
|
Feb 09 08:31:34 AM UTC 25 |
Feb 09 08:31:38 AM UTC 25 |
98112045 ps |
| T147 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.2106083687 |
|
|
Feb 09 08:31:34 AM UTC 25 |
Feb 09 08:31:39 AM UTC 25 |
90947094 ps |
| T900 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_tl_errors.1338389014 |
|
|
Feb 09 08:31:34 AM UTC 25 |
Feb 09 08:31:39 AM UTC 25 |
90554785 ps |
| T901 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_intr_test.3117502634 |
|
|
Feb 09 08:31:37 AM UTC 25 |
Feb 09 08:31:39 AM UTC 25 |
29920865 ps |
| T902 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_tl_intg_err.3869778744 |
|
|
Feb 09 08:31:34 AM UTC 25 |
Feb 09 08:31:39 AM UTC 25 |
423409832 ps |
| T141 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.1310914485 |
|
|
Feb 09 08:31:34 AM UTC 25 |
Feb 09 08:31:40 AM UTC 25 |
116362939 ps |
| T903 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_tl_errors.2071248418 |
|
|
Feb 09 08:31:36 AM UTC 25 |
Feb 09 08:31:40 AM UTC 25 |
44341637 ps |
| T904 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_csr_rw.356792220 |
|
|
Feb 09 08:31:39 AM UTC 25 |
Feb 09 08:31:42 AM UTC 25 |
64769929 ps |
| T905 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.714309859 |
|
|
Feb 09 08:31:39 AM UTC 25 |
Feb 09 08:31:42 AM UTC 25 |
100334308 ps |
| T200 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_tl_intg_err.3874831288 |
|
|
Feb 09 08:31:37 AM UTC 25 |
Feb 09 08:31:42 AM UTC 25 |
97796196 ps |
| T906 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_intr_test.4013021269 |
|
|
Feb 09 08:31:45 AM UTC 25 |
Feb 09 08:31:48 AM UTC 25 |
12874899 ps |
| T907 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_csr_rw.1748056502 |
|
|
Feb 09 08:31:45 AM UTC 25 |
Feb 09 08:31:48 AM UTC 25 |
25613750 ps |
| T908 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.1197433940 |
|
|
Feb 09 08:31:45 AM UTC 25 |
Feb 09 08:31:48 AM UTC 25 |
43677510 ps |
| T148 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.3182116647 |
|
|
Feb 09 08:31:45 AM UTC 25 |
Feb 09 08:31:48 AM UTC 25 |
103570414 ps |
| T145 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.1203795603 |
|
|
Feb 09 08:31:45 AM UTC 25 |
Feb 09 08:31:49 AM UTC 25 |
116039970 ps |
| T131 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_tl_intg_err.3698057823 |
|
|
Feb 09 08:31:45 AM UTC 25 |
Feb 09 08:31:50 AM UTC 25 |
167512928 ps |
| T909 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_tl_errors.1798738001 |
|
|
Feb 09 08:31:45 AM UTC 25 |
Feb 09 08:31:51 AM UTC 25 |
589876851 ps |
| T910 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.329951130 |
|
|
Feb 09 08:31:47 AM UTC 25 |
Feb 09 08:31:51 AM UTC 25 |
50456670 ps |
| T911 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.2230895561 |
|
|
Feb 09 08:31:47 AM UTC 25 |
Feb 09 08:31:51 AM UTC 25 |
72571210 ps |
| T912 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_intr_test.2003736220 |
|
|
Feb 09 08:31:49 AM UTC 25 |
Feb 09 08:31:51 AM UTC 25 |
15180382 ps |
| T913 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_csr_rw.2086803405 |
|
|
Feb 09 08:32:21 AM UTC 25 |
Feb 09 08:32:23 AM UTC 25 |
14320298 ps |
| T914 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_csr_rw.3698304980 |
|
|
Feb 09 08:31:49 AM UTC 25 |
Feb 09 08:31:51 AM UTC 25 |
18231940 ps |
| T126 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_tl_intg_err.2137605247 |
|
|
Feb 09 08:31:47 AM UTC 25 |
Feb 09 08:31:52 AM UTC 25 |
81210280 ps |
| T143 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.33542694 |
|
|
Feb 09 08:31:47 AM UTC 25 |
Feb 09 08:31:52 AM UTC 25 |
412699615 ps |
| T915 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.2299681393 |
|
|
Feb 09 08:31:49 AM UTC 25 |
Feb 09 08:31:52 AM UTC 25 |
107122346 ps |
| T916 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_tl_errors.1181286829 |
|
|
Feb 09 08:31:47 AM UTC 25 |
Feb 09 08:31:52 AM UTC 25 |
143658234 ps |
| T917 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.1326562526 |
|
|
Feb 09 08:31:47 AM UTC 25 |
Feb 09 08:31:53 AM UTC 25 |
150429411 ps |
| T918 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.2302421799 |
|
|
Feb 09 08:31:50 AM UTC 25 |
Feb 09 08:31:53 AM UTC 25 |
39473889 ps |
| T144 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.4269151594 |
|
|
Feb 09 08:31:50 AM UTC 25 |
Feb 09 08:31:54 AM UTC 25 |
77120660 ps |
| T919 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_intr_test.2936609199 |
|
|
Feb 09 08:31:53 AM UTC 25 |
Feb 09 08:31:56 AM UTC 25 |
37745152 ps |
| T920 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_csr_rw.1998226656 |
|
|
Feb 09 08:31:53 AM UTC 25 |
Feb 09 08:31:56 AM UTC 25 |
14707297 ps |
| T921 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.2278763772 |
|
|
Feb 09 08:31:50 AM UTC 25 |
Feb 09 08:31:56 AM UTC 25 |
138413239 ps |
| T922 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.1712721631 |
|
|
Feb 09 08:31:54 AM UTC 25 |
Feb 09 08:31:57 AM UTC 25 |
39487242 ps |
| T923 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.3892562135 |
|
|
Feb 09 08:31:54 AM UTC 25 |
Feb 09 08:31:57 AM UTC 25 |
101601813 ps |
| T924 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.3989867039 |
|
|
Feb 09 08:31:54 AM UTC 25 |
Feb 09 08:31:57 AM UTC 25 |
125964050 ps |
| T925 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_tl_errors.3227295321 |
|
|
Feb 09 08:31:53 AM UTC 25 |
Feb 09 08:31:58 AM UTC 25 |
118621733 ps |
| T133 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_tl_intg_err.2789554945 |
|
|
Feb 09 08:31:53 AM UTC 25 |
Feb 09 08:31:59 AM UTC 25 |
182092338 ps |
| T926 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_intr_test.3252917936 |
|
|
Feb 09 08:32:04 AM UTC 25 |
Feb 09 08:32:06 AM UTC 25 |
58924986 ps |
| T927 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_csr_rw.751646706 |
|
|
Feb 09 08:32:04 AM UTC 25 |
Feb 09 08:32:06 AM UTC 25 |
16540034 ps |
| T928 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_intr_test.2527463512 |
|
|
Feb 09 08:32:04 AM UTC 25 |
Feb 09 08:32:06 AM UTC 25 |
14260453 ps |
| T929 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.3190571442 |
|
|
Feb 09 08:32:04 AM UTC 25 |
Feb 09 08:32:06 AM UTC 25 |
52767749 ps |
| T930 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.1486587161 |
|
|
Feb 09 08:32:04 AM UTC 25 |
Feb 09 08:32:06 AM UTC 25 |
35034627 ps |
| T931 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.805318925 |
|
|
Feb 09 08:32:04 AM UTC 25 |
Feb 09 08:32:07 AM UTC 25 |
75537443 ps |
| T199 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_tl_intg_err.855256795 |
|
|
Feb 09 08:32:04 AM UTC 25 |
Feb 09 08:32:07 AM UTC 25 |
124642248 ps |
| T932 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_csr_rw.933185716 |
|
|
Feb 09 08:32:04 AM UTC 25 |
Feb 09 08:32:07 AM UTC 25 |
59125547 ps |
| T933 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.2066862616 |
|
|
Feb 09 08:32:04 AM UTC 25 |
Feb 09 08:32:07 AM UTC 25 |
55584319 ps |
| T142 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.2318444066 |
|
|
Feb 09 08:32:04 AM UTC 25 |
Feb 09 08:32:08 AM UTC 25 |
105289311 ps |
| T934 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.1981356465 |
|
|
Feb 09 08:32:04 AM UTC 25 |
Feb 09 08:32:08 AM UTC 25 |
144661290 ps |
| T935 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_tl_errors.2351483898 |
|
|
Feb 09 08:32:04 AM UTC 25 |
Feb 09 08:32:08 AM UTC 25 |
57260535 ps |
| T936 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_tl_errors.885230584 |
|
|
Feb 09 08:32:04 AM UTC 25 |
Feb 09 08:32:08 AM UTC 25 |
164718865 ps |
| T937 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_tl_intg_err.3543395905 |
|
|
Feb 09 08:32:04 AM UTC 25 |
Feb 09 08:32:10 AM UTC 25 |
519777400 ps |
| T127 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_tl_intg_err.3688724163 |
|
|
Feb 09 08:32:15 AM UTC 25 |
Feb 09 08:32:22 AM UTC 25 |
1448433677 ps |
| T938 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_intr_test.1499844157 |
|
|
Feb 09 08:32:09 AM UTC 25 |
Feb 09 08:32:12 AM UTC 25 |
25456903 ps |
| T939 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_csr_rw.41120175 |
|
|
Feb 09 08:32:09 AM UTC 25 |
Feb 09 08:32:12 AM UTC 25 |
45680500 ps |
| T132 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3357385707 |
|
|
Feb 09 08:32:09 AM UTC 25 |
Feb 09 08:32:12 AM UTC 25 |
57006443 ps |
| T940 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.987772073 |
|
|
Feb 09 08:32:09 AM UTC 25 |
Feb 09 08:32:12 AM UTC 25 |
32383634 ps |
| T941 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.928557344 |
|
|
Feb 09 08:32:09 AM UTC 25 |
Feb 09 08:32:12 AM UTC 25 |
40809400 ps |
| T942 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.3139554536 |
|
|
Feb 09 08:32:09 AM UTC 25 |
Feb 09 08:32:13 AM UTC 25 |
29492086 ps |
| T943 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.1698751080 |
|
|
Feb 09 08:32:09 AM UTC 25 |
Feb 09 08:32:13 AM UTC 25 |
154320567 ps |
| T944 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.2019409411 |
|
|
Feb 09 08:32:09 AM UTC 25 |
Feb 09 08:32:13 AM UTC 25 |
51252907 ps |
| T945 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_tl_errors.710190826 |
|
|
Feb 09 08:32:09 AM UTC 25 |
Feb 09 08:32:13 AM UTC 25 |
24914572 ps |
| T946 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.240826140 |
|
|
Feb 09 08:32:09 AM UTC 25 |
Feb 09 08:32:13 AM UTC 25 |
136124682 ps |
| T947 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.4048510055 |
|
|
Feb 09 08:32:09 AM UTC 25 |
Feb 09 08:32:13 AM UTC 25 |
92421509 ps |
| T948 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_tl_intg_err.747896411 |
|
|
Feb 09 08:32:10 AM UTC 25 |
Feb 09 08:32:14 AM UTC 25 |
65071361 ps |
| T949 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_intr_test.3226002492 |
|
|
Feb 09 08:32:12 AM UTC 25 |
Feb 09 08:32:14 AM UTC 25 |
14971196 ps |
| T950 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_tl_errors.1733153542 |
|
|
Feb 09 08:32:09 AM UTC 25 |
Feb 09 08:32:16 AM UTC 25 |
380837222 ps |
| T951 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_csr_rw.635095932 |
|
|
Feb 09 08:32:15 AM UTC 25 |
Feb 09 08:32:17 AM UTC 25 |
15713707 ps |
| T952 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_csr_rw.1123956243 |
|
|
Feb 09 08:32:15 AM UTC 25 |
Feb 09 08:32:17 AM UTC 25 |
18560727 ps |
| T953 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_intr_test.1276472991 |
|
|
Feb 09 08:32:15 AM UTC 25 |
Feb 09 08:32:17 AM UTC 25 |
17249753 ps |
| T954 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.1837304838 |
|
|
Feb 09 08:32:15 AM UTC 25 |
Feb 09 08:32:18 AM UTC 25 |
43632218 ps |
| T149 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.2439721728 |
|
|
Feb 09 08:32:15 AM UTC 25 |
Feb 09 08:32:18 AM UTC 25 |
254142869 ps |
| T955 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.95428730 |
|
|
Feb 09 08:32:15 AM UTC 25 |
Feb 09 08:32:19 AM UTC 25 |
82310107 ps |
| T956 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.2073577057 |
|
|
Feb 09 08:32:15 AM UTC 25 |
Feb 09 08:32:19 AM UTC 25 |
88021560 ps |
| T957 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.3218493757 |
|
|
Feb 09 08:32:15 AM UTC 25 |
Feb 09 08:32:19 AM UTC 25 |
87932857 ps |
| T958 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.738141679 |
|
|
Feb 09 08:32:15 AM UTC 25 |
Feb 09 08:32:20 AM UTC 25 |
394052877 ps |
| T959 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_tl_errors.729160410 |
|
|
Feb 09 08:32:15 AM UTC 25 |
Feb 09 08:32:20 AM UTC 25 |
441455710 ps |
| T960 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.2079641715 |
|
|
Feb 09 08:32:15 AM UTC 25 |
Feb 09 08:32:22 AM UTC 25 |
479890169 ps |
| T961 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_intr_test.293300012 |
|
|
Feb 09 08:32:21 AM UTC 25 |
Feb 09 08:32:23 AM UTC 25 |
60604748 ps |
| T962 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.442259291 |
|
|
Feb 09 08:32:21 AM UTC 25 |
Feb 09 08:32:24 AM UTC 25 |
109645416 ps |
| T963 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.583169713 |
|
|
Feb 09 08:32:21 AM UTC 25 |
Feb 09 08:32:24 AM UTC 25 |
44842878 ps |
| T964 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_tl_errors.2436550287 |
|
|
Feb 09 08:32:21 AM UTC 25 |
Feb 09 08:32:25 AM UTC 25 |
78418196 ps |
| T965 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.1342549198 |
|
|
Feb 09 08:32:21 AM UTC 25 |
Feb 09 08:32:25 AM UTC 25 |
142410285 ps |
| T966 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_intr_test.3243978078 |
|
|
Feb 09 08:32:23 AM UTC 25 |
Feb 09 08:32:25 AM UTC 25 |
38918142 ps |
| T967 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.3948255319 |
|
|
Feb 09 08:32:21 AM UTC 25 |
Feb 09 08:32:25 AM UTC 25 |
423732670 ps |
| T968 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.18759412 |
|
|
Feb 09 08:32:23 AM UTC 25 |
Feb 09 08:32:25 AM UTC 25 |
51223301 ps |
| T969 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_intg_err.2866464821 |
|
|
Feb 09 08:32:21 AM UTC 25 |
Feb 09 08:32:25 AM UTC 25 |
234726792 ps |
| T970 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.280805156 |
|
|
Feb 09 08:32:21 AM UTC 25 |
Feb 09 08:32:26 AM UTC 25 |
153642159 ps |
| T971 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_csr_rw.858602080 |
|
|
Feb 09 08:32:23 AM UTC 25 |
Feb 09 08:32:26 AM UTC 25 |
186689427 ps |
| T972 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.4043176644 |
|
|
Feb 09 08:32:23 AM UTC 25 |
Feb 09 08:32:26 AM UTC 25 |
205601474 ps |
| T973 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_errors.3584778104 |
|
|
Feb 09 08:32:21 AM UTC 25 |
Feb 09 08:32:26 AM UTC 25 |
74294918 ps |
| T974 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_intr_test.3558225209 |
|
|
Feb 09 08:32:25 AM UTC 25 |
Feb 09 08:32:28 AM UTC 25 |
38307845 ps |
| T975 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.1190215293 |
|
|
Feb 09 08:32:25 AM UTC 25 |
Feb 09 08:32:29 AM UTC 25 |
62710334 ps |
| T976 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.3884018556 |
|
|
Feb 09 08:32:25 AM UTC 25 |
Feb 09 08:32:29 AM UTC 25 |
198031544 ps |
| T128 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_intg_err.2045637396 |
|
|
Feb 09 08:32:25 AM UTC 25 |
Feb 09 08:32:29 AM UTC 25 |
74515656 ps |
| T977 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_csr_rw.3253642176 |
|
|
Feb 09 08:32:25 AM UTC 25 |
Feb 09 08:32:29 AM UTC 25 |
264779335 ps |
| T201 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_tl_intg_err.107031486 |
|
|
Feb 09 08:32:21 AM UTC 25 |
Feb 09 08:32:30 AM UTC 25 |
1309134999 ps |
| T978 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_errors.3863046523 |
|
|
Feb 09 08:32:25 AM UTC 25 |
Feb 09 08:32:30 AM UTC 25 |
403622324 ps |
| T979 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/20.clkmgr_intr_test.508013020 |
|
|
Feb 09 08:32:28 AM UTC 25 |
Feb 09 08:32:30 AM UTC 25 |
11688800 ps |
| T980 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/21.clkmgr_intr_test.1834889333 |
|
|
Feb 09 08:32:28 AM UTC 25 |
Feb 09 08:32:30 AM UTC 25 |
14073034 ps |
| T981 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/22.clkmgr_intr_test.2360205726 |
|
|
Feb 09 08:32:28 AM UTC 25 |
Feb 09 08:32:31 AM UTC 25 |
17060705 ps |
| T982 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/23.clkmgr_intr_test.4255162061 |
|
|
Feb 09 08:32:28 AM UTC 25 |
Feb 09 08:32:31 AM UTC 25 |
12873609 ps |
| T983 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/24.clkmgr_intr_test.3802763271 |
|
|
Feb 09 08:32:28 AM UTC 25 |
Feb 09 08:32:31 AM UTC 25 |
13192394 ps |
| T984 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/25.clkmgr_intr_test.3559142413 |
|
|
Feb 09 08:32:28 AM UTC 25 |
Feb 09 08:32:31 AM UTC 25 |
17674330 ps |
| T985 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/26.clkmgr_intr_test.951464485 |
|
|
Feb 09 08:32:28 AM UTC 25 |
Feb 09 08:32:31 AM UTC 25 |
84974799 ps |
| T986 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.2776825780 |
|
|
Feb 09 08:32:28 AM UTC 25 |
Feb 09 08:32:31 AM UTC 25 |
86125328 ps |
| T987 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/27.clkmgr_intr_test.947799198 |
|
|
Feb 09 08:32:28 AM UTC 25 |
Feb 09 08:32:31 AM UTC 25 |
50036386 ps |
| T988 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.4113768729 |
|
|
Feb 09 08:32:28 AM UTC 25 |
Feb 09 08:32:31 AM UTC 25 |
121757938 ps |
| T989 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/28.clkmgr_intr_test.525286367 |
|
|
Feb 09 08:32:29 AM UTC 25 |
Feb 09 08:32:32 AM UTC 25 |
40068911 ps |
| T990 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/32.clkmgr_intr_test.2563337079 |
|
|
Feb 09 08:32:33 AM UTC 25 |
Feb 09 08:32:35 AM UTC 25 |
29963572 ps |
| T991 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/29.clkmgr_intr_test.1499024507 |
|
|
Feb 09 08:32:33 AM UTC 25 |
Feb 09 08:32:35 AM UTC 25 |
20605520 ps |
| T992 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/31.clkmgr_intr_test.1903848500 |
|
|
Feb 09 08:32:33 AM UTC 25 |
Feb 09 08:32:35 AM UTC 25 |
12292554 ps |
| T993 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/30.clkmgr_intr_test.2209461995 |
|
|
Feb 09 08:32:33 AM UTC 25 |
Feb 09 08:32:35 AM UTC 25 |
13116872 ps |
| T994 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/33.clkmgr_intr_test.2261351784 |
|
|
Feb 09 08:32:33 AM UTC 25 |
Feb 09 08:32:35 AM UTC 25 |
17233226 ps |
| T995 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/34.clkmgr_intr_test.1316302021 |
|
|
Feb 09 08:32:33 AM UTC 25 |
Feb 09 08:32:35 AM UTC 25 |
13784252 ps |
| T996 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/41.clkmgr_intr_test.171834335 |
|
|
Feb 09 08:32:33 AM UTC 25 |
Feb 09 08:32:35 AM UTC 25 |
11457610 ps |
| T997 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/36.clkmgr_intr_test.157847051 |
|
|
Feb 09 08:32:33 AM UTC 25 |
Feb 09 08:32:36 AM UTC 25 |
13169725 ps |
| T998 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/37.clkmgr_intr_test.385012766 |
|
|
Feb 09 08:32:33 AM UTC 25 |
Feb 09 08:32:36 AM UTC 25 |
33483220 ps |
| T999 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/39.clkmgr_intr_test.3677157912 |
|
|
Feb 09 08:32:33 AM UTC 25 |
Feb 09 08:32:36 AM UTC 25 |
19923181 ps |
| T1000 |
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/43.clkmgr_intr_test.1376705094 |
|
|
Feb 09 08:32:33 AM UTC 25 |
Feb 09 08:32:36 AM UTC 25 |
24785698 ps |