Unified Coverage Report :: Tests

Tests

dashboard | hierarchy | modlist | groups | tests | asserts

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.02	98.80

Total test records in report: 1010

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T1001	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/38.clkmgr_intr_test.1050501170			Feb 09 08:32:33 AM UTC 25	Feb 09 08:32:36 AM UTC 25	17275466 ps
T1002	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/40.clkmgr_intr_test.2510120458			Feb 09 08:32:33 AM UTC 25	Feb 09 08:32:36 AM UTC 25	19416103 ps
T1003	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/35.clkmgr_intr_test.2326945903			Feb 09 08:32:33 AM UTC 25	Feb 09 08:32:36 AM UTC 25	95243318 ps
T1004	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/42.clkmgr_intr_test.935068583			Feb 09 08:32:33 AM UTC 25	Feb 09 08:32:36 AM UTC 25	28727748 ps
T1005	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/45.clkmgr_intr_test.1322216720			Feb 09 08:32:33 AM UTC 25	Feb 09 08:32:36 AM UTC 25	50574985 ps
T1006	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/44.clkmgr_intr_test.4188407137			Feb 09 08:32:33 AM UTC 25	Feb 09 08:32:36 AM UTC 25	13100299 ps
T1007	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/49.clkmgr_intr_test.2826196588			Feb 09 08:32:37 AM UTC 25	Feb 09 08:32:40 AM UTC 25	11072732 ps
T1008	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/46.clkmgr_intr_test.3802077319			Feb 09 08:32:37 AM UTC 25	Feb 09 08:32:40 AM UTC 25	23392637 ps
T1009	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/47.clkmgr_intr_test.3918059375			Feb 09 08:32:37 AM UTC 25	Feb 09 08:32:40 AM UTC 25	20566930 ps
T1010	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/48.clkmgr_intr_test.3852265892			Feb 09 08:32:37 AM UTC 25	Feb 09 08:32:40 AM UTC 25	76534814 ps

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.260141068
Short name	T31
Test name
Test status
Simulation time	13425035 ps
CPU time	1.13 seconds
Started	Feb 09 08:16:11 AM UTC 25
Finished	Feb 09 08:16:14 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260141068 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_handshake_intersig_mubi.260141068
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_frequency.3510443877
Short name	T10
Test name
Test status
Simulation time	2482005324 ps
CPU time	27.25 seconds
Started	Feb 09 08:16:15 AM UTC 25
Finished	Feb 09 08:16:43 AM UTC 25
Peak memory	210588 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510443877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.3510443877
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_regwen.3571871232
Short name	T1
Test name
Test status
Simulation time	493915025 ps
CPU time	4.47 seconds
Started	Feb 09 08:16:12 AM UTC 25
Finished	Feb 09 08:16:18 AM UTC 25
Peak memory	210372 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571871232 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.3571871232
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_stress_all.1692212339
Short name	T13
Test name
Test status
Simulation time	9376249050 ps
CPU time	54.04 seconds
Started	Feb 09 08:16:23 AM UTC 25
Finished	Feb 09 08:17:18 AM UTC 25
Peak memory	210652 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692212339 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all.1692212339
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_idle_intersig_mubi.3561078348
Short name	T32
Test name
Test status
Simulation time	22460195 ps
CPU time	1.39 seconds
Started	Feb 09 08:16:11 AM UTC 25
Finished	Feb 09 08:16:14 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561078348 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_idle_intersig_mubi.3561078348
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_stress_all_with_rand_reset.3262355730
Short name	T74
Test name
Test status
Simulation time	29201155212 ps
CPU time	295.16 seconds
Started	Feb 09 08:16:33 AM UTC 25
Finished	Feb 09 08:21:33 AM UTC 25
Peak memory	220172 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3262355730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.c lkmgr_stress_all_with_rand_reset.3262355730
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.3772827481
Short name	T80
Test name
Test status
Simulation time	86895119 ps
CPU time	2.84 seconds
Started	Feb 09 08:30:50 AM UTC 25
Finished	Feb 09 08:30:54 AM UTC 25
Peak memory	229032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772827481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors.3772827481
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_sec_cm.987578347
Short name	T55
Test name
Test status
Simulation time	586731592 ps
CPU time	6.73 seconds
Started	Feb 09 08:16:12 AM UTC 25
Finished	Feb 09 08:16:20 AM UTC 25
Peak memory	242716 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987578347 -assert nopostproc +UV M_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_sec_cm.987578347
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_clk_status.3238152432
Short name	T28
Test name
Test status
Simulation time	13774458 ps
CPU time	1.12 seconds
Started	Feb 09 08:16:10 AM UTC 25
Finished	Feb 09 08:16:12 AM UTC 25
Peak memory	208816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238152432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.3238152432
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_div_intersig_mubi.1654407331
Short name	T19
Test name
Test status
Simulation time	30269995 ps
CPU time	1.39 seconds
Started	Feb 09 08:16:21 AM UTC 25
Finished	Feb 09 08:16:24 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654407331 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_div_intersig_mubi.1654407331
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_peri.430009267
Short name	T6
Test name
Test status
Simulation time	14622230 ps
CPU time	1.04 seconds
Started	Feb 09 08:16:10 AM UTC 25
Finished	Feb 09 08:16:12 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430009267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.430009267
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_tl_intg_err.239835774
Short name	T130
Test name
Test status
Simulation time	98412556 ps
CPU time	3.7 seconds
Started	Feb 09 08:31:09 AM UTC 25
Finished	Feb 09 08:31:14 AM UTC 25
Peak memory	212372 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239835774 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_tl_intg_err.239835774
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.582673974
Short name	T139
Test name
Test status
Simulation time	149167488 ps
CPU time	3.9 seconds
Started	Feb 09 08:31:25 AM UTC 25
Finished	Feb 09 08:31:30 AM UTC 25
Peak memory	229312 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582673974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors.582673974
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_alert_test.227812304
Short name	T69
Test name
Test status
Simulation time	80647657 ps
CPU time	1.43 seconds
Started	Feb 09 08:16:14 AM UTC 25
Finished	Feb 09 08:16:16 AM UTC 25
Peak memory	209916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227812304 -assert nopostproc +U VM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_alert_test.227812304
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.2866060893
Short name	T33
Test name
Test status
Simulation time	70308433 ps
CPU time	1.47 seconds
Started	Feb 09 08:16:11 AM UTC 25
Finished	Feb 09 08:16:14 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866060893 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_lc_clk_byp_req_intersig_mubi.2866060893
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/18.clkmgr_regwen.2063396625
Short name	T7
Test name
Test status
Simulation time	839038796 ps
CPU time	8.73 seconds
Started	Feb 09 08:21:20 AM UTC 25
Finished	Feb 09 08:21:30 AM UTC 25
Peak memory	210648 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063396625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.2063396625
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.879341447
Short name	T79
Test name
Test status
Simulation time	547655258 ps
CPU time	6.4 seconds
Started	Feb 09 08:30:28 AM UTC 25
Finished	Feb 09 08:30:36 AM UTC 25
Peak memory	221888 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879341 447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.879341447
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_stress_all_with_rand_reset.4031718209
Short name	T72
Test name
Test status
Simulation time	56137148998 ps
CPU time	631.5 seconds
Started	Feb 09 08:17:14 AM UTC 25
Finished	Feb 09 08:27:53 AM UTC 25
Peak memory	222220 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=4031718209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.c lkmgr_stress_all_with_rand_reset.4031718209
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_tl_intg_err.107031486
Short name	T201
Test name
Test status
Simulation time	1309134999 ps
CPU time	7.68 seconds
Started	Feb 09 08:32:21 AM UTC 25
Finished	Feb 09 08:32:30 AM UTC 25
Peak memory	212568 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107031486 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_tl_intg_err.107031486
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_idle_intersig_mubi.3472937462
Short name	T274
Test name
Test status
Simulation time	34599491 ps
CPU time	1.06 seconds
Started	Feb 09 08:18:53 AM UTC 25
Finished	Feb 09 08:18:55 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472937462 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_idle_intersig_mubi.3472937462
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.2439721728
Short name	T149
Test name
Test status
Simulation time	254142869 ps
CPU time	2.21 seconds
Started	Feb 09 08:32:15 AM UTC 25
Finished	Feb 09 08:32:18 AM UTC 25
Peak memory	212680 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439721728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors.2439721728
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.3907405656
Short name	T58
Test name
Test status
Simulation time	19011829 ps
CPU time	1.28 seconds
Started	Feb 09 08:16:20 AM UTC 25
Finished	Feb 09 08:16:23 AM UTC 25
Peak memory	210096 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907405656 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_handshake_intersig_mubi.3907405656
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_tl_intg_err.2137605247
Short name	T126
Test name
Test status
Simulation time	81210280 ps
CPU time	2.84 seconds
Started	Feb 09 08:31:47 AM UTC 25
Finished	Feb 09 08:31:52 AM UTC 25
Peak memory	212344 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137605247 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_tl_intg_err.2137605247
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3998694327
Short name	T125
Test name
Test status
Simulation time	229232978 ps
CPU time	3.52 seconds
Started	Feb 09 08:31:00 AM UTC 25
Finished	Feb 09 08:31:05 AM UTC 25
Peak memory	212276 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998694327 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_tl_intg_err.3998694327
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_tl_intg_err.3747007634
Short name	T129
Test name
Test status
Simulation time	94095888 ps
CPU time	3.65 seconds
Started	Feb 09 08:31:16 AM UTC 25
Finished	Feb 09 08:31:21 AM UTC 25
Peak memory	212348 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747007634 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_tl_intg_err.3747007634
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_aliasing.484724460
Short name	T856
Test name
Test status
Simulation time	114961542 ps
CPU time	3 seconds
Started	Feb 09 08:30:49 AM UTC 25
Finished	Feb 09 08:30:53 AM UTC 25
Peak memory	212544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484724460 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_aliasing.484724460
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.2627611125
Short name	T854
Test name
Test status
Simulation time	214447930 ps
CPU time	5.75 seconds
Started	Feb 09 08:30:37 AM UTC 25
Finished	Feb 09 08:30:44 AM UTC 25
Peak memory	212316 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627611125 -assert nopostpr oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_bit_bash.2627611125
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.4208681592
Short name	T853
Test name
Test status
Simulation time	43867075 ps
CPU time	1.42 seconds
Started	Feb 09 08:30:36 AM UTC 25
Finished	Feb 09 08:30:39 AM UTC 25
Peak memory	211684 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208681592 -assert nopostpr oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_hw_reset.4208681592
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.2787329818
Short name	T855
Test name
Test status
Simulation time	173285818 ps
CPU time	2.57 seconds
Started	Feb 09 08:30:49 AM UTC 25
Finished	Feb 09 08:30:53 AM UTC 25
Peak memory	212120 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_cl ear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=2787329818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem _rw_with_rand_reset.2787329818
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_rw.3755302611
Short name	T107
Test name
Test status
Simulation time	17831772 ps
CPU time	1.31 seconds
Started	Feb 09 08:30:36 AM UTC 25
Finished	Feb 09 08:30:38 AM UTC 25
Peak memory	211808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755302611 -assert nopostproc +UV M_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_rw.3755302611
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_intr_test.3554159753
Short name	T851
Test name
Test status
Simulation time	19181366 ps
CPU time	0.99 seconds
Started	Feb 09 08:30:33 AM UTC 25
Finished	Feb 09 08:30:35 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554159753 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_intr_test.3554159753
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.3224375675
Short name	T108
Test name
Test status
Simulation time	95025441 ps
CPU time	2.12 seconds
Started	Feb 09 08:30:49 AM UTC 25
Finished	Feb 09 08:30:52 AM UTC 25
Peak memory	212272 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224375675 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_same_csr_outstanding.3224375675
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.787562386
Short name	T78
Test name
Test status
Simulation time	198910962 ps
CPU time	2.63 seconds
Started	Feb 09 08:30:28 AM UTC 25
Finished	Feb 09 08:30:32 AM UTC 25
Peak memory	212408 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787562386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors.787562386
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_tl_errors.27453560
Short name	T852
Test name
Test status
Simulation time	759438501 ps
CPU time	7 seconds
Started	Feb 09 08:30:29 AM UTC 25
Finished	Feb 09 08:30:38 AM UTC 25
Peak memory	212384 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27453560 -assert nopostproc +UVM_TES TNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_tl_errors.27453560
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1869780782
Short name	T123
Test name
Test status
Simulation time	70908572 ps
CPU time	2.85 seconds
Started	Feb 09 08:30:31 AM UTC 25
Finished	Feb 09 08:30:35 AM UTC 25
Peak memory	212540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869780782 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_tl_intg_err.1869780782
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_aliasing.2513130169
Short name	T110
Test name
Test status
Simulation time	134116627 ps
CPU time	3.38 seconds
Started	Feb 09 08:30:55 AM UTC 25
Finished	Feb 09 08:30:59 AM UTC 25
Peak memory	212348 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513130169 -assert nopostpr oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_aliasing.2513130169
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.1387712075
Short name	T861
Test name
Test status
Simulation time	321322077 ps
CPU time	7.05 seconds
Started	Feb 09 08:30:55 AM UTC 25
Finished	Feb 09 08:31:03 AM UTC 25
Peak memory	212612 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387712075 -assert nopostpr oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_bit_bash.1387712075
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.607252302
Short name	T859
Test name
Test status
Simulation time	14512770 ps
CPU time	1.12 seconds
Started	Feb 09 08:30:53 AM UTC 25
Finished	Feb 09 08:30:56 AM UTC 25
Peak memory	211744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607252302 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_hw_reset.607252302
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.1136577562
Short name	T860
Test name
Test status
Simulation time	104700669 ps
CPU time	2.49 seconds
Started	Feb 09 08:30:57 AM UTC 25
Finished	Feb 09 08:31:00 AM UTC 25
Peak memory	212520 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_cl ear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=1136577562 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem _rw_with_rand_reset.1136577562
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_rw.456300270
Short name	T109
Test name
Test status
Simulation time	40746327 ps
CPU time	1.26 seconds
Started	Feb 09 08:30:54 AM UTC 25
Finished	Feb 09 08:30:57 AM UTC 25
Peak memory	211744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456300270 -assert nopostproc +UVM _TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_rw.456300270
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_intr_test.813807062
Short name	T858
Test name
Test status
Simulation time	12513774 ps
CPU time	1.06 seconds
Started	Feb 09 08:30:53 AM UTC 25
Finished	Feb 09 08:30:56 AM UTC 25
Peak memory	210600 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813807062 -assert nopostproc +UVM_TE STNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_intr_test.813807062
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.3171664270
Short name	T111
Test name
Test status
Simulation time	50914230 ps
CPU time	2.3 seconds
Started	Feb 09 08:30:57 AM UTC 25
Finished	Feb 09 08:31:00 AM UTC 25
Peak memory	212608 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171664270 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_same_csr_outstanding.3171664270
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.327073871
Short name	T83
Test name
Test status
Simulation time	238588383 ps
CPU time	4.84 seconds
Started	Feb 09 08:30:50 AM UTC 25
Finished	Feb 09 08:30:56 AM UTC 25
Peak memory	221976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327073 871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.327073871
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_tl_errors.516129293
Short name	T857
Test name
Test status
Simulation time	21110402 ps
CPU time	1.88 seconds
Started	Feb 09 08:30:50 AM UTC 25
Finished	Feb 09 08:30:53 AM UTC 25
Peak memory	211932 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516129293 -assert nopostproc +UVM_TE STNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_tl_errors.516129293
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_tl_intg_err.1645099304
Short name	T124
Test name
Test status
Simulation time	141133162 ps
CPU time	4.31 seconds
Started	Feb 09 08:30:53 AM UTC 25
Finished	Feb 09 08:30:59 AM UTC 25
Peak memory	212064 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645099304 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_tl_intg_err.1645099304
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.2302421799
Short name	T918
Test name
Test status
Simulation time	39473889 ps
CPU time	1.92 seconds
Started	Feb 09 08:31:50 AM UTC 25
Finished	Feb 09 08:31:53 AM UTC 25
Peak memory	211596 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_cl ear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=2302421799 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_me m_rw_with_rand_reset.2302421799
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_csr_rw.3698304980
Short name	T914
Test name
Test status
Simulation time	18231940 ps
CPU time	0.92 seconds
Started	Feb 09 08:31:49 AM UTC 25
Finished	Feb 09 08:31:51 AM UTC 25
Peak memory	211620 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698304980 -assert nopostproc +UV M_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_rw.3698304980
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_intr_test.2003736220
Short name	T912
Test name
Test status
Simulation time	15180382 ps
CPU time	1.04 seconds
Started	Feb 09 08:31:49 AM UTC 25
Finished	Feb 09 08:31:51 AM UTC 25
Peak memory	211244 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003736220 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_intr_test.2003736220
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.2299681393
Short name	T915
Test name
Test status
Simulation time	107122346 ps
CPU time	1.68 seconds
Started	Feb 09 08:31:49 AM UTC 25
Finished	Feb 09 08:31:52 AM UTC 25
Peak memory	211808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299681393 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_same_csr_outstanding.2299681393
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.33542694
Short name	T143
Test name
Test status
Simulation time	412699615 ps
CPU time	3.29 seconds
Started	Feb 09 08:31:47 AM UTC 25
Finished	Feb 09 08:31:52 AM UTC 25
Peak memory	212412 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33542694 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors.33542694
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.1326562526
Short name	T917
Test name
Test status
Simulation time	150429411 ps
CPU time	4.39 seconds
Started	Feb 09 08:31:47 AM UTC 25
Finished	Feb 09 08:31:53 AM UTC 25
Peak memory	221904 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132656 2526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.1326562526
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_tl_errors.1181286829
Short name	T916
Test name
Test status
Simulation time	143658234 ps
CPU time	3.64 seconds
Started	Feb 09 08:31:47 AM UTC 25
Finished	Feb 09 08:31:52 AM UTC 25
Peak memory	212784 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181286829 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_tl_errors.1181286829
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.3989867039
Short name	T924
Test name
Test status
Simulation time	125964050 ps
CPU time	2.48 seconds
Started	Feb 09 08:31:54 AM UTC 25
Finished	Feb 09 08:31:57 AM UTC 25
Peak memory	212200 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_cl ear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=3989867039 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_me m_rw_with_rand_reset.3989867039
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_csr_rw.1998226656
Short name	T920
Test name
Test status
Simulation time	14707297 ps
CPU time	1.13 seconds
Started	Feb 09 08:31:53 AM UTC 25
Finished	Feb 09 08:31:56 AM UTC 25
Peak memory	211808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998226656 -assert nopostproc +UV M_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_rw.1998226656
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_intr_test.2936609199
Short name	T919
Test name
Test status
Simulation time	37745152 ps
CPU time	1.11 seconds
Started	Feb 09 08:31:53 AM UTC 25
Finished	Feb 09 08:31:56 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936609199 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_intr_test.2936609199
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.1712721631
Short name	T922
Test name
Test status
Simulation time	39487242 ps
CPU time	1.78 seconds
Started	Feb 09 08:31:54 AM UTC 25
Finished	Feb 09 08:31:57 AM UTC 25
Peak memory	211872 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712721631 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_same_csr_outstanding.1712721631
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.4269151594
Short name	T144
Test name
Test status
Simulation time	77120660 ps
CPU time	2.05 seconds
Started	Feb 09 08:31:50 AM UTC 25
Finished	Feb 09 08:31:54 AM UTC 25
Peak memory	212496 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269151594 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors.4269151594
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.2278763772
Short name	T921
Test name
Test status
Simulation time	138413239 ps
CPU time	4.29 seconds
Started	Feb 09 08:31:50 AM UTC 25
Finished	Feb 09 08:31:56 AM UTC 25
Peak memory	222100 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227876 3772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.2278763772
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_tl_errors.3227295321
Short name	T925
Test name
Test status
Simulation time	118621733 ps
CPU time	3.21 seconds
Started	Feb 09 08:31:53 AM UTC 25
Finished	Feb 09 08:31:58 AM UTC 25
Peak memory	212712 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227295321 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_tl_errors.3227295321
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_tl_intg_err.2789554945
Short name	T133
Test name
Test status
Simulation time	182092338 ps
CPU time	4.28 seconds
Started	Feb 09 08:31:53 AM UTC 25
Finished	Feb 09 08:31:59 AM UTC 25
Peak memory	212352 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789554945 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_tl_intg_err.2789554945
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.805318925
Short name	T931
Test name
Test status
Simulation time	75537443 ps
CPU time	1.49 seconds
Started	Feb 09 08:32:04 AM UTC 25
Finished	Feb 09 08:32:07 AM UTC 25
Peak memory	211680 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_cl ear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=805318925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem _rw_with_rand_reset.805318925
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_csr_rw.751646706
Short name	T927
Test name
Test status
Simulation time	16540034 ps
CPU time	1.07 seconds
Started	Feb 09 08:32:04 AM UTC 25
Finished	Feb 09 08:32:06 AM UTC 25
Peak memory	211744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751646706 -assert nopostproc +UVM _TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_rw.751646706
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_intr_test.3252917936
Short name	T926
Test name
Test status
Simulation time	58924986 ps
CPU time	1.05 seconds
Started	Feb 09 08:32:04 AM UTC 25
Finished	Feb 09 08:32:06 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252917936 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_intr_test.3252917936
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.1486587161
Short name	T930
Test name
Test status
Simulation time	35034627 ps
CPU time	1.38 seconds
Started	Feb 09 08:32:04 AM UTC 25
Finished	Feb 09 08:32:06 AM UTC 25
Peak memory	211808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486587161 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_same_csr_outstanding.1486587161
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.3892562135
Short name	T923
Test name
Test status
Simulation time	101601813 ps
CPU time	2.3 seconds
Started	Feb 09 08:31:54 AM UTC 25
Finished	Feb 09 08:31:57 AM UTC 25
Peak memory	212344 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892562135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors.3892562135
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.3190571442
Short name	T929
Test name
Test status
Simulation time	52767749 ps
CPU time	1.6 seconds
Started	Feb 09 08:32:04 AM UTC 25
Finished	Feb 09 08:32:06 AM UTC 25
Peak memory	228832 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319057 1442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.3190571442
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_tl_errors.885230584
Short name	T936
Test name
Test status
Simulation time	164718865 ps
CPU time	3.53 seconds
Started	Feb 09 08:32:04 AM UTC 25
Finished	Feb 09 08:32:08 AM UTC 25
Peak memory	212708 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885230584 -assert nopostproc +UVM_TE STNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_tl_errors.885230584
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_tl_intg_err.855256795
Short name	T199
Test name
Test status
Simulation time	124642248 ps
CPU time	1.84 seconds
Started	Feb 09 08:32:04 AM UTC 25
Finished	Feb 09 08:32:07 AM UTC 25
Peak memory	211940 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855256795 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_tl_intg_err.855256795
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.928557344
Short name	T941
Test name
Test status
Simulation time	40809400 ps
CPU time	2.01 seconds
Started	Feb 09 08:32:09 AM UTC 25
Finished	Feb 09 08:32:12 AM UTC 25
Peak memory	211680 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_cl ear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=928557344 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem _rw_with_rand_reset.928557344
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_csr_rw.933185716
Short name	T932
Test name
Test status
Simulation time	59125547 ps
CPU time	1.45 seconds
Started	Feb 09 08:32:04 AM UTC 25
Finished	Feb 09 08:32:07 AM UTC 25
Peak memory	211744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933185716 -assert nopostproc +UVM _TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_rw.933185716
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_intr_test.2527463512
Short name	T928
Test name
Test status
Simulation time	14260453 ps
CPU time	0.98 seconds
Started	Feb 09 08:32:04 AM UTC 25
Finished	Feb 09 08:32:06 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527463512 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_intr_test.2527463512
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.2066862616
Short name	T933
Test name
Test status
Simulation time	55584319 ps
CPU time	1.75 seconds
Started	Feb 09 08:32:04 AM UTC 25
Finished	Feb 09 08:32:07 AM UTC 25
Peak memory	211560 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066862616 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_same_csr_outstanding.2066862616
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.2318444066
Short name	T142
Test name
Test status
Simulation time	105289311 ps
CPU time	2.34 seconds
Started	Feb 09 08:32:04 AM UTC 25
Finished	Feb 09 08:32:08 AM UTC 25
Peak memory	221932 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318444066 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors.2318444066
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.1981356465
Short name	T934
Test name
Test status
Simulation time	144661290 ps
CPU time	2.67 seconds
Started	Feb 09 08:32:04 AM UTC 25
Finished	Feb 09 08:32:08 AM UTC 25
Peak memory	212612 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198135 6465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.1981356465
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_tl_errors.2351483898
Short name	T935
Test name
Test status
Simulation time	57260535 ps
CPU time	2.75 seconds
Started	Feb 09 08:32:04 AM UTC 25
Finished	Feb 09 08:32:08 AM UTC 25
Peak memory	212312 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351483898 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_tl_errors.2351483898
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_tl_intg_err.3543395905
Short name	T937
Test name
Test status
Simulation time	519777400 ps
CPU time	5.03 seconds
Started	Feb 09 08:32:04 AM UTC 25
Finished	Feb 09 08:32:10 AM UTC 25
Peak memory	212660 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543395905 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_tl_intg_err.3543395905
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.3139554536
Short name	T942
Test name
Test status
Simulation time	29492086 ps
CPU time	1.66 seconds
Started	Feb 09 08:32:09 AM UTC 25
Finished	Feb 09 08:32:13 AM UTC 25
Peak memory	211740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_cl ear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=3139554536 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_me m_rw_with_rand_reset.3139554536
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_csr_rw.41120175
Short name	T939
Test name
Test status
Simulation time	45680500 ps
CPU time	1.42 seconds
Started	Feb 09 08:32:09 AM UTC 25
Finished	Feb 09 08:32:12 AM UTC 25
Peak memory	211744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41120175 -assert nopostproc +UVM_ TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_rw.41120175
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_intr_test.1499844157
Short name	T938
Test name
Test status
Simulation time	25456903 ps
CPU time	0.91 seconds
Started	Feb 09 08:32:09 AM UTC 25
Finished	Feb 09 08:32:12 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499844157 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_intr_test.1499844157
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.987772073
Short name	T940
Test name
Test status
Simulation time	32383634 ps
CPU time	1.63 seconds
Started	Feb 09 08:32:09 AM UTC 25
Finished	Feb 09 08:32:12 AM UTC 25
Peak memory	211756 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987772073 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_same_csr_outstanding.987772073
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.1698751080
Short name	T943
Test name
Test status
Simulation time	154320567 ps
CPU time	2.08 seconds
Started	Feb 09 08:32:09 AM UTC 25
Finished	Feb 09 08:32:13 AM UTC 25
Peak memory	212412 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698751080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors.1698751080
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.4048510055
Short name	T947
Test name
Test status
Simulation time	92421509 ps
CPU time	3.05 seconds
Started	Feb 09 08:32:09 AM UTC 25
Finished	Feb 09 08:32:13 AM UTC 25
Peak memory	212880 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404851 0055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.4048510055
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_tl_errors.710190826
Short name	T945
Test name
Test status
Simulation time	24914572 ps
CPU time	2.17 seconds
Started	Feb 09 08:32:09 AM UTC 25
Finished	Feb 09 08:32:13 AM UTC 25
Peak memory	212468 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710190826 -assert nopostproc +UVM_TE STNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_tl_errors.710190826
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3357385707
Short name	T132
Test name
Test status
Simulation time	57006443 ps
CPU time	1.71 seconds
Started	Feb 09 08:32:09 AM UTC 25
Finished	Feb 09 08:32:12 AM UTC 25
Peak memory	211932 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357385707 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_tl_intg_err.3357385707
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.95428730
Short name	T955
Test name
Test status
Simulation time	82310107 ps
CPU time	2.76 seconds
Started	Feb 09 08:32:15 AM UTC 25
Finished	Feb 09 08:32:19 AM UTC 25
Peak memory	221780 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_cl ear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=95428730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_ rw_with_rand_reset.95428730
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_csr_rw.635095932
Short name	T951
Test name
Test status
Simulation time	15713707 ps
CPU time	0.92 seconds
Started	Feb 09 08:32:15 AM UTC 25
Finished	Feb 09 08:32:17 AM UTC 25
Peak memory	211348 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635095932 -assert nopostproc +UVM _TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_rw.635095932
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_intr_test.3226002492
Short name	T949
Test name
Test status
Simulation time	14971196 ps
CPU time	1.09 seconds
Started	Feb 09 08:32:12 AM UTC 25
Finished	Feb 09 08:32:14 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226002492 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_intr_test.3226002492
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.738141679
Short name	T958
Test name
Test status
Simulation time	394052877 ps
CPU time	4.06 seconds
Started	Feb 09 08:32:15 AM UTC 25
Finished	Feb 09 08:32:20 AM UTC 25
Peak memory	212488 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738141679 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_same_csr_outstanding.738141679
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.2019409411
Short name	T944
Test name
Test status
Simulation time	51252907 ps
CPU time	1.76 seconds
Started	Feb 09 08:32:09 AM UTC 25
Finished	Feb 09 08:32:13 AM UTC 25
Peak memory	211624 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019409411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors.2019409411
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.240826140
Short name	T946
Test name
Test status
Simulation time	136124682 ps
CPU time	2.57 seconds
Started	Feb 09 08:32:09 AM UTC 25
Finished	Feb 09 08:32:13 AM UTC 25
Peak memory	212552 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240826 140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.240826140
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_tl_errors.1733153542
Short name	T950
Test name
Test status
Simulation time	380837222 ps
CPU time	5.16 seconds
Started	Feb 09 08:32:09 AM UTC 25
Finished	Feb 09 08:32:16 AM UTC 25
Peak memory	212712 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733153542 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_tl_errors.1733153542
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_tl_intg_err.747896411
Short name	T948
Test name
Test status
Simulation time	65071361 ps
CPU time	2.08 seconds
Started	Feb 09 08:32:10 AM UTC 25
Finished	Feb 09 08:32:14 AM UTC 25
Peak memory	212416 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747896411 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_tl_intg_err.747896411
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.1837304838
Short name	T954
Test name
Test status
Simulation time	43632218 ps
CPU time	1.29 seconds
Started	Feb 09 08:32:15 AM UTC 25
Finished	Feb 09 08:32:18 AM UTC 25
Peak memory	211684 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_cl ear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=1837304838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_me m_rw_with_rand_reset.1837304838
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_csr_rw.1123956243
Short name	T952
Test name
Test status
Simulation time	18560727 ps
CPU time	1.12 seconds
Started	Feb 09 08:32:15 AM UTC 25
Finished	Feb 09 08:32:17 AM UTC 25
Peak memory	211808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123956243 -assert nopostproc +UV M_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_rw.1123956243
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_intr_test.1276472991
Short name	T953
Test name
Test status
Simulation time	17249753 ps
CPU time	1.04 seconds
Started	Feb 09 08:32:15 AM UTC 25
Finished	Feb 09 08:32:17 AM UTC 25
Peak memory	211420 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276472991 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_intr_test.1276472991
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.2073577057
Short name	T956
Test name
Test status
Simulation time	88021560 ps
CPU time	2.47 seconds
Started	Feb 09 08:32:15 AM UTC 25
Finished	Feb 09 08:32:19 AM UTC 25
Peak memory	212600 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073577057 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_same_csr_outstanding.2073577057
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.2079641715
Short name	T960
Test name
Test status
Simulation time	479890169 ps
CPU time	5.46 seconds
Started	Feb 09 08:32:15 AM UTC 25
Finished	Feb 09 08:32:22 AM UTC 25
Peak memory	212620 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207964 1715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.2079641715
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_tl_errors.729160410
Short name	T959
Test name
Test status
Simulation time	441455710 ps
CPU time	4.31 seconds
Started	Feb 09 08:32:15 AM UTC 25
Finished	Feb 09 08:32:20 AM UTC 25
Peak memory	212732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729160410 -assert nopostproc +UVM_TE STNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_tl_errors.729160410
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_tl_intg_err.3688724163
Short name	T127
Test name
Test status
Simulation time	1448433677 ps
CPU time	6.26 seconds
Started	Feb 09 08:32:15 AM UTC 25
Finished	Feb 09 08:32:22 AM UTC 25
Peak memory	212412 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688724163 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_tl_intg_err.3688724163
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.583169713
Short name	T963
Test name
Test status
Simulation time	44842878 ps
CPU time	1.95 seconds
Started	Feb 09 08:32:21 AM UTC 25
Finished	Feb 09 08:32:24 AM UTC 25
Peak memory	211680 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_cl ear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=583169713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem _rw_with_rand_reset.583169713
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_csr_rw.2086803405
Short name	T913
Test name
Test status
Simulation time	14320298 ps
CPU time	1.06 seconds
Started	Feb 09 08:32:21 AM UTC 25
Finished	Feb 09 08:32:23 AM UTC 25
Peak memory	211868 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086803405 -assert nopostproc +UV M_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_rw.2086803405
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_intr_test.293300012
Short name	T961
Test name
Test status
Simulation time	60604748 ps
CPU time	1.24 seconds
Started	Feb 09 08:32:21 AM UTC 25
Finished	Feb 09 08:32:23 AM UTC 25
Peak memory	211152 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293300012 -assert nopostproc +UVM_TE STNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_intr_test.293300012
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.442259291
Short name	T962
Test name
Test status
Simulation time	109645416 ps
CPU time	1.66 seconds
Started	Feb 09 08:32:21 AM UTC 25
Finished	Feb 09 08:32:24 AM UTC 25
Peak memory	211420 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442259291 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_same_csr_outstanding.442259291
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.3218493757
Short name	T957
Test name
Test status
Simulation time	87932857 ps
CPU time	2.44 seconds
Started	Feb 09 08:32:15 AM UTC 25
Finished	Feb 09 08:32:19 AM UTC 25
Peak memory	212684 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218493757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors.3218493757
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.1342549198
Short name	T965
Test name
Test status
Simulation time	142410285 ps
CPU time	2.72 seconds
Started	Feb 09 08:32:21 AM UTC 25
Finished	Feb 09 08:32:25 AM UTC 25
Peak memory	212508 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134254 9198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.1342549198
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_tl_errors.2436550287
Short name	T964
Test name
Test status
Simulation time	78418196 ps
CPU time	2.62 seconds
Started	Feb 09 08:32:21 AM UTC 25
Finished	Feb 09 08:32:25 AM UTC 25
Peak memory	212456 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436550287 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_tl_errors.2436550287
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.4043176644
Short name	T972
Test name
Test status
Simulation time	205601474 ps
CPU time	2.15 seconds
Started	Feb 09 08:32:23 AM UTC 25
Finished	Feb 09 08:32:26 AM UTC 25
Peak memory	212392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_cl ear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=4043176644 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_me m_rw_with_rand_reset.4043176644
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_csr_rw.858602080
Short name	T971
Test name
Test status
Simulation time	186689427 ps
CPU time	2.12 seconds
Started	Feb 09 08:32:23 AM UTC 25
Finished	Feb 09 08:32:26 AM UTC 25
Peak memory	212072 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858602080 -assert nopostproc +UVM _TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_rw.858602080
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_intr_test.3243978078
Short name	T966
Test name
Test status
Simulation time	38918142 ps
CPU time	1.05 seconds
Started	Feb 09 08:32:23 AM UTC 25
Finished	Feb 09 08:32:25 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243978078 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_intr_test.3243978078
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.18759412
Short name	T968
Test name
Test status
Simulation time	51223301 ps
CPU time	1.5 seconds
Started	Feb 09 08:32:23 AM UTC 25
Finished	Feb 09 08:32:25 AM UTC 25
Peak memory	211808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18759412 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_same_csr_outstanding.18759412
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.3948255319
Short name	T967
Test name
Test status
Simulation time	423732670 ps
CPU time	2.63 seconds
Started	Feb 09 08:32:21 AM UTC 25
Finished	Feb 09 08:32:25 AM UTC 25
Peak memory	212736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948255319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors.3948255319
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.280805156
Short name	T970
Test name
Test status
Simulation time	153642159 ps
CPU time	3.36 seconds
Started	Feb 09 08:32:21 AM UTC 25
Finished	Feb 09 08:32:26 AM UTC 25
Peak memory	212608 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280805 156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.280805156
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_errors.3584778104
Short name	T973
Test name
Test status
Simulation time	74294918 ps
CPU time	3.59 seconds
Started	Feb 09 08:32:21 AM UTC 25
Finished	Feb 09 08:32:26 AM UTC 25
Peak memory	212728 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584778104 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_tl_errors.3584778104
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_intg_err.2866464821
Short name	T969
Test name
Test status
Simulation time	234726792 ps
CPU time	2.87 seconds
Started	Feb 09 08:32:21 AM UTC 25
Finished	Feb 09 08:32:25 AM UTC 25
Peak memory	212348 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866464821 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_tl_intg_err.2866464821
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.4113768729
Short name	T988
Test name
Test status
Simulation time	121757938 ps
CPU time	1.91 seconds
Started	Feb 09 08:32:28 AM UTC 25
Finished	Feb 09 08:32:31 AM UTC 25
Peak memory	211740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_cl ear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=4113768729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_me m_rw_with_rand_reset.4113768729
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_csr_rw.3253642176
Short name	T977
Test name
Test status
Simulation time	264779335 ps
CPU time	2.47 seconds
Started	Feb 09 08:32:25 AM UTC 25
Finished	Feb 09 08:32:29 AM UTC 25
Peak memory	212392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253642176 -assert nopostproc +UV M_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_rw.3253642176
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_intr_test.3558225209
Short name	T974
Test name
Test status
Simulation time	38307845 ps
CPU time	1.16 seconds
Started	Feb 09 08:32:25 AM UTC 25
Finished	Feb 09 08:32:28 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558225209 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_intr_test.3558225209
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.2776825780
Short name	T986
Test name
Test status
Simulation time	86125328 ps
CPU time	1.6 seconds
Started	Feb 09 08:32:28 AM UTC 25
Finished	Feb 09 08:32:31 AM UTC 25
Peak memory	211880 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776825780 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_same_csr_outstanding.2776825780
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.1190215293
Short name	T975
Test name
Test status
Simulation time	62710334 ps
CPU time	2.22 seconds
Started	Feb 09 08:32:25 AM UTC 25
Finished	Feb 09 08:32:29 AM UTC 25
Peak memory	212736 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190215293 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors.1190215293
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.3884018556
Short name	T976
Test name
Test status
Simulation time	198031544 ps
CPU time	2.32 seconds
Started	Feb 09 08:32:25 AM UTC 25
Finished	Feb 09 08:32:29 AM UTC 25
Peak memory	212684 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388401 8556 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.3884018556
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_errors.3863046523
Short name	T978
Test name
Test status
Simulation time	403622324 ps
CPU time	3.42 seconds
Started	Feb 09 08:32:25 AM UTC 25
Finished	Feb 09 08:32:30 AM UTC 25
Peak memory	212792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863046523 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_tl_errors.3863046523
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_intg_err.2045637396
Short name	T128
Test name
Test status
Simulation time	74515656 ps
CPU time	2.67 seconds
Started	Feb 09 08:32:25 AM UTC 25
Finished	Feb 09 08:32:29 AM UTC 25
Peak memory	212412 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045637396 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_tl_intg_err.2045637396
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_aliasing.2744441637
Short name	T865
Test name
Test status
Simulation time	113204682 ps
CPU time	3.14 seconds
Started	Feb 09 08:31:04 AM UTC 25
Finished	Feb 09 08:31:08 AM UTC 25
Peak memory	212592 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744441637 -assert nopostpr oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_aliasing.2744441637
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.3265155945
Short name	T871
Test name
Test status
Simulation time	712054944 ps
CPU time	9.15 seconds
Started	Feb 09 08:31:04 AM UTC 25
Finished	Feb 09 08:31:14 AM UTC 25
Peak memory	212352 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265155945 -assert nopostpr oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_bit_bash.3265155945
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.4039956680
Short name	T863
Test name
Test status
Simulation time	168317393 ps
CPU time	2.04 seconds
Started	Feb 09 08:31:01 AM UTC 25
Finished	Feb 09 08:31:05 AM UTC 25
Peak memory	212364 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039956680 -assert nopostpr oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_hw_reset.4039956680
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.3771133706
Short name	T866
Test name
Test status
Simulation time	24190487 ps
CPU time	1.53 seconds
Started	Feb 09 08:31:07 AM UTC 25
Finished	Feb 09 08:31:09 AM UTC 25
Peak memory	211676 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_cl ear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=3771133706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem _rw_with_rand_reset.3771133706
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_rw.4080021858
Short name	T112
Test name
Test status
Simulation time	19967105 ps
CPU time	1.27 seconds
Started	Feb 09 08:31:03 AM UTC 25
Finished	Feb 09 08:31:05 AM UTC 25
Peak memory	211808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080021858 -assert nopostproc +UV M_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_rw.4080021858
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_intr_test.2407197257
Short name	T862
Test name
Test status
Simulation time	13540230 ps
CPU time	1.08 seconds
Started	Feb 09 08:31:01 AM UTC 25
Finished	Feb 09 08:31:04 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407197257 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_intr_test.2407197257
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.65294621
Short name	T113
Test name
Test status
Simulation time	83214385 ps
CPU time	1.68 seconds
Started	Feb 09 08:31:05 AM UTC 25
Finished	Feb 09 08:31:08 AM UTC 25
Peak memory	211812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65294621 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_same_csr_outstanding.65294621
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.2854188303
Short name	T84
Test name
Test status
Simulation time	129949260 ps
CPU time	3.33 seconds
Started	Feb 09 08:30:57 AM UTC 25
Finished	Feb 09 08:31:01 AM UTC 25
Peak memory	222168 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854188303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors.2854188303
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.1925786532
Short name	T86
Test name
Test status
Simulation time	144366229 ps
CPU time	3.8 seconds
Started	Feb 09 08:30:58 AM UTC 25
Finished	Feb 09 08:31:03 AM UTC 25
Peak memory	212616 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192578 6532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.1925786532
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_tl_errors.3826200862
Short name	T864
Test name
Test status
Simulation time	89472814 ps
CPU time	4.08 seconds
Started	Feb 09 08:31:00 AM UTC 25
Finished	Feb 09 08:31:05 AM UTC 25
Peak memory	212476 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826200862 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_tl_errors.3826200862
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/20.clkmgr_intr_test.508013020
Short name	T979
Test name
Test status
Simulation time	11688800 ps
CPU time	0.81 seconds
Started	Feb 09 08:32:28 AM UTC 25
Finished	Feb 09 08:32:30 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508013020 -assert nopostproc +UVM_TE STNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.clkmgr_intr_test.508013020
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/20.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/21.clkmgr_intr_test.1834889333
Short name	T980
Test name
Test status
Simulation time	14073034 ps
CPU time	0.86 seconds
Started	Feb 09 08:32:28 AM UTC 25
Finished	Feb 09 08:32:30 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834889333 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.clkmgr_intr_test.1834889333
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/21.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/22.clkmgr_intr_test.2360205726
Short name	T981
Test name
Test status
Simulation time	17060705 ps
CPU time	0.89 seconds
Started	Feb 09 08:32:28 AM UTC 25
Finished	Feb 09 08:32:31 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360205726 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.clkmgr_intr_test.2360205726
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/22.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/23.clkmgr_intr_test.4255162061
Short name	T982
Test name
Test status
Simulation time	12873609 ps
CPU time	0.86 seconds
Started	Feb 09 08:32:28 AM UTC 25
Finished	Feb 09 08:32:31 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255162061 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.clkmgr_intr_test.4255162061
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/23.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/24.clkmgr_intr_test.3802763271
Short name	T983
Test name
Test status
Simulation time	13192394 ps
CPU time	0.96 seconds
Started	Feb 09 08:32:28 AM UTC 25
Finished	Feb 09 08:32:31 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802763271 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.clkmgr_intr_test.3802763271
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/24.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/25.clkmgr_intr_test.3559142413
Short name	T984
Test name
Test status
Simulation time	17674330 ps
CPU time	0.99 seconds
Started	Feb 09 08:32:28 AM UTC 25
Finished	Feb 09 08:32:31 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559142413 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.clkmgr_intr_test.3559142413
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/25.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/26.clkmgr_intr_test.951464485
Short name	T985
Test name
Test status
Simulation time	84974799 ps
CPU time	0.99 seconds
Started	Feb 09 08:32:28 AM UTC 25
Finished	Feb 09 08:32:31 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951464485 -assert nopostproc +UVM_TE STNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.clkmgr_intr_test.951464485
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/26.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/27.clkmgr_intr_test.947799198
Short name	T987
Test name
Test status
Simulation time	50036386 ps
CPU time	1.11 seconds
Started	Feb 09 08:32:28 AM UTC 25
Finished	Feb 09 08:32:31 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947799198 -assert nopostproc +UVM_TE STNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.clkmgr_intr_test.947799198
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/27.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/28.clkmgr_intr_test.525286367
Short name	T989
Test name
Test status
Simulation time	40068911 ps
CPU time	0.89 seconds
Started	Feb 09 08:32:29 AM UTC 25
Finished	Feb 09 08:32:32 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525286367 -assert nopostproc +UVM_TE STNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.clkmgr_intr_test.525286367
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/28.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/29.clkmgr_intr_test.1499024507
Short name	T991
Test name
Test status
Simulation time	20605520 ps
CPU time	0.97 seconds
Started	Feb 09 08:32:33 AM UTC 25
Finished	Feb 09 08:32:35 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499024507 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.clkmgr_intr_test.1499024507
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/29.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_aliasing.420475837
Short name	T872
Test name
Test status
Simulation time	44116872 ps
CPU time	1.93 seconds
Started	Feb 09 08:31:13 AM UTC 25
Finished	Feb 09 08:31:16 AM UTC 25
Peak memory	211744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420475837 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_aliasing.420475837
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.411533605
Short name	T879
Test name
Test status
Simulation time	277842992 ps
CPU time	6.6 seconds
Started	Feb 09 08:31:13 AM UTC 25
Finished	Feb 09 08:31:21 AM UTC 25
Peak memory	212236 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411533605 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_bit_bash.411533605
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.3914898707
Short name	T868
Test name
Test status
Simulation time	14379685 ps
CPU time	1.19 seconds
Started	Feb 09 08:31:10 AM UTC 25
Finished	Feb 09 08:31:12 AM UTC 25
Peak memory	212104 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914898707 -assert nopostpr oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_hw_reset.3914898707
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.1341678681
Short name	T875
Test name
Test status
Simulation time	39193125 ps
CPU time	1.85 seconds
Started	Feb 09 08:31:15 AM UTC 25
Finished	Feb 09 08:31:18 AM UTC 25
Peak memory	210580 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_cl ear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=1341678681 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem _rw_with_rand_reset.1341678681
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_rw.1494494153
Short name	T870
Test name
Test status
Simulation time	35414555 ps
CPU time	1.32 seconds
Started	Feb 09 08:31:11 AM UTC 25
Finished	Feb 09 08:31:14 AM UTC 25
Peak memory	212340 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494494153 -assert nopostproc +UV M_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_rw.1494494153
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_intr_test.3219299379
Short name	T867
Test name
Test status
Simulation time	27959775 ps
CPU time	1.03 seconds
Started	Feb 09 08:31:09 AM UTC 25
Finished	Feb 09 08:31:11 AM UTC 25
Peak memory	211524 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219299379 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_intr_test.3219299379
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.3722492221
Short name	T873
Test name
Test status
Simulation time	22018135 ps
CPU time	1.44 seconds
Started	Feb 09 08:31:15 AM UTC 25
Finished	Feb 09 08:31:17 AM UTC 25
Peak memory	210732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722492221 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_same_csr_outstanding.3722492221
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.2251515990
Short name	T81
Test name
Test status
Simulation time	130109656 ps
CPU time	2.32 seconds
Started	Feb 09 08:31:07 AM UTC 25
Finished	Feb 09 08:31:10 AM UTC 25
Peak memory	212544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251515990 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors.2251515990
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.1848011817
Short name	T88
Test name
Test status
Simulation time	198999189 ps
CPU time	3.44 seconds
Started	Feb 09 08:31:07 AM UTC 25
Finished	Feb 09 08:31:11 AM UTC 25
Peak memory	229032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184801 1817 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.1848011817
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_tl_errors.649407556
Short name	T869
Test name
Test status
Simulation time	460936083 ps
CPU time	5.39 seconds
Started	Feb 09 08:31:07 AM UTC 25
Finished	Feb 09 08:31:14 AM UTC 25
Peak memory	212456 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649407556 -assert nopostproc +UVM_TE STNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_tl_errors.649407556
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/30.clkmgr_intr_test.2209461995
Short name	T993
Test name
Test status
Simulation time	13116872 ps
CPU time	0.95 seconds
Started	Feb 09 08:32:33 AM UTC 25
Finished	Feb 09 08:32:35 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209461995 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.clkmgr_intr_test.2209461995
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/30.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/31.clkmgr_intr_test.1903848500
Short name	T992
Test name
Test status
Simulation time	12292554 ps
CPU time	0.97 seconds
Started	Feb 09 08:32:33 AM UTC 25
Finished	Feb 09 08:32:35 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903848500 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.clkmgr_intr_test.1903848500
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/31.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/32.clkmgr_intr_test.2563337079
Short name	T990
Test name
Test status
Simulation time	29963572 ps
CPU time	0.78 seconds
Started	Feb 09 08:32:33 AM UTC 25
Finished	Feb 09 08:32:35 AM UTC 25
Peak memory	211540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563337079 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.clkmgr_intr_test.2563337079
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/32.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/33.clkmgr_intr_test.2261351784
Short name	T994
Test name
Test status
Simulation time	17233226 ps
CPU time	0.91 seconds
Started	Feb 09 08:32:33 AM UTC 25
Finished	Feb 09 08:32:35 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261351784 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.clkmgr_intr_test.2261351784
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/33.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/34.clkmgr_intr_test.1316302021
Short name	T995
Test name
Test status
Simulation time	13784252 ps
CPU time	1.06 seconds
Started	Feb 09 08:32:33 AM UTC 25
Finished	Feb 09 08:32:35 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316302021 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.clkmgr_intr_test.1316302021
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/34.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/35.clkmgr_intr_test.2326945903
Short name	T1003
Test name
Test status
Simulation time	95243318 ps
CPU time	1.28 seconds
Started	Feb 09 08:32:33 AM UTC 25
Finished	Feb 09 08:32:36 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326945903 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.clkmgr_intr_test.2326945903
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/35.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/36.clkmgr_intr_test.157847051
Short name	T997
Test name
Test status
Simulation time	13169725 ps
CPU time	0.99 seconds
Started	Feb 09 08:32:33 AM UTC 25
Finished	Feb 09 08:32:36 AM UTC 25
Peak memory	211540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157847051 -assert nopostproc +UVM_TE STNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.clkmgr_intr_test.157847051
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/36.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/37.clkmgr_intr_test.385012766
Short name	T998
Test name
Test status
Simulation time	33483220 ps
CPU time	1.01 seconds
Started	Feb 09 08:32:33 AM UTC 25
Finished	Feb 09 08:32:36 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385012766 -assert nopostproc +UVM_TE STNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.clkmgr_intr_test.385012766
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/37.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/38.clkmgr_intr_test.1050501170
Short name	T1001
Test name
Test status
Simulation time	17275466 ps
CPU time	0.99 seconds
Started	Feb 09 08:32:33 AM UTC 25
Finished	Feb 09 08:32:36 AM UTC 25
Peak memory	211372 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050501170 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.clkmgr_intr_test.1050501170
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/38.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/39.clkmgr_intr_test.3677157912
Short name	T999
Test name
Test status
Simulation time	19923181 ps
CPU time	0.93 seconds
Started	Feb 09 08:32:33 AM UTC 25
Finished	Feb 09 08:32:36 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677157912 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.clkmgr_intr_test.3677157912
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/39.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_aliasing.2391296486
Short name	T881
Test name
Test status
Simulation time	136472951 ps
CPU time	2.05 seconds
Started	Feb 09 08:31:20 AM UTC 25
Finished	Feb 09 08:31:23 AM UTC 25
Peak memory	212080 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391296486 -assert nopostpr oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_aliasing.2391296486
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.1234320159
Short name	T884
Test name
Test status
Simulation time	141038631 ps
CPU time	4.95 seconds
Started	Feb 09 08:31:20 AM UTC 25
Finished	Feb 09 08:31:26 AM UTC 25
Peak memory	212636 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234320159 -assert nopostpr oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_bit_bash.1234320159
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.3776371600
Short name	T878
Test name
Test status
Simulation time	92448529 ps
CPU time	1.65 seconds
Started	Feb 09 08:31:17 AM UTC 25
Finished	Feb 09 08:31:20 AM UTC 25
Peak memory	211684 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776371600 -assert nopostpr oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_hw_reset.3776371600
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.604873006
Short name	T882
Test name
Test status
Simulation time	100996943 ps
CPU time	2.38 seconds
Started	Feb 09 08:31:20 AM UTC 25
Finished	Feb 09 08:31:23 AM UTC 25
Peak memory	212460 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_cl ear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=604873006 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_ rw_with_rand_reset.604873006
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_rw.2998373509
Short name	T880
Test name
Test status
Simulation time	50407235 ps
CPU time	1.34 seconds
Started	Feb 09 08:31:20 AM UTC 25
Finished	Feb 09 08:31:22 AM UTC 25
Peak memory	212344 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998373509 -assert nopostproc +UV M_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_rw.2998373509
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_intr_test.3295371209
Short name	T876
Test name
Test status
Simulation time	24997831 ps
CPU time	0.97 seconds
Started	Feb 09 08:31:16 AM UTC 25
Finished	Feb 09 08:31:18 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295371209 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_intr_test.3295371209
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.2281054146
Short name	T883
Test name
Test status
Simulation time	242364411 ps
CPU time	2.56 seconds
Started	Feb 09 08:31:20 AM UTC 25
Finished	Feb 09 08:31:24 AM UTC 25
Peak memory	212148 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281054146 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_same_csr_outstanding.2281054146
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.1457776255
Short name	T87
Test name
Test status
Simulation time	360390485 ps
CPU time	4.62 seconds
Started	Feb 09 08:31:15 AM UTC 25
Finished	Feb 09 08:31:21 AM UTC 25
Peak memory	229108 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457776255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors.1457776255
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.2554617891
Short name	T138
Test name
Test status
Simulation time	57002895 ps
CPU time	2.23 seconds
Started	Feb 09 08:31:15 AM UTC 25
Finished	Feb 09 08:31:18 AM UTC 25
Peak memory	222160 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255461 7891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.2554617891
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_tl_errors.3433768385
Short name	T877
Test name
Test status
Simulation time	74759737 ps
CPU time	2.43 seconds
Started	Feb 09 08:31:15 AM UTC 25
Finished	Feb 09 08:31:18 AM UTC 25
Peak memory	212708 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433768385 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_tl_errors.3433768385
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/40.clkmgr_intr_test.2510120458
Short name	T1002
Test name
Test status
Simulation time	19416103 ps
CPU time	1 seconds
Started	Feb 09 08:32:33 AM UTC 25
Finished	Feb 09 08:32:36 AM UTC 25
Peak memory	211136 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510120458 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.clkmgr_intr_test.2510120458
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/40.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/41.clkmgr_intr_test.171834335
Short name	T996
Test name
Test status
Simulation time	11457610 ps
CPU time	0.85 seconds
Started	Feb 09 08:32:33 AM UTC 25
Finished	Feb 09 08:32:35 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171834335 -assert nopostproc +UVM_TE STNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.clkmgr_intr_test.171834335
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/41.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/42.clkmgr_intr_test.935068583
Short name	T1004
Test name
Test status
Simulation time	28727748 ps
CPU time	0.9 seconds
Started	Feb 09 08:32:33 AM UTC 25
Finished	Feb 09 08:32:36 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935068583 -assert nopostproc +UVM_TE STNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.clkmgr_intr_test.935068583
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/42.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/43.clkmgr_intr_test.1376705094
Short name	T1000
Test name
Test status
Simulation time	24785698 ps
CPU time	0.79 seconds
Started	Feb 09 08:32:33 AM UTC 25
Finished	Feb 09 08:32:36 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376705094 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.clkmgr_intr_test.1376705094
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/43.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/44.clkmgr_intr_test.4188407137
Short name	T1006
Test name
Test status
Simulation time	13100299 ps
CPU time	1.06 seconds
Started	Feb 09 08:32:33 AM UTC 25
Finished	Feb 09 08:32:36 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188407137 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.clkmgr_intr_test.4188407137
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/44.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/45.clkmgr_intr_test.1322216720
Short name	T1005
Test name
Test status
Simulation time	50574985 ps
CPU time	1.01 seconds
Started	Feb 09 08:32:33 AM UTC 25
Finished	Feb 09 08:32:36 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322216720 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.clkmgr_intr_test.1322216720
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/45.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/46.clkmgr_intr_test.3802077319
Short name	T1008
Test name
Test status
Simulation time	23392637 ps
CPU time	0.97 seconds
Started	Feb 09 08:32:37 AM UTC 25
Finished	Feb 09 08:32:40 AM UTC 25
Peak memory	211540 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802077319 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.clkmgr_intr_test.3802077319
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/46.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/47.clkmgr_intr_test.3918059375
Short name	T1009
Test name
Test status
Simulation time	20566930 ps
CPU time	1.09 seconds
Started	Feb 09 08:32:37 AM UTC 25
Finished	Feb 09 08:32:40 AM UTC 25
Peak memory	211516 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918059375 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.clkmgr_intr_test.3918059375
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/47.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/48.clkmgr_intr_test.3852265892
Short name	T1010
Test name
Test status
Simulation time	76534814 ps
CPU time	1.24 seconds
Started	Feb 09 08:32:37 AM UTC 25
Finished	Feb 09 08:32:40 AM UTC 25
Peak memory	211280 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852265892 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.clkmgr_intr_test.3852265892
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/48.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/49.clkmgr_intr_test.2826196588
Short name	T1007
Test name
Test status
Simulation time	11072732 ps
CPU time	0.97 seconds
Started	Feb 09 08:32:37 AM UTC 25
Finished	Feb 09 08:32:40 AM UTC 25
Peak memory	211320 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826196588 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.clkmgr_intr_test.2826196588
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/49.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.1509610301
Short name	T888
Test name
Test status
Simulation time	72044051 ps
CPU time	2.1 seconds
Started	Feb 09 08:31:24 AM UTC 25
Finished	Feb 09 08:31:27 AM UTC 25
Peak memory	212200 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_cl ear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=1509610301 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem _rw_with_rand_reset.1509610301
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_csr_rw.2638500758
Short name	T887
Test name
Test status
Simulation time	26613481 ps
CPU time	1.15 seconds
Started	Feb 09 08:31:24 AM UTC 25
Finished	Feb 09 08:31:26 AM UTC 25
Peak memory	212344 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638500758 -assert nopostproc +UV M_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_rw.2638500758
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_intr_test.2275267209
Short name	T886
Test name
Test status
Simulation time	14624816 ps
CPU time	1.01 seconds
Started	Feb 09 08:31:24 AM UTC 25
Finished	Feb 09 08:31:26 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275267209 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_intr_test.2275267209
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.1419236700
Short name	T889
Test name
Test status
Simulation time	62330486 ps
CPU time	2.22 seconds
Started	Feb 09 08:31:24 AM UTC 25
Finished	Feb 09 08:31:27 AM UTC 25
Peak memory	212668 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419236700 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_same_csr_outstanding.1419236700
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.1865764356
Short name	T82
Test name
Test status
Simulation time	122888850 ps
CPU time	3.08 seconds
Started	Feb 09 08:31:21 AM UTC 25
Finished	Feb 09 08:31:25 AM UTC 25
Peak memory	221904 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865764356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors.1865764356
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.3669005359
Short name	T85
Test name
Test status
Simulation time	160275711 ps
CPU time	4.11 seconds
Started	Feb 09 08:31:22 AM UTC 25
Finished	Feb 09 08:31:28 AM UTC 25
Peak memory	212680 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366900 5359 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.3669005359
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_tl_errors.3214058133
Short name	T891
Test name
Test status
Simulation time	640393698 ps
CPU time	5.7 seconds
Started	Feb 09 08:31:22 AM UTC 25
Finished	Feb 09 08:31:29 AM UTC 25
Peak memory	212788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214058133 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_tl_errors.3214058133
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_tl_intg_err.1849033418
Short name	T885
Test name
Test status
Simulation time	57776128 ps
CPU time	2.32 seconds
Started	Feb 09 08:31:22 AM UTC 25
Finished	Feb 09 08:31:26 AM UTC 25
Peak memory	212672 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849033418 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_tl_intg_err.1849033418
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.1214922529
Short name	T895
Test name
Test status
Simulation time	115011401 ps
CPU time	2.48 seconds
Started	Feb 09 08:31:28 AM UTC 25
Finished	Feb 09 08:31:32 AM UTC 25
Peak memory	212392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_cl ear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=1214922529 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem _rw_with_rand_reset.1214922529
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_csr_rw.3746928616
Short name	T892
Test name
Test status
Simulation time	23307375 ps
CPU time	1.38 seconds
Started	Feb 09 08:31:27 AM UTC 25
Finished	Feb 09 08:31:30 AM UTC 25
Peak memory	211744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746928616 -assert nopostproc +UV M_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_rw.3746928616
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_intr_test.2925975028
Short name	T890
Test name
Test status
Simulation time	14849464 ps
CPU time	1.1 seconds
Started	Feb 09 08:31:27 AM UTC 25
Finished	Feb 09 08:31:29 AM UTC 25
Peak memory	211476 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925975028 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_intr_test.2925975028
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.1211769090
Short name	T893
Test name
Test status
Simulation time	88307386 ps
CPU time	1.84 seconds
Started	Feb 09 08:31:28 AM UTC 25
Finished	Feb 09 08:31:32 AM UTC 25
Peak memory	211752 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211769090 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_same_csr_outstanding.1211769090
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.2403785764
Short name	T150
Test name
Test status
Simulation time	96249350 ps
CPU time	2.84 seconds
Started	Feb 09 08:31:27 AM UTC 25
Finished	Feb 09 08:31:31 AM UTC 25
Peak memory	221828 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240378 5764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.2403785764
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_tl_errors.538580105
Short name	T874
Test name
Test status
Simulation time	28726885 ps
CPU time	2.55 seconds
Started	Feb 09 08:31:27 AM UTC 25
Finished	Feb 09 08:31:31 AM UTC 25
Peak memory	212268 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538580105 -assert nopostproc +UVM_TE STNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_tl_errors.538580105
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_tl_intg_err.2058688
Short name	T894
Test name
Test status
Simulation time	117258782 ps
CPU time	3.76 seconds
Started	Feb 09 08:31:27 AM UTC 25
Finished	Feb 09 08:31:32 AM UTC 25
Peak memory	212260 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058688 -assert nopostpr oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_tl_intg_err.2058688
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.3834963301
Short name	T898
Test name
Test status
Simulation time	37154735 ps
CPU time	1.9 seconds
Started	Feb 09 08:31:34 AM UTC 25
Finished	Feb 09 08:31:38 AM UTC 25
Peak memory	211676 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_cl ear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=3834963301 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem _rw_with_rand_reset.3834963301
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_csr_rw.716494406
Short name	T897
Test name
Test status
Simulation time	13645938 ps
CPU time	1.18 seconds
Started	Feb 09 08:31:34 AM UTC 25
Finished	Feb 09 08:31:37 AM UTC 25
Peak memory	211740 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716494406 -assert nopostproc +UVM _TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_rw.716494406
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_intr_test.1029493629
Short name	T896
Test name
Test status
Simulation time	16063526 ps
CPU time	1.05 seconds
Started	Feb 09 08:31:34 AM UTC 25
Finished	Feb 09 08:31:37 AM UTC 25
Peak memory	211528 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029493629 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_intr_test.1029493629
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.178650867
Short name	T899
Test name
Test status
Simulation time	98112045 ps
CPU time	2.46 seconds
Started	Feb 09 08:31:34 AM UTC 25
Finished	Feb 09 08:31:38 AM UTC 25
Peak memory	212400 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178650867 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_same_csr_outstanding.178650867
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.268616082
Short name	T140
Test name
Test status
Simulation time	98140010 ps
CPU time	1.69 seconds
Started	Feb 09 08:31:28 AM UTC 25
Finished	Feb 09 08:31:32 AM UTC 25
Peak memory	211688 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268616082 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors.268616082
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.2106083687
Short name	T147
Test name
Test status
Simulation time	90947094 ps
CPU time	3.11 seconds
Started	Feb 09 08:31:34 AM UTC 25
Finished	Feb 09 08:31:39 AM UTC 25
Peak memory	212460 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210608 3687 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.2106083687
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_tl_errors.1338389014
Short name	T900
Test name
Test status
Simulation time	90554785 ps
CPU time	3.29 seconds
Started	Feb 09 08:31:34 AM UTC 25
Finished	Feb 09 08:31:39 AM UTC 25
Peak memory	212508 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338389014 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_tl_errors.1338389014
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_tl_intg_err.3869778744
Short name	T902
Test name
Test status
Simulation time	423409832 ps
CPU time	3.94 seconds
Started	Feb 09 08:31:34 AM UTC 25
Finished	Feb 09 08:31:39 AM UTC 25
Peak memory	212404 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869778744 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_tl_intg_err.3869778744
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.1197433940
Short name	T908
Test name
Test status
Simulation time	43677510 ps
CPU time	1.47 seconds
Started	Feb 09 08:31:45 AM UTC 25
Finished	Feb 09 08:31:48 AM UTC 25
Peak memory	211656 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_cl ear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=1197433940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem _rw_with_rand_reset.1197433940
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_csr_rw.356792220
Short name	T904
Test name
Test status
Simulation time	64769929 ps
CPU time	1.57 seconds
Started	Feb 09 08:31:39 AM UTC 25
Finished	Feb 09 08:31:42 AM UTC 25
Peak memory	211744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356792220 -assert nopostproc +UVM _TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_rw.356792220
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_intr_test.3117502634
Short name	T901
Test name
Test status
Simulation time	29920865 ps
CPU time	1.09 seconds
Started	Feb 09 08:31:37 AM UTC 25
Finished	Feb 09 08:31:39 AM UTC 25
Peak memory	211544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117502634 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_intr_test.3117502634
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.714309859
Short name	T905
Test name
Test status
Simulation time	100334308 ps
CPU time	1.82 seconds
Started	Feb 09 08:31:39 AM UTC 25
Finished	Feb 09 08:31:42 AM UTC 25
Peak memory	211680 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714309859 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_same_csr_outstanding.714309859
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.919618936
Short name	T146
Test name
Test status
Simulation time	139020969 ps
CPU time	2.34 seconds
Started	Feb 09 08:31:34 AM UTC 25
Finished	Feb 09 08:31:38 AM UTC 25
Peak memory	212672 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919618936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors.919618936
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.1310914485
Short name	T141
Test name
Test status
Simulation time	116362939 ps
CPU time	4.17 seconds
Started	Feb 09 08:31:34 AM UTC 25
Finished	Feb 09 08:31:40 AM UTC 25
Peak memory	221908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131091 4485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.1310914485
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_tl_errors.2071248418
Short name	T903
Test name
Test status
Simulation time	44341637 ps
CPU time	3.41 seconds
Started	Feb 09 08:31:36 AM UTC 25
Finished	Feb 09 08:31:40 AM UTC 25
Peak memory	212772 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071248418 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_tl_errors.2071248418
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_tl_intg_err.3874831288
Short name	T200
Test name
Test status
Simulation time	97796196 ps
CPU time	3.86 seconds
Started	Feb 09 08:31:37 AM UTC 25
Finished	Feb 09 08:31:42 AM UTC 25
Peak memory	212676 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874831288 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_tl_intg_err.3874831288
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.2230895561
Short name	T911
Test name
Test status
Simulation time	72571210 ps
CPU time	2.17 seconds
Started	Feb 09 08:31:47 AM UTC 25
Finished	Feb 09 08:31:51 AM UTC 25
Peak memory	212468 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_cl ear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=2230895561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem _rw_with_rand_reset.2230895561
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_csr_rw.1748056502
Short name	T907
Test name
Test status
Simulation time	25613750 ps
CPU time	1.13 seconds
Started	Feb 09 08:31:45 AM UTC 25
Finished	Feb 09 08:31:48 AM UTC 25
Peak memory	211988 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748056502 -assert nopostproc +UV M_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_rw.1748056502
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_intr_test.4013021269
Short name	T906
Test name
Test status
Simulation time	12874899 ps
CPU time	0.95 seconds
Started	Feb 09 08:31:45 AM UTC 25
Finished	Feb 09 08:31:48 AM UTC 25
Peak memory	211532 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013021269 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_intr_test.4013021269
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.329951130
Short name	T910
Test name
Test status
Simulation time	50456670 ps
CPU time	2.05 seconds
Started	Feb 09 08:31:47 AM UTC 25
Finished	Feb 09 08:31:51 AM UTC 25
Peak memory	212332 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329951130 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_same_csr_outstanding.329951130
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.1203795603
Short name	T145
Test name
Test status
Simulation time	116039970 ps
CPU time	2.53 seconds
Started	Feb 09 08:31:45 AM UTC 25
Finished	Feb 09 08:31:49 AM UTC 25
Peak memory	212944 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203795603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors.1203795603
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.3182116647
Short name	T148
Test name
Test status
Simulation time	103570414 ps
CPU time	2.06 seconds
Started	Feb 09 08:31:45 AM UTC 25
Finished	Feb 09 08:31:48 AM UTC 25
Peak memory	212672 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318211 6647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.3182116647
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_tl_errors.1798738001
Short name	T909
Test name
Test status
Simulation time	589876851 ps
CPU time	3.99 seconds
Started	Feb 09 08:31:45 AM UTC 25
Finished	Feb 09 08:31:51 AM UTC 25
Peak memory	212360 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798738001 -assert nopostproc +UVM_T ESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_tl_errors.1798738001
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_tl_intg_err.3698057823
Short name	T131
Test name
Test status
Simulation time	167512928 ps
CPU time	3.16 seconds
Started	Feb 09 08:31:45 AM UTC 25
Finished	Feb 09 08:31:50 AM UTC 25
Peak memory	212612 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698057823 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_tl_intg_err.3698057823
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_div_intersig_mubi.1183323880
Short name	T34
Test name
Test status
Simulation time	21318830 ps
CPU time	1.22 seconds
Started	Feb 09 08:16:12 AM UTC 25
Finished	Feb 09 08:16:15 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183323880 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_div_intersig_mubi.1183323880
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_extclk.3431089618
Short name	T5
Test name
Test status
Simulation time	82050616 ps
CPU time	1.69 seconds
Started	Feb 09 08:16:09 AM UTC 25
Finished	Feb 09 08:16:12 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431089618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.3431089618
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_frequency.3297973451
Short name	T2
Test name
Test status
Simulation time	1534516919 ps
CPU time	11.87 seconds
Started	Feb 09 08:16:10 AM UTC 25
Finished	Feb 09 08:16:23 AM UTC 25
Peak memory	210248 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297973451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.3297973451
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_frequency_timeout.3635684348
Short name	T50
Test name
Test status
Simulation time	2061675138 ps
CPU time	21.92 seconds
Started	Feb 09 08:16:10 AM UTC 25
Finished	Feb 09 08:16:33 AM UTC 25
Peak memory	210492 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635684348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_timeout.3635684348
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.2971784146
Short name	T30
Test name
Test status
Simulation time	30311295 ps
CPU time	1.31 seconds
Started	Feb 09 08:16:11 AM UTC 25
Finished	Feb 09 08:16:14 AM UTC 25
Peak memory	210028 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971784146 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_lc_ctrl_intersig_mubi.2971784146
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_smoke.3171486846
Short name	T4
Test name
Test status
Simulation time	17152148 ps
CPU time	1.18 seconds
Started	Feb 09 08:16:09 AM UTC 25
Finished	Feb 09 08:16:11 AM UTC 25
Peak memory	209528 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171486846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.3171486846
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_stress_all.3514542336
Short name	T35
Test name
Test status
Simulation time	9988569270 ps
CPU time	112.6 seconds
Started	Feb 09 08:16:14 AM UTC 25
Finished	Feb 09 08:18:09 AM UTC 25
Peak memory	210912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514542336 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all.3514542336
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_stress_all_with_rand_reset.2964178475
Short name	T75
Test name
Test status
Simulation time	32014759634 ps
CPU time	387.78 seconds
Started	Feb 09 08:16:13 AM UTC 25
Finished	Feb 09 08:22:47 AM UTC 25
Peak memory	220300 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2964178475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.c lkmgr_stress_all_with_rand_reset.2964178475
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/0.clkmgr_trans.725489414
Short name	T29
Test name
Test status
Simulation time	62610371 ps
CPU time	1.26 seconds
Started	Feb 09 08:16:10 AM UTC 25
Finished	Feb 09 08:16:12 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725489414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.725489414
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/0.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_alert_test.440004051
Short name	T22
Test name
Test status
Simulation time	54842568 ps
CPU time	1.41 seconds
Started	Feb 09 08:16:24 AM UTC 25
Finished	Feb 09 08:16:26 AM UTC 25
Peak memory	209604 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440004051 -assert nopostproc +U VM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_alert_test.440004051
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_clk_status.3611914082
Short name	T53
Test name
Test status
Simulation time	12025360 ps
CPU time	1.04 seconds
Started	Feb 09 08:16:18 AM UTC 25
Finished	Feb 09 08:16:20 AM UTC 25
Peak memory	210028 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611914082 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.3611914082
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_extclk.1916830376
Short name	T104
Test name
Test status
Simulation time	16394744 ps
CPU time	1.19 seconds
Started	Feb 09 08:16:15 AM UTC 25
Finished	Feb 09 08:16:17 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916830376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.1916830376
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_frequency_timeout.1423458037
Short name	T3
Test name
Test status
Simulation time	1350029520 ps
CPU time	7.39 seconds
Started	Feb 09 08:16:15 AM UTC 25
Finished	Feb 09 08:16:23 AM UTC 25
Peak memory	210280 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423458037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_timeout.1423458037
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_idle_intersig_mubi.3305713584
Short name	T54
Test name
Test status
Simulation time	20249779 ps
CPU time	1.13 seconds
Started	Feb 09 08:16:18 AM UTC 25
Finished	Feb 09 08:16:20 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305713584 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_idle_intersig_mubi.3305713584
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.1826983368
Short name	T57
Test name
Test status
Simulation time	61753511 ps
CPU time	1.48 seconds
Started	Feb 09 08:16:19 AM UTC 25
Finished	Feb 09 08:16:22 AM UTC 25
Peak memory	209764 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826983368 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_lc_clk_byp_req_intersig_mubi.1826983368
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.2135980226
Short name	T56
Test name
Test status
Simulation time	30903083 ps
CPU time	1.19 seconds
Started	Feb 09 08:16:19 AM UTC 25
Finished	Feb 09 08:16:22 AM UTC 25
Peak memory	209824 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135980226 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_lc_ctrl_intersig_mubi.2135980226
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_peri.764897134
Short name	T51
Test name
Test status
Simulation time	17109418 ps
CPU time	1.14 seconds
Started	Feb 09 08:16:16 AM UTC 25
Finished	Feb 09 08:16:18 AM UTC 25
Peak memory	210088 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764897134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.764897134
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_regwen.3853561362
Short name	T11
Test name
Test status
Simulation time	734361828 ps
CPU time	8.22 seconds
Started	Feb 09 08:16:21 AM UTC 25
Finished	Feb 09 08:16:31 AM UTC 25
Peak memory	210192 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853561362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.3853561362
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_sec_cm.794205438
Short name	T20
Test name
Test status
Simulation time	153301237 ps
CPU time	3.37 seconds
Started	Feb 09 08:16:21 AM UTC 25
Finished	Feb 09 08:16:26 AM UTC 25
Peak memory	242388 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794205438 -assert nopostproc +UV M_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_sec_cm.794205438
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_smoke.715465861
Short name	T68
Test name
Test status
Simulation time	14439240 ps
CPU time	1.07 seconds
Started	Feb 09 08:16:15 AM UTC 25
Finished	Feb 09 08:16:17 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715465861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.715465861
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_stress_all_with_rand_reset.3238474378
Short name	T765
Test name
Test status
Simulation time	69663721421 ps
CPU time	768.39 seconds
Started	Feb 09 08:16:22 AM UTC 25
Finished	Feb 09 08:29:20 AM UTC 25
Peak memory	222220 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3238474378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.c lkmgr_stress_all_with_rand_reset.3238474378
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/1.clkmgr_trans.3732036377
Short name	T52
Test name
Test status
Simulation time	22389972 ps
CPU time	1.32 seconds
Started	Feb 09 08:16:17 AM UTC 25
Finished	Feb 09 08:16:19 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732036377 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.3732036377
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/1.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_alert_test.3388051374
Short name	T267
Test name
Test status
Simulation time	46367765 ps
CPU time	1.29 seconds
Started	Feb 09 08:18:42 AM UTC 25
Finished	Feb 09 08:18:45 AM UTC 25
Peak memory	209916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388051374 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_alert_test.3388051374
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.1356302737
Short name	T117
Test name
Test status
Simulation time	64757789 ps
CPU time	1.57 seconds
Started	Feb 09 08:18:37 AM UTC 25
Finished	Feb 09 08:18:40 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356302737 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_handshake_intersig_mubi.1356302737
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_clk_status.1685878029
Short name	T197
Test name
Test status
Simulation time	12757144 ps
CPU time	0.97 seconds
Started	Feb 09 08:18:33 AM UTC 25
Finished	Feb 09 08:18:35 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685878029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.1685878029
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_div_intersig_mubi.521878540
Short name	T264
Test name
Test status
Simulation time	20743267 ps
CPU time	1.12 seconds
Started	Feb 09 08:18:38 AM UTC 25
Finished	Feb 09 08:18:41 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521878540 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_div_intersig_mubi.521878540
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_extclk.1056689832
Short name	T257
Test name
Test status
Simulation time	26532676 ps
CPU time	1.29 seconds
Started	Feb 09 08:18:27 AM UTC 25
Finished	Feb 09 08:18:30 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056689832 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.1056689832
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_frequency.2110581001
Short name	T260
Test name
Test status
Simulation time	467268151 ps
CPU time	4.24 seconds
Started	Feb 09 08:18:28 AM UTC 25
Finished	Feb 09 08:18:34 AM UTC 25
Peak memory	210244 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110581001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.2110581001
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_frequency_timeout.763468366
Short name	T268
Test name
Test status
Simulation time	1338902036 ps
CPU time	16.63 seconds
Started	Feb 09 08:18:29 AM UTC 25
Finished	Feb 09 08:18:47 AM UTC 25
Peak memory	210272 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763468366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_timeout.763468366
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_idle_intersig_mubi.1012181583
Short name	T261
Test name
Test status
Simulation time	36162603 ps
CPU time	1.09 seconds
Started	Feb 09 08:18:34 AM UTC 25
Finished	Feb 09 08:18:36 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012181583 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_idle_intersig_mubi.1012181583
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.1576979944
Short name	T263
Test name
Test status
Simulation time	56715951 ps
CPU time	1.59 seconds
Started	Feb 09 08:18:36 AM UTC 25
Finished	Feb 09 08:18:39 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576979944 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_lc_clk_byp_req_intersig_mubi.1576979944
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.274618865
Short name	T262
Test name
Test status
Simulation time	30255803 ps
CPU time	1.3 seconds
Started	Feb 09 08:18:35 AM UTC 25
Finished	Feb 09 08:18:37 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274618865 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_lc_ctrl_intersig_mubi.274618865
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_peri.79336302
Short name	T258
Test name
Test status
Simulation time	62612629 ps
CPU time	1.52 seconds
Started	Feb 09 08:18:29 AM UTC 25
Finished	Feb 09 08:18:32 AM UTC 25
Peak memory	210092 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79336302 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.79336302
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_regwen.1243515022
Short name	T266
Test name
Test status
Simulation time	654279045 ps
CPU time	4.27 seconds
Started	Feb 09 08:18:39 AM UTC 25
Finished	Feb 09 08:18:45 AM UTC 25
Peak memory	210648 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243515022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.1243515022
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_smoke.3902854734
Short name	T256
Test name
Test status
Simulation time	93210485 ps
CPU time	1.5 seconds
Started	Feb 09 08:18:26 AM UTC 25
Finished	Feb 09 08:18:29 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902854734 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.3902854734
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_stress_all.671009849
Short name	T154
Test name
Test status
Simulation time	2431648299 ps
CPU time	17.04 seconds
Started	Feb 09 08:18:41 AM UTC 25
Finished	Feb 09 08:19:00 AM UTC 25
Peak memory	210580 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671009849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all.671009849
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_stress_all_with_rand_reset.1297255778
Short name	T835
Test name
Test status
Simulation time	157476930387 ps
CPU time	1207.7 seconds
Started	Feb 09 08:18:40 AM UTC 25
Finished	Feb 09 08:39:01 AM UTC 25
Peak memory	220364 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1297255778 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10. clkmgr_stress_all_with_rand_reset.1297255778
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/10.clkmgr_trans.4117840116
Short name	T259
Test name
Test status
Simulation time	73455383 ps
CPU time	1.55 seconds
Started	Feb 09 08:18:31 AM UTC 25
Finished	Feb 09 08:18:33 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117840116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.4117840116
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_alert_test.2920281585
Short name	T279
Test name
Test status
Simulation time	14392336 ps
CPU time	1.07 seconds
Started	Feb 09 08:19:01 AM UTC 25
Finished	Feb 09 08:19:03 AM UTC 25
Peak memory	209656 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920281585 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_alert_test.2920281585
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.3757739251
Short name	T277
Test name
Test status
Simulation time	61971409 ps
CPU time	1.39 seconds
Started	Feb 09 08:18:56 AM UTC 25
Finished	Feb 09 08:18:59 AM UTC 25
Peak memory	210036 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757739251 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_handshake_intersig_mubi.3757739251
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_clk_status.2168191250
Short name	T273
Test name
Test status
Simulation time	84049042 ps
CPU time	1.48 seconds
Started	Feb 09 08:18:52 AM UTC 25
Finished	Feb 09 08:18:55 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168191250 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.2168191250
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_div_intersig_mubi.705715669
Short name	T278
Test name
Test status
Simulation time	13379541 ps
CPU time	1.1 seconds
Started	Feb 09 08:18:57 AM UTC 25
Finished	Feb 09 08:19:00 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705715669 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_div_intersig_mubi.705715669
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_extclk.2042823454
Short name	T269
Test name
Test status
Simulation time	39217639 ps
CPU time	1.29 seconds
Started	Feb 09 08:18:46 AM UTC 25
Finished	Feb 09 08:18:48 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042823454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.2042823454
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_frequency.3303880629
Short name	T272
Test name
Test status
Simulation time	464675171 ps
CPU time	2.81 seconds
Started	Feb 09 08:18:49 AM UTC 25
Finished	Feb 09 08:18:53 AM UTC 25
Peak memory	210244 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303880629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.3303880629
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_frequency_timeout.2399218878
Short name	T285
Test name
Test status
Simulation time	2064930747 ps
CPU time	24.89 seconds
Started	Feb 09 08:18:49 AM UTC 25
Finished	Feb 09 08:19:15 AM UTC 25
Peak memory	210584 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399218878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_timeout.2399218878
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.1661421013
Short name	T276
Test name
Test status
Simulation time	13316417 ps
CPU time	1.13 seconds
Started	Feb 09 08:18:55 AM UTC 25
Finished	Feb 09 08:18:58 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661421013 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_lc_clk_byp_req_intersig_mubi.1661421013
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.1488062800
Short name	T275
Test name
Test status
Simulation time	15362872 ps
CPU time	1.11 seconds
Started	Feb 09 08:18:54 AM UTC 25
Finished	Feb 09 08:18:57 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488062800 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_lc_ctrl_intersig_mubi.1488062800
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_peri.646622300
Short name	T270
Test name
Test status
Simulation time	15235483 ps
CPU time	1.14 seconds
Started	Feb 09 08:18:49 AM UTC 25
Finished	Feb 09 08:18:51 AM UTC 25
Peak memory	209904 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646622300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.646622300
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_regwen.943177508
Short name	T174
Test name
Test status
Simulation time	390603111 ps
CPU time	3.76 seconds
Started	Feb 09 08:18:59 AM UTC 25
Finished	Feb 09 08:19:03 AM UTC 25
Peak memory	210244 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943177508 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.943177508
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_smoke.456811327
Short name	T153
Test name
Test status
Simulation time	16410539 ps
CPU time	1.22 seconds
Started	Feb 09 08:18:46 AM UTC 25
Finished	Feb 09 08:18:48 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456811327 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.456811327
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_stress_all.1425791579
Short name	T280
Test name
Test status
Simulation time	33310395 ps
CPU time	1.49 seconds
Started	Feb 09 08:19:01 AM UTC 25
Finished	Feb 09 08:19:03 AM UTC 25
Peak memory	209804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425791579 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all.1425791579
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_stress_all_with_rand_reset.3587974108
Short name	T840
Test name
Test status
Simulation time	221139428707 ps
CPU time	1304.1 seconds
Started	Feb 09 08:19:00 AM UTC 25
Finished	Feb 09 08:40:57 AM UTC 25
Peak memory	226356 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3587974108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11. clkmgr_stress_all_with_rand_reset.3587974108
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/11.clkmgr_trans.1256435156
Short name	T271
Test name
Test status
Simulation time	15138119 ps
CPU time	1.14 seconds
Started	Feb 09 08:18:50 AM UTC 25
Finished	Feb 09 08:18:52 AM UTC 25
Peak memory	210028 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256435156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.1256435156
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/11.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_alert_test.987870172
Short name	T295
Test name
Test status
Simulation time	38313850 ps
CPU time	1.15 seconds
Started	Feb 09 08:19:39 AM UTC 25
Finished	Feb 09 08:19:42 AM UTC 25
Peak memory	209888 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987870172 -assert nopostproc +U VM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_alert_test.987870172
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.1019231709
Short name	T291
Test name
Test status
Simulation time	37575394 ps
CPU time	1.25 seconds
Started	Feb 09 08:19:21 AM UTC 25
Finished	Feb 09 08:19:23 AM UTC 25
Peak memory	210036 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019231709 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_handshake_intersig_mubi.1019231709
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_clk_status.751316305
Short name	T286
Test name
Test status
Simulation time	22520523 ps
CPU time	1.16 seconds
Started	Feb 09 08:19:14 AM UTC 25
Finished	Feb 09 08:19:17 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751316305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.751316305
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_div_intersig_mubi.3601856355
Short name	T294
Test name
Test status
Simulation time	34299075 ps
CPU time	1.4 seconds
Started	Feb 09 08:19:39 AM UTC 25
Finished	Feb 09 08:19:42 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601856355 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_div_intersig_mubi.3601856355
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_extclk.2546142607
Short name	T282
Test name
Test status
Simulation time	40384193 ps
CPU time	1.35 seconds
Started	Feb 09 08:19:04 AM UTC 25
Finished	Feb 09 08:19:06 AM UTC 25
Peak memory	209372 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546142607 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.2546142607
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_frequency.2011301501
Short name	T290
Test name
Test status
Simulation time	2472800386 ps
CPU time	17.59 seconds
Started	Feb 09 08:19:04 AM UTC 25
Finished	Feb 09 08:19:23 AM UTC 25
Peak memory	210600 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011301501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.2011301501
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_frequency_timeout.3976078710
Short name	T292
Test name
Test status
Simulation time	1816075384 ps
CPU time	18.95 seconds
Started	Feb 09 08:19:07 AM UTC 25
Finished	Feb 09 08:19:28 AM UTC 25
Peak memory	210272 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976078710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_timeout.3976078710
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_idle_intersig_mubi.2297659027
Short name	T287
Test name
Test status
Simulation time	24921417 ps
CPU time	1.44 seconds
Started	Feb 09 08:19:16 AM UTC 25
Finished	Feb 09 08:19:19 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297659027 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_idle_intersig_mubi.2297659027
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.2255807235
Short name	T289
Test name
Test status
Simulation time	48949368 ps
CPU time	1.27 seconds
Started	Feb 09 08:19:20 AM UTC 25
Finished	Feb 09 08:19:22 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255807235 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_lc_clk_byp_req_intersig_mubi.2255807235
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.2855446258
Short name	T288
Test name
Test status
Simulation time	62226707 ps
CPU time	1.37 seconds
Started	Feb 09 08:19:18 AM UTC 25
Finished	Feb 09 08:19:20 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855446258 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_lc_ctrl_intersig_mubi.2855446258
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_peri.1593295765
Short name	T283
Test name
Test status
Simulation time	13554729 ps
CPU time	1.16 seconds
Started	Feb 09 08:19:07 AM UTC 25
Finished	Feb 09 08:19:09 AM UTC 25
Peak memory	210088 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593295765 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.1593295765
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_regwen.4156983108
Short name	T297
Test name
Test status
Simulation time	969863746 ps
CPU time	9.29 seconds
Started	Feb 09 08:19:39 AM UTC 25
Finished	Feb 09 08:19:50 AM UTC 25
Peak memory	210624 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156983108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.4156983108
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_smoke.2459668392
Short name	T281
Test name
Test status
Simulation time	19706395 ps
CPU time	1.18 seconds
Started	Feb 09 08:19:04 AM UTC 25
Finished	Feb 09 08:19:06 AM UTC 25
Peak memory	210260 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459668392 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.2459668392
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_stress_all.2184609975
Short name	T70
Test name
Test status
Simulation time	5860085929 ps
CPU time	42.72 seconds
Started	Feb 09 08:19:39 AM UTC 25
Finished	Feb 09 08:20:23 AM UTC 25
Peak memory	210848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184609975 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all.2184609975
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_stress_all_with_rand_reset.1077947399
Short name	T93
Test name
Test status
Simulation time	60610479746 ps
CPU time	463.38 seconds
Started	Feb 09 08:19:39 AM UTC 25
Finished	Feb 09 08:27:28 AM UTC 25
Peak memory	220468 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1077947399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12. clkmgr_stress_all_with_rand_reset.1077947399
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/12.clkmgr_trans.308497388
Short name	T284
Test name
Test status
Simulation time	333290588 ps
CPU time	2.08 seconds
Started	Feb 09 08:19:10 AM UTC 25
Finished	Feb 09 08:19:14 AM UTC 25
Peak memory	210180 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308497388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.308497388
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/12.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_alert_test.528756802
Short name	T308
Test name
Test status
Simulation time	23198946 ps
CPU time	1.22 seconds
Started	Feb 09 08:20:00 AM UTC 25
Finished	Feb 09 08:20:02 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528756802 -assert nopostproc +U VM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_alert_test.528756802
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.3921069589
Short name	T302
Test name
Test status
Simulation time	26854803 ps
CPU time	1.27 seconds
Started	Feb 09 08:19:56 AM UTC 25
Finished	Feb 09 08:19:59 AM UTC 25
Peak memory	209916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921069589 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_handshake_intersig_mubi.3921069589
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_clk_status.3904209859
Short name	T303
Test name
Test status
Simulation time	171744515 ps
CPU time	1.71 seconds
Started	Feb 09 08:19:56 AM UTC 25
Finished	Feb 09 08:19:59 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904209859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.3904209859
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_div_intersig_mubi.4099571991
Short name	T307
Test name
Test status
Simulation time	24328172 ps
CPU time	1.27 seconds
Started	Feb 09 08:19:59 AM UTC 25
Finished	Feb 09 08:20:02 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099571991 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_div_intersig_mubi.4099571991
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_extclk.3089136140
Short name	T296
Test name
Test status
Simulation time	23194545 ps
CPU time	1.27 seconds
Started	Feb 09 08:19:39 AM UTC 25
Finished	Feb 09 08:19:42 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089136140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.3089136140
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_frequency.2747351847
Short name	T99
Test name
Test status
Simulation time	562794283 ps
CPU time	8.69 seconds
Started	Feb 09 08:19:56 AM UTC 25
Finished	Feb 09 08:20:06 AM UTC 25
Peak memory	210244 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747351847 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.2747351847
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_frequency_timeout.337521389
Short name	T305
Test name
Test status
Simulation time	528068480 ps
CPU time	4.07 seconds
Started	Feb 09 08:19:56 AM UTC 25
Finished	Feb 09 08:20:01 AM UTC 25
Peak memory	210528 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337521389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_timeout.337521389
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_idle_intersig_mubi.1438188300
Short name	T299
Test name
Test status
Simulation time	17114873 ps
CPU time	1.09 seconds
Started	Feb 09 08:19:56 AM UTC 25
Finished	Feb 09 08:19:58 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438188300 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_idle_intersig_mubi.1438188300
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.3295689998
Short name	T304
Test name
Test status
Simulation time	382263230 ps
CPU time	3.53 seconds
Started	Feb 09 08:19:56 AM UTC 25
Finished	Feb 09 08:20:01 AM UTC 25
Peak memory	210172 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295689998 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_lc_clk_byp_req_intersig_mubi.3295689998
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.1378051325
Short name	T301
Test name
Test status
Simulation time	131274342 ps
CPU time	1.28 seconds
Started	Feb 09 08:19:56 AM UTC 25
Finished	Feb 09 08:19:59 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378051325 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_lc_ctrl_intersig_mubi.1378051325
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_peri.4202480726
Short name	T298
Test name
Test status
Simulation time	41738241 ps
CPU time	1.15 seconds
Started	Feb 09 08:19:56 AM UTC 25
Finished	Feb 09 08:19:58 AM UTC 25
Peak memory	210060 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202480726 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.4202480726
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_regwen.597943987
Short name	T309
Test name
Test status
Simulation time	124905421 ps
CPU time	1.58 seconds
Started	Feb 09 08:19:59 AM UTC 25
Finished	Feb 09 08:20:02 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597943987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.597943987
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_smoke.2608398647
Short name	T293
Test name
Test status
Simulation time	26599837 ps
CPU time	1.07 seconds
Started	Feb 09 08:19:39 AM UTC 25
Finished	Feb 09 08:19:41 AM UTC 25
Peak memory	210324 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608398647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.2608398647
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_stress_all.2273570457
Short name	T135
Test name
Test status
Simulation time	8899366737 ps
CPU time	58.12 seconds
Started	Feb 09 08:20:00 AM UTC 25
Finished	Feb 09 08:20:59 AM UTC 25
Peak memory	210716 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273570457 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all.2273570457
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_stress_all_with_rand_reset.4160180878
Short name	T178
Test name
Test status
Simulation time	41103207102 ps
CPU time	602.45 seconds
Started	Feb 09 08:19:59 AM UTC 25
Finished	Feb 09 08:30:09 AM UTC 25
Peak memory	220152 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=4160180878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13. clkmgr_stress_all_with_rand_reset.4160180878
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/13.clkmgr_trans.1945477951
Short name	T300
Test name
Test status
Simulation time	32233204 ps
CPU time	1.4 seconds
Started	Feb 09 08:19:56 AM UTC 25
Finished	Feb 09 08:19:59 AM UTC 25
Peak memory	209760 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945477951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.1945477951
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/13.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_alert_test.1099937197
Short name	T312
Test name
Test status
Simulation time	41493681 ps
CPU time	1.26 seconds
Started	Feb 09 08:20:10 AM UTC 25
Finished	Feb 09 08:20:12 AM UTC 25
Peak memory	209896 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099937197 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_alert_test.1099937197
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.780202844
Short name	T102
Test name
Test status
Simulation time	31567353 ps
CPU time	1.22 seconds
Started	Feb 09 08:20:06 AM UTC 25
Finished	Feb 09 08:20:09 AM UTC 25
Peak memory	209928 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780202844 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_handshake_intersig_mubi.780202844
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_clk_status.1422162103
Short name	T97
Test name
Test status
Simulation time	106687549 ps
CPU time	1.48 seconds
Started	Feb 09 08:20:03 AM UTC 25
Finished	Feb 09 08:20:06 AM UTC 25
Peak memory	208744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422162103 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.1422162103
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_div_intersig_mubi.1713386278
Short name	T310
Test name
Test status
Simulation time	36044243 ps
CPU time	1.27 seconds
Started	Feb 09 08:20:06 AM UTC 25
Finished	Feb 09 08:20:09 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713386278 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_div_intersig_mubi.1713386278
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_extclk.2826591277
Short name	T95
Test name
Test status
Simulation time	19562183 ps
CPU time	1.28 seconds
Started	Feb 09 08:20:02 AM UTC 25
Finished	Feb 09 08:20:04 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826591277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.2826591277
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_frequency.4178896530
Short name	T311
Test name
Test status
Simulation time	1054102432 ps
CPU time	6.94 seconds
Started	Feb 09 08:20:02 AM UTC 25
Finished	Feb 09 08:20:10 AM UTC 25
Peak memory	210432 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178896530 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.4178896530
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_frequency_timeout.675958987
Short name	T317
Test name
Test status
Simulation time	2144181420 ps
CPU time	13.25 seconds
Started	Feb 09 08:20:03 AM UTC 25
Finished	Feb 09 08:20:17 AM UTC 25
Peak memory	210544 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675958987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_timeout.675958987
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_idle_intersig_mubi.1886573245
Short name	T100
Test name
Test status
Simulation time	72846913 ps
CPU time	1.83 seconds
Started	Feb 09 08:20:03 AM UTC 25
Finished	Feb 09 08:20:06 AM UTC 25
Peak memory	209852 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886573245 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_idle_intersig_mubi.1886573245
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.406394715
Short name	T103
Test name
Test status
Simulation time	53556784 ps
CPU time	1.23 seconds
Started	Feb 09 08:20:06 AM UTC 25
Finished	Feb 09 08:20:09 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406394715 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_lc_clk_byp_req_intersig_mubi.406394715
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.254206531
Short name	T101
Test name
Test status
Simulation time	145925294 ps
CPU time	2.12 seconds
Started	Feb 09 08:20:05 AM UTC 25
Finished	Feb 09 08:20:08 AM UTC 25
Peak memory	210184 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254206531 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_lc_ctrl_intersig_mubi.254206531
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_peri.340645872
Short name	T96
Test name
Test status
Simulation time	44261079 ps
CPU time	1.3 seconds
Started	Feb 09 08:20:03 AM UTC 25
Finished	Feb 09 08:20:05 AM UTC 25
Peak memory	210084 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340645872 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.340645872
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_regwen.2039341424
Short name	T175
Test name
Test status
Simulation time	958805843 ps
CPU time	7.55 seconds
Started	Feb 09 08:20:06 AM UTC 25
Finished	Feb 09 08:20:15 AM UTC 25
Peak memory	210456 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039341424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.2039341424
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_smoke.2295100126
Short name	T306
Test name
Test status
Simulation time	42254890 ps
CPU time	1 seconds
Started	Feb 09 08:20:00 AM UTC 25
Finished	Feb 09 08:20:02 AM UTC 25
Peak memory	210324 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295100126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.2295100126
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_stress_all.1467207765
Short name	T355
Test name
Test status
Simulation time	4539964262 ps
CPU time	64.26 seconds
Started	Feb 09 08:20:10 AM UTC 25
Finished	Feb 09 08:21:16 AM UTC 25
Peak memory	210592 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467207765 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all.1467207765
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_stress_all_with_rand_reset.3112514561
Short name	T94
Test name
Test status
Simulation time	23414550162 ps
CPU time	455.59 seconds
Started	Feb 09 08:20:08 AM UTC 25
Finished	Feb 09 08:27:49 AM UTC 25
Peak memory	220172 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3112514561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14. clkmgr_stress_all_with_rand_reset.3112514561
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/14.clkmgr_trans.3148262598
Short name	T98
Test name
Test status
Simulation time	81489225 ps
CPU time	1.59 seconds
Started	Feb 09 08:20:03 AM UTC 25
Finished	Feb 09 08:20:06 AM UTC 25
Peak memory	209964 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148262598 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.3148262598
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/14.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_alert_test.1606671237
Short name	T324
Test name
Test status
Simulation time	48826860 ps
CPU time	1.28 seconds
Started	Feb 09 08:20:23 AM UTC 25
Finished	Feb 09 08:20:25 AM UTC 25
Peak memory	209516 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606671237 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_alert_test.1606671237
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.3370269741
Short name	T323
Test name
Test status
Simulation time	39840345 ps
CPU time	1.22 seconds
Started	Feb 09 08:20:20 AM UTC 25
Finished	Feb 09 08:20:22 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370269741 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_handshake_intersig_mubi.3370269741
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_clk_status.3615539715
Short name	T318
Test name
Test status
Simulation time	14949923 ps
CPU time	1.1 seconds
Started	Feb 09 08:20:16 AM UTC 25
Finished	Feb 09 08:20:19 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615539715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.3615539715
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_div_intersig_mubi.3200788926
Short name	T322
Test name
Test status
Simulation time	28713596 ps
CPU time	1.12 seconds
Started	Feb 09 08:20:20 AM UTC 25
Finished	Feb 09 08:20:22 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200788926 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_div_intersig_mubi.3200788926
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_extclk.2058463309
Short name	T313
Test name
Test status
Simulation time	43469441 ps
CPU time	1.27 seconds
Started	Feb 09 08:20:10 AM UTC 25
Finished	Feb 09 08:20:12 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058463309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.2058463309
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_frequency.892449529
Short name	T336
Test name
Test status
Simulation time	2476942085 ps
CPU time	32.91 seconds
Started	Feb 09 08:20:11 AM UTC 25
Finished	Feb 09 08:20:45 AM UTC 25
Peak memory	210780 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892449529 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.892449529
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_frequency_timeout.3383246775
Short name	T326
Test name
Test status
Simulation time	1709956497 ps
CPU time	13.42 seconds
Started	Feb 09 08:20:13 AM UTC 25
Finished	Feb 09 08:20:28 AM UTC 25
Peak memory	210272 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383246775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_timeout.3383246775
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_idle_intersig_mubi.1228747584
Short name	T319
Test name
Test status
Simulation time	27052418 ps
CPU time	1.34 seconds
Started	Feb 09 08:20:16 AM UTC 25
Finished	Feb 09 08:20:19 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228747584 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_idle_intersig_mubi.1228747584
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.2166217612
Short name	T321
Test name
Test status
Simulation time	189259535 ps
CPU time	2.4 seconds
Started	Feb 09 08:20:19 AM UTC 25
Finished	Feb 09 08:20:22 AM UTC 25
Peak memory	210180 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166217612 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_lc_clk_byp_req_intersig_mubi.2166217612
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.1737403590
Short name	T320
Test name
Test status
Simulation time	21262370 ps
CPU time	1.34 seconds
Started	Feb 09 08:20:16 AM UTC 25
Finished	Feb 09 08:20:19 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737403590 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_lc_ctrl_intersig_mubi.1737403590
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_peri.983600258
Short name	T315
Test name
Test status
Simulation time	15448659 ps
CPU time	1.16 seconds
Started	Feb 09 08:20:13 AM UTC 25
Finished	Feb 09 08:20:15 AM UTC 25
Peak memory	210084 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983600258 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.983600258
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_regwen.1925591244
Short name	T134
Test name
Test status
Simulation time	2655350531 ps
CPU time	14.53 seconds
Started	Feb 09 08:20:20 AM UTC 25
Finished	Feb 09 08:20:36 AM UTC 25
Peak memory	210820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925591244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.1925591244
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_smoke.1884336793
Short name	T314
Test name
Test status
Simulation time	47475407 ps
CPU time	1.36 seconds
Started	Feb 09 08:20:10 AM UTC 25
Finished	Feb 09 08:20:12 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884336793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.1884336793
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_stress_all.2265054288
Short name	T394
Test name
Test status
Simulation time	10178849775 ps
CPU time	106 seconds
Started	Feb 09 08:20:23 AM UTC 25
Finished	Feb 09 08:22:11 AM UTC 25
Peak memory	210296 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265054288 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all.2265054288
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_stress_all_with_rand_reset.26254983
Short name	T184
Test name
Test status
Simulation time	115062692561 ps
CPU time	1180.07 seconds
Started	Feb 09 08:20:23 AM UTC 25
Finished	Feb 09 08:40:16 AM UTC 25
Peak memory	220236 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=26254983 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.cl kmgr_stress_all_with_rand_reset.26254983
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/15.clkmgr_trans.3998450315
Short name	T316
Test name
Test status
Simulation time	30018992 ps
CPU time	1.58 seconds
Started	Feb 09 08:20:13 AM UTC 25
Finished	Feb 09 08:20:16 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998450315 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.3998450315
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/15.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_alert_test.4080433074
Short name	T338
Test name
Test status
Simulation time	20067730 ps
CPU time	1.15 seconds
Started	Feb 09 08:20:45 AM UTC 25
Finished	Feb 09 08:20:48 AM UTC 25
Peak memory	209856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080433074 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_alert_test.4080433074
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.3222830905
Short name	T118
Test name
Test status
Simulation time	247343459 ps
CPU time	2.21 seconds
Started	Feb 09 08:20:37 AM UTC 25
Finished	Feb 09 08:20:40 AM UTC 25
Peak memory	210188 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222830905 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_handshake_intersig_mubi.3222830905
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_clk_status.2575743529
Short name	T330
Test name
Test status
Simulation time	19618272 ps
CPU time	1.1 seconds
Started	Feb 09 08:20:32 AM UTC 25
Finished	Feb 09 08:20:34 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575743529 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.2575743529
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_div_intersig_mubi.3453394636
Short name	T334
Test name
Test status
Simulation time	13987921 ps
CPU time	1.2 seconds
Started	Feb 09 08:20:38 AM UTC 25
Finished	Feb 09 08:20:40 AM UTC 25
Peak memory	210028 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453394636 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_div_intersig_mubi.3453394636
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_extclk.4200807463
Short name	T327
Test name
Test status
Simulation time	82674208 ps
CPU time	1.57 seconds
Started	Feb 09 08:20:25 AM UTC 25
Finished	Feb 09 08:20:28 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200807463 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.4200807463
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_frequency.398627228
Short name	T337
Test name
Test status
Simulation time	3225378166 ps
CPU time	17.9 seconds
Started	Feb 09 08:20:26 AM UTC 25
Finished	Feb 09 08:20:45 AM UTC 25
Peak memory	210776 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398627228 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.398627228
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_frequency_timeout.4035444938
Short name	T335
Test name
Test status
Simulation time	2220991463 ps
CPU time	16.24 seconds
Started	Feb 09 08:20:27 AM UTC 25
Finished	Feb 09 08:20:45 AM UTC 25
Peak memory	210712 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035444938 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_timeout.4035444938
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_idle_intersig_mubi.2409244862
Short name	T331
Test name
Test status
Simulation time	68348279 ps
CPU time	1.86 seconds
Started	Feb 09 08:20:32 AM UTC 25
Finished	Feb 09 08:20:35 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409244862 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_idle_intersig_mubi.2409244862
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.781761061
Short name	T333
Test name
Test status
Simulation time	74691148 ps
CPU time	1.42 seconds
Started	Feb 09 08:20:36 AM UTC 25
Finished	Feb 09 08:20:38 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781761061 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_lc_clk_byp_req_intersig_mubi.781761061
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.36712154
Short name	T332
Test name
Test status
Simulation time	15701507 ps
CPU time	1.22 seconds
Started	Feb 09 08:20:35 AM UTC 25
Finished	Feb 09 08:20:37 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36712154 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_lc_ctrl_intersig_mubi.36712154
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_peri.3666135250
Short name	T328
Test name
Test status
Simulation time	14992574 ps
CPU time	1.06 seconds
Started	Feb 09 08:20:28 AM UTC 25
Finished	Feb 09 08:20:31 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666135250 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.3666135250
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_regwen.3308773059
Short name	T176
Test name
Test status
Simulation time	1684270009 ps
CPU time	10.53 seconds
Started	Feb 09 08:20:39 AM UTC 25
Finished	Feb 09 08:20:51 AM UTC 25
Peak memory	210456 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308773059 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.3308773059
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_smoke.3834452243
Short name	T325
Test name
Test status
Simulation time	20893588 ps
CPU time	1.22 seconds
Started	Feb 09 08:20:24 AM UTC 25
Finished	Feb 09 08:20:27 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834452243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.3834452243
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_stress_all.3125153532
Short name	T348
Test name
Test status
Simulation time	4813447736 ps
CPU time	20.06 seconds
Started	Feb 09 08:20:41 AM UTC 25
Finished	Feb 09 08:21:03 AM UTC 25
Peak memory	210628 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125153532 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all.3125153532
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_stress_all_with_rand_reset.40198248
Short name	T182
Test name
Test status
Simulation time	169332434463 ps
CPU time	1033.18 seconds
Started	Feb 09 08:20:41 AM UTC 25
Finished	Feb 09 08:38:06 AM UTC 25
Peak memory	220128 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=40198248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.cl kmgr_stress_all_with_rand_reset.40198248
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/16.clkmgr_trans.1520599599
Short name	T329
Test name
Test status
Simulation time	25505886 ps
CPU time	1.15 seconds
Started	Feb 09 08:20:28 AM UTC 25
Finished	Feb 09 08:20:31 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520599599 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.1520599599
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/16.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/17.clkmgr_alert_test.1057795357
Short name	T352
Test name
Test status
Simulation time	32951541 ps
CPU time	1.23 seconds
Started	Feb 09 08:21:08 AM UTC 25
Finished	Feb 09 08:21:11 AM UTC 25
Peak memory	209844 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057795357 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_alert_test.1057795357
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.1465363642
Short name	T347
Test name
Test status
Simulation time	16545832 ps
CPU time	1.22 seconds
Started	Feb 09 08:20:59 AM UTC 25
Finished	Feb 09 08:21:02 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465363642 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_handshake_intersig_mubi.1465363642
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/17.clkmgr_clk_status.934922421
Short name	T343
Test name
Test status
Simulation time	25918264 ps
CPU time	1.13 seconds
Started	Feb 09 08:20:53 AM UTC 25
Finished	Feb 09 08:20:55 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934922421 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.934922421
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/17.clkmgr_div_intersig_mubi.3983613283
Short name	T349
Test name
Test status
Simulation time	33979829 ps
CPU time	1.26 seconds
Started	Feb 09 08:21:00 AM UTC 25
Finished	Feb 09 08:21:03 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983613283 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_div_intersig_mubi.3983613283
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/17.clkmgr_extclk.1904375526
Short name	T339
Test name
Test status
Simulation time	31863035 ps
CPU time	1.24 seconds
Started	Feb 09 08:20:47 AM UTC 25
Finished	Feb 09 08:20:49 AM UTC 25
Peak memory	209916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904375526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.1904375526
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/17.clkmgr_frequency.2787621024
Short name	T354
Test name
Test status
Simulation time	2477128966 ps
CPU time	22.82 seconds
Started	Feb 09 08:20:49 AM UTC 25
Finished	Feb 09 08:21:13 AM UTC 25
Peak memory	210644 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787621024 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.2787621024
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/17.clkmgr_frequency_timeout.2740004811
Short name	T353
Test name
Test status
Simulation time	1703192944 ps
CPU time	20.71 seconds
Started	Feb 09 08:20:50 AM UTC 25
Finished	Feb 09 08:21:12 AM UTC 25
Peak memory	210464 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740004811 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_timeout.2740004811
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/17.clkmgr_idle_intersig_mubi.1179143648
Short name	T344
Test name
Test status
Simulation time	23638702 ps
CPU time	1.33 seconds
Started	Feb 09 08:20:55 AM UTC 25
Finished	Feb 09 08:20:58 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179143648 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_idle_intersig_mubi.1179143648
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.640132204
Short name	T346
Test name
Test status
Simulation time	72703621 ps
CPU time	1.59 seconds
Started	Feb 09 08:20:58 AM UTC 25
Finished	Feb 09 08:21:01 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640132204 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_lc_clk_byp_req_intersig_mubi.640132204
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.3241175843
Short name	T345
Test name
Test status
Simulation time	24668404 ps
CPU time	1.13 seconds
Started	Feb 09 08:20:56 AM UTC 25
Finished	Feb 09 08:20:58 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241175843 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_lc_ctrl_intersig_mubi.3241175843
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/17.clkmgr_peri.3271024867
Short name	T341
Test name
Test status
Simulation time	24745188 ps
CPU time	1.2 seconds
Started	Feb 09 08:20:50 AM UTC 25
Finished	Feb 09 08:20:52 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271024867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.3271024867
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/17.clkmgr_regwen.770354860
Short name	T350
Test name
Test status
Simulation time	759563713 ps
CPU time	5.66 seconds
Started	Feb 09 08:21:02 AM UTC 25
Finished	Feb 09 08:21:08 AM UTC 25
Peak memory	210496 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770354860 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.770354860
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/17.clkmgr_smoke.1981767735
Short name	T340
Test name
Test status
Simulation time	43744061 ps
CPU time	1.34 seconds
Started	Feb 09 08:20:46 AM UTC 25
Finished	Feb 09 08:20:49 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981767735 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.1981767735
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/17.clkmgr_stress_all.2330799346
Short name	T417
Test name
Test status
Simulation time	8617878133 ps
CPU time	101.23 seconds
Started	Feb 09 08:21:08 AM UTC 25
Finished	Feb 09 08:22:52 AM UTC 25
Peak memory	210780 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330799346 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all.2330799346
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/17.clkmgr_stress_all_with_rand_reset.3352654103
Short name	T90
Test name
Test status
Simulation time	17617673673 ps
CPU time	323.8 seconds
Started	Feb 09 08:21:03 AM UTC 25
Finished	Feb 09 08:26:31 AM UTC 25
Peak memory	227148 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3352654103 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17. clkmgr_stress_all_with_rand_reset.3352654103
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/17.clkmgr_trans.2062908124
Short name	T342
Test name
Test status
Simulation time	63518514 ps
CPU time	1.48 seconds
Started	Feb 09 08:20:52 AM UTC 25
Finished	Feb 09 08:20:54 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062908124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.2062908124
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/18.clkmgr_alert_test.2065268725
Short name	T367
Test name
Test status
Simulation time	18086858 ps
CPU time	1.2 seconds
Started	Feb 09 08:21:21 AM UTC 25
Finished	Feb 09 08:21:23 AM UTC 25
Peak memory	208828 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065268725 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_alert_test.2065268725
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.3709700496
Short name	T363
Test name
Test status
Simulation time	29820122 ps
CPU time	1.33 seconds
Started	Feb 09 08:21:17 AM UTC 25
Finished	Feb 09 08:21:20 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709700496 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_handshake_intersig_mubi.3709700496
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/18.clkmgr_clk_status.3020824326
Short name	T357
Test name
Test status
Simulation time	16385707 ps
CPU time	1.01 seconds
Started	Feb 09 08:21:14 AM UTC 25
Finished	Feb 09 08:21:16 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020824326 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.3020824326
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/18.clkmgr_div_intersig_mubi.2194288988
Short name	T365
Test name
Test status
Simulation time	29238501 ps
CPU time	1.26 seconds
Started	Feb 09 08:21:19 AM UTC 25
Finished	Feb 09 08:21:21 AM UTC 25
Peak memory	210028 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194288988 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_div_intersig_mubi.2194288988
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/18.clkmgr_extclk.2419999107
Short name	T356
Test name
Test status
Simulation time	13970841 ps
CPU time	0.99 seconds
Started	Feb 09 08:21:14 AM UTC 25
Finished	Feb 09 08:21:16 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419999107 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.2419999107
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/18.clkmgr_frequency.1940328781
Short name	T364
Test name
Test status
Simulation time	316697156 ps
CPU time	4.73 seconds
Started	Feb 09 08:21:14 AM UTC 25
Finished	Feb 09 08:21:20 AM UTC 25
Peak memory	210192 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940328781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.1940328781
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/18.clkmgr_frequency_timeout.1517491121
Short name	T187
Test name
Test status
Simulation time	1815484194 ps
CPU time	19.16 seconds
Started	Feb 09 08:21:14 AM UTC 25
Finished	Feb 09 08:21:35 AM UTC 25
Peak memory	210464 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517491121 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_timeout.1517491121
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/18.clkmgr_idle_intersig_mubi.3869932336
Short name	T360
Test name
Test status
Simulation time	23122675 ps
CPU time	1.27 seconds
Started	Feb 09 08:21:16 AM UTC 25
Finished	Feb 09 08:21:19 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869932336 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_idle_intersig_mubi.3869932336
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.2441668076
Short name	T361
Test name
Test status
Simulation time	47215114 ps
CPU time	1.22 seconds
Started	Feb 09 08:21:17 AM UTC 25
Finished	Feb 09 08:21:20 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441668076 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_lc_clk_byp_req_intersig_mubi.2441668076
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.3665815295
Short name	T362
Test name
Test status
Simulation time	25134562 ps
CPU time	1.43 seconds
Started	Feb 09 08:21:17 AM UTC 25
Finished	Feb 09 08:21:20 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665815295 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_lc_ctrl_intersig_mubi.3665815295
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/18.clkmgr_peri.937738746
Short name	T358
Test name
Test status
Simulation time	88494785 ps
CPU time	1.52 seconds
Started	Feb 09 08:21:14 AM UTC 25
Finished	Feb 09 08:21:17 AM UTC 25
Peak memory	210084 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937738746 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.937738746
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/18.clkmgr_smoke.2489281650
Short name	T351
Test name
Test status
Simulation time	45242201 ps
CPU time	1.25 seconds
Started	Feb 09 08:21:08 AM UTC 25
Finished	Feb 09 08:21:11 AM UTC 25
Peak memory	210268 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489281650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.2489281650
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/18.clkmgr_stress_all.1831929143
Short name	T418
Test name
Test status
Simulation time	11499350413 ps
CPU time	89.73 seconds
Started	Feb 09 08:21:21 AM UTC 25
Finished	Feb 09 08:22:52 AM UTC 25
Peak memory	210680 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831929143 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all.1831929143
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/18.clkmgr_stress_all_with_rand_reset.598236631
Short name	T91
Test name
Test status
Simulation time	28937262408 ps
CPU time	329.93 seconds
Started	Feb 09 08:21:21 AM UTC 25
Finished	Feb 09 08:26:55 AM UTC 25
Peak memory	227152 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=598236631 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.c lkmgr_stress_all_with_rand_reset.598236631
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/18.clkmgr_trans.944900753
Short name	T359
Test name
Test status
Simulation time	65484090 ps
CPU time	1.63 seconds
Started	Feb 09 08:21:14 AM UTC 25
Finished	Feb 09 08:21:17 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944900753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.944900753
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/18.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/19.clkmgr_alert_test.1984578662
Short name	T191
Test name
Test status
Simulation time	29013249 ps
CPU time	1.2 seconds
Started	Feb 09 08:21:38 AM UTC 25
Finished	Feb 09 08:21:41 AM UTC 25
Peak memory	209856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984578662 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_alert_test.1984578662
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.4224171156
Short name	T119
Test name
Test status
Simulation time	46149542 ps
CPU time	1.5 seconds
Started	Feb 09 08:21:35 AM UTC 25
Finished	Feb 09 08:21:38 AM UTC 25
Peak memory	209916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224171156 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_handshake_intersig_mubi.4224171156
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/19.clkmgr_clk_status.666802815
Short name	T371
Test name
Test status
Simulation time	13940453 ps
CPU time	1.02 seconds
Started	Feb 09 08:21:30 AM UTC 25
Finished	Feb 09 08:21:33 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666802815 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.666802815
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/19.clkmgr_div_intersig_mubi.3351514079
Short name	T190
Test name
Test status
Simulation time	34136073 ps
CPU time	1.33 seconds
Started	Feb 09 08:21:35 AM UTC 25
Finished	Feb 09 08:21:37 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351514079 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_div_intersig_mubi.3351514079
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/19.clkmgr_extclk.1422161272
Short name	T368
Test name
Test status
Simulation time	22799376 ps
CPU time	1.27 seconds
Started	Feb 09 08:21:22 AM UTC 25
Finished	Feb 09 08:21:24 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422161272 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.1422161272
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/19.clkmgr_frequency.612816116
Short name	T375
Test name
Test status
Simulation time	2383659509 ps
CPU time	21.84 seconds
Started	Feb 09 08:21:24 AM UTC 25
Finished	Feb 09 08:21:47 AM UTC 25
Peak memory	210620 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612816116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.612816116
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/19.clkmgr_frequency_timeout.433424766
Short name	T374
Test name
Test status
Simulation time	2424004644 ps
CPU time	21.56 seconds
Started	Feb 09 08:21:24 AM UTC 25
Finished	Feb 09 08:21:47 AM UTC 25
Peak memory	210436 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433424766 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_timeout.433424766
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/19.clkmgr_idle_intersig_mubi.1615336552
Short name	T186
Test name
Test status
Simulation time	27227270 ps
CPU time	1.36 seconds
Started	Feb 09 08:21:31 AM UTC 25
Finished	Feb 09 08:21:34 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615336552 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_idle_intersig_mubi.1615336552
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.2834857194
Short name	T188
Test name
Test status
Simulation time	26833919 ps
CPU time	0.97 seconds
Started	Feb 09 08:21:34 AM UTC 25
Finished	Feb 09 08:21:36 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834857194 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_lc_clk_byp_req_intersig_mubi.2834857194
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.3077115411
Short name	T189
Test name
Test status
Simulation time	67368248 ps
CPU time	1.53 seconds
Started	Feb 09 08:21:34 AM UTC 25
Finished	Feb 09 08:21:36 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077115411 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_lc_ctrl_intersig_mubi.3077115411
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/19.clkmgr_peri.3330183778
Short name	T369
Test name
Test status
Simulation time	20944408 ps
CPU time	1.12 seconds
Started	Feb 09 08:21:25 AM UTC 25
Finished	Feb 09 08:21:27 AM UTC 25
Peak memory	210088 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330183778 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.3330183778
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/19.clkmgr_regwen.291819839
Short name	T373
Test name
Test status
Simulation time	1249236561 ps
CPU time	8.87 seconds
Started	Feb 09 08:21:36 AM UTC 25
Finished	Feb 09 08:21:46 AM UTC 25
Peak memory	210392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291819839 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.291819839
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/19.clkmgr_smoke.931631771
Short name	T366
Test name
Test status
Simulation time	23070240 ps
CPU time	1.13 seconds
Started	Feb 09 08:21:21 AM UTC 25
Finished	Feb 09 08:21:23 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931631771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.931631771
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/19.clkmgr_stress_all.3690452293
Short name	T383
Test name
Test status
Simulation time	3549921922 ps
CPU time	22.32 seconds
Started	Feb 09 08:21:37 AM UTC 25
Finished	Feb 09 08:22:01 AM UTC 25
Peak memory	210852 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690452293 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all.3690452293
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/19.clkmgr_stress_all_with_rand_reset.4165758434
Short name	T831
Test name
Test status
Simulation time	39823462898 ps
CPU time	809.86 seconds
Started	Feb 09 08:21:37 AM UTC 25
Finished	Feb 09 08:35:16 AM UTC 25
Peak memory	222452 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=4165758434 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19. clkmgr_stress_all_with_rand_reset.4165758434
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/19.clkmgr_trans.1606875216
Short name	T370
Test name
Test status
Simulation time	17575445 ps
CPU time	1.06 seconds
Started	Feb 09 08:21:28 AM UTC 25
Finished	Feb 09 08:21:31 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606875216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.1606875216
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/19.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_alert_test.312798757
Short name	T64
Test name
Test status
Simulation time	14880398 ps
CPU time	1.09 seconds
Started	Feb 09 08:16:35 AM UTC 25
Finished	Feb 09 08:16:37 AM UTC 25
Peak memory	209856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312798757 -assert nopostproc +U VM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_alert_test.312798757
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.2122989267
Short name	T62
Test name
Test status
Simulation time	24109615 ps
CPU time	1.42 seconds
Started	Feb 09 08:16:31 AM UTC 25
Finished	Feb 09 08:16:34 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122989267 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_handshake_intersig_mubi.2122989267
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_clk_status.1980773892
Short name	T26
Test name
Test status
Simulation time	14171993 ps
CPU time	1.12 seconds
Started	Feb 09 08:16:28 AM UTC 25
Finished	Feb 09 08:16:30 AM UTC 25
Peak memory	210028 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980773892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.1980773892
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_div_intersig_mubi.3130642587
Short name	T63
Test name
Test status
Simulation time	28178101 ps
CPU time	1.14 seconds
Started	Feb 09 08:16:32 AM UTC 25
Finished	Feb 09 08:16:35 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130642587 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_div_intersig_mubi.3130642587
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_extclk.3094708637
Short name	T23
Test name
Test status
Simulation time	37159199 ps
CPU time	1.28 seconds
Started	Feb 09 08:16:25 AM UTC 25
Finished	Feb 09 08:16:27 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094708637 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.3094708637
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_frequency.1782338553
Short name	T9
Test name
Test status
Simulation time	518085318 ps
CPU time	5 seconds
Started	Feb 09 08:16:25 AM UTC 25
Finished	Feb 09 08:16:31 AM UTC 25
Peak memory	210436 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782338553 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.1782338553
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_frequency_timeout.303490718
Short name	T40
Test name
Test status
Simulation time	395000371 ps
CPU time	4.22 seconds
Started	Feb 09 08:16:27 AM UTC 25
Finished	Feb 09 08:16:32 AM UTC 25
Peak memory	210280 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303490718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_timeout.303490718
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_idle_intersig_mubi.3903365559
Short name	T60
Test name
Test status
Simulation time	28893175 ps
CPU time	1.39 seconds
Started	Feb 09 08:16:30 AM UTC 25
Finished	Feb 09 08:16:33 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903365559 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_idle_intersig_mubi.3903365559
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.167474363
Short name	T61
Test name
Test status
Simulation time	36353639 ps
CPU time	1.17 seconds
Started	Feb 09 08:16:31 AM UTC 25
Finished	Feb 09 08:16:34 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167474363 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_lc_clk_byp_req_intersig_mubi.167474363
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.1567037184
Short name	T59
Test name
Test status
Simulation time	33083231 ps
CPU time	1.2 seconds
Started	Feb 09 08:16:30 AM UTC 25
Finished	Feb 09 08:16:32 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567037184 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_lc_ctrl_intersig_mubi.1567037184
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_peri.301740166
Short name	T25
Test name
Test status
Simulation time	21398050 ps
CPU time	1.16 seconds
Started	Feb 09 08:16:27 AM UTC 25
Finished	Feb 09 08:16:29 AM UTC 25
Peak memory	210088 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301740166 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.301740166
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_regwen.3897916883
Short name	T27
Test name
Test status
Simulation time	1086710321 ps
CPU time	8.2 seconds
Started	Feb 09 08:16:33 AM UTC 25
Finished	Feb 09 08:16:43 AM UTC 25
Peak memory	210392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897916883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.3897916883
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_sec_cm.3887758845
Short name	T67
Test name
Test status
Simulation time	156577662 ps
CPU time	3.48 seconds
Started	Feb 09 08:16:33 AM UTC 25
Finished	Feb 09 08:16:38 AM UTC 25
Peak memory	241172 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887758845 -assert nopostproc +U VM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_sec_cm.3887758845
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_smoke.3812454709
Short name	T21
Test name
Test status
Simulation time	48131736 ps
CPU time	1.25 seconds
Started	Feb 09 08:16:24 AM UTC 25
Finished	Feb 09 08:16:26 AM UTC 25
Peak memory	209664 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812454709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.3812454709
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_stress_all.2920571746
Short name	T18
Test name
Test status
Simulation time	10964164499 ps
CPU time	71.52 seconds
Started	Feb 09 08:16:35 AM UTC 25
Finished	Feb 09 08:17:48 AM UTC 25
Peak memory	210976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920571746 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all.2920571746
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/2.clkmgr_trans.2637274166
Short name	T24
Test name
Test status
Simulation time	15203015 ps
CPU time	1.07 seconds
Started	Feb 09 08:16:27 AM UTC 25
Finished	Feb 09 08:16:29 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637274166 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.2637274166
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/2.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/20.clkmgr_alert_test.3080215714
Short name	T388
Test name
Test status
Simulation time	14443159 ps
CPU time	1.1 seconds
Started	Feb 09 08:22:01 AM UTC 25
Finished	Feb 09 08:22:04 AM UTC 25
Peak memory	210040 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080215714 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_alert_test.3080215714
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/20.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.2010438415
Short name	T120
Test name
Test status
Simulation time	23257337 ps
CPU time	1.37 seconds
Started	Feb 09 08:21:53 AM UTC 25
Finished	Feb 09 08:21:56 AM UTC 25
Peak memory	209916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010438415 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_handshake_intersig_mubi.2010438415
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/20.clkmgr_clk_status.272325905
Short name	T378
Test name
Test status
Simulation time	13308819 ps
CPU time	1.12 seconds
Started	Feb 09 08:21:49 AM UTC 25
Finished	Feb 09 08:21:51 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272325905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.272325905
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/20.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/20.clkmgr_div_intersig_mubi.2100946890
Short name	T382
Test name
Test status
Simulation time	28057630 ps
CPU time	1.45 seconds
Started	Feb 09 08:21:54 AM UTC 25
Finished	Feb 09 08:21:57 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100946890 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_div_intersig_mubi.2100946890
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/20.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/20.clkmgr_extclk.1136141787
Short name	T372
Test name
Test status
Simulation time	33825669 ps
CPU time	1.2 seconds
Started	Feb 09 08:21:41 AM UTC 25
Finished	Feb 09 08:21:44 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136141787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.1136141787
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/20.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/20.clkmgr_frequency.2601844233
Short name	T384
Test name
Test status
Simulation time	2671269142 ps
CPU time	18.45 seconds
Started	Feb 09 08:21:41 AM UTC 25
Finished	Feb 09 08:22:01 AM UTC 25
Peak memory	210680 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601844233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.2601844233
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/20.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/20.clkmgr_frequency_timeout.1324345408
Short name	T386
Test name
Test status
Simulation time	2194024795 ps
CPU time	15.38 seconds
Started	Feb 09 08:21:44 AM UTC 25
Finished	Feb 09 08:22:01 AM UTC 25
Peak memory	210800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324345408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_timeout.1324345408
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/20.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/20.clkmgr_idle_intersig_mubi.2977669949
Short name	T379
Test name
Test status
Simulation time	19537094 ps
CPU time	1.14 seconds
Started	Feb 09 08:21:50 AM UTC 25
Finished	Feb 09 08:21:52 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977669949 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_idle_intersig_mubi.2977669949
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/20.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.3263667088
Short name	T381
Test name
Test status
Simulation time	18939430 ps
CPU time	1.17 seconds
Started	Feb 09 08:21:52 AM UTC 25
Finished	Feb 09 08:21:54 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263667088 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_lc_clk_byp_req_intersig_mubi.3263667088
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.3250668927
Short name	T380
Test name
Test status
Simulation time	30691681 ps
CPU time	1.56 seconds
Started	Feb 09 08:21:51 AM UTC 25
Finished	Feb 09 08:21:53 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250668927 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_lc_ctrl_intersig_mubi.3250668927
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/20.clkmgr_peri.3447595844
Short name	T376
Test name
Test status
Simulation time	19864763 ps
CPU time	1.19 seconds
Started	Feb 09 08:21:46 AM UTC 25
Finished	Feb 09 08:21:49 AM UTC 25
Peak memory	210148 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447595844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.3447595844
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/20.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/20.clkmgr_regwen.3991984162
Short name	T385
Test name
Test status
Simulation time	460071777 ps
CPU time	4.63 seconds
Started	Feb 09 08:21:55 AM UTC 25
Finished	Feb 09 08:22:01 AM UTC 25
Peak memory	210588 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991984162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.3991984162
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/20.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/20.clkmgr_smoke.3507723610
Short name	T156
Test name
Test status
Simulation time	37154226 ps
CPU time	1.23 seconds
Started	Feb 09 08:21:38 AM UTC 25
Finished	Feb 09 08:21:41 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507723610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.3507723610
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/20.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/20.clkmgr_stress_all.3202762984
Short name	T387
Test name
Test status
Simulation time	204637066 ps
CPU time	3.37 seconds
Started	Feb 09 08:21:57 AM UTC 25
Finished	Feb 09 08:22:02 AM UTC 25
Peak memory	210520 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202762984 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all.3202762984
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/20.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/20.clkmgr_stress_all_with_rand_reset.3676824073
Short name	T92
Test name
Test status
Simulation time	18887333056 ps
CPU time	322.3 seconds
Started	Feb 09 08:21:56 AM UTC 25
Finished	Feb 09 08:27:23 AM UTC 25
Peak memory	226504 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3676824073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20. clkmgr_stress_all_with_rand_reset.3676824073
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/20.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/20.clkmgr_trans.1927196199
Short name	T377
Test name
Test status
Simulation time	15337557 ps
CPU time	1.12 seconds
Started	Feb 09 08:21:48 AM UTC 25
Finished	Feb 09 08:21:50 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927196199 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.1927196199
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/20.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/21.clkmgr_alert_test.1364071047
Short name	T401
Test name
Test status
Simulation time	32444598 ps
CPU time	1.17 seconds
Started	Feb 09 08:22:27 AM UTC 25
Finished	Feb 09 08:22:29 AM UTC 25
Peak memory	208888 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364071047 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_alert_test.1364071047
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/21.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.3054093006
Short name	T121
Test name
Test status
Simulation time	49503168 ps
CPU time	1.63 seconds
Started	Feb 09 08:22:11 AM UTC 25
Finished	Feb 09 08:22:14 AM UTC 25
Peak memory	209916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054093006 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_handshake_intersig_mubi.3054093006
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/21.clkmgr_clk_status.691186900
Short name	T392
Test name
Test status
Simulation time	36953578 ps
CPU time	1.1 seconds
Started	Feb 09 08:22:06 AM UTC 25
Finished	Feb 09 08:22:08 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691186900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.691186900
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/21.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/21.clkmgr_div_intersig_mubi.2897920506
Short name	T399
Test name
Test status
Simulation time	26949069 ps
CPU time	1.13 seconds
Started	Feb 09 08:22:27 AM UTC 25
Finished	Feb 09 08:22:29 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897920506 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_div_intersig_mubi.2897920506
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/21.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/21.clkmgr_extclk.154694160
Short name	T389
Test name
Test status
Simulation time	66960555 ps
CPU time	1.57 seconds
Started	Feb 09 08:22:03 AM UTC 25
Finished	Feb 09 08:22:05 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154694160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.154694160
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/21.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/21.clkmgr_frequency.2493291622
Short name	T398
Test name
Test status
Simulation time	1519877318 ps
CPU time	23.49 seconds
Started	Feb 09 08:22:03 AM UTC 25
Finished	Feb 09 08:22:28 AM UTC 25
Peak memory	210244 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493291622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.2493291622
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/21.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/21.clkmgr_frequency_timeout.2587231075
Short name	T397
Test name
Test status
Simulation time	2511898759 ps
CPU time	17.9 seconds
Started	Feb 09 08:22:03 AM UTC 25
Finished	Feb 09 08:22:22 AM UTC 25
Peak memory	210612 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587231075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_timeout.2587231075
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/21.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/21.clkmgr_idle_intersig_mubi.3394586020
Short name	T395
Test name
Test status
Simulation time	176088278 ps
CPU time	2.34 seconds
Started	Feb 09 08:22:08 AM UTC 25
Finished	Feb 09 08:22:11 AM UTC 25
Peak memory	210184 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394586020 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_idle_intersig_mubi.3394586020
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/21.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.2684990501
Short name	T396
Test name
Test status
Simulation time	51460283 ps
CPU time	1.32 seconds
Started	Feb 09 08:22:09 AM UTC 25
Finished	Feb 09 08:22:12 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684990501 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_lc_clk_byp_req_intersig_mubi.2684990501
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.308958487
Short name	T393
Test name
Test status
Simulation time	64743525 ps
CPU time	1.48 seconds
Started	Feb 09 08:22:08 AM UTC 25
Finished	Feb 09 08:22:11 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308958487 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_lc_ctrl_intersig_mubi.308958487
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/21.clkmgr_peri.3108878680
Short name	T391
Test name
Test status
Simulation time	17492747 ps
CPU time	1.23 seconds
Started	Feb 09 08:22:05 AM UTC 25
Finished	Feb 09 08:22:07 AM UTC 25
Peak memory	210088 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108878680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.3108878680
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/21.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/21.clkmgr_regwen.1686383420
Short name	T400
Test name
Test status
Simulation time	68623120 ps
CPU time	1.27 seconds
Started	Feb 09 08:22:27 AM UTC 25
Finished	Feb 09 08:22:29 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686383420 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.1686383420
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/21.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/21.clkmgr_smoke.3141377748
Short name	T157
Test name
Test status
Simulation time	16241973 ps
CPU time	1.12 seconds
Started	Feb 09 08:22:01 AM UTC 25
Finished	Feb 09 08:22:04 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141377748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.3141377748
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/21.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/21.clkmgr_stress_all.2623455887
Short name	T427
Test name
Test status
Simulation time	3835866481 ps
CPU time	30.11 seconds
Started	Feb 09 08:22:27 AM UTC 25
Finished	Feb 09 08:22:58 AM UTC 25
Peak memory	210616 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623455887 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all.2623455887
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/21.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/21.clkmgr_stress_all_with_rand_reset.2971908090
Short name	T828
Test name
Test status
Simulation time	54526123436 ps
CPU time	635.31 seconds
Started	Feb 09 08:22:27 AM UTC 25
Finished	Feb 09 08:33:10 AM UTC 25
Peak memory	220152 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2971908090 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21. clkmgr_stress_all_with_rand_reset.2971908090
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/21.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/21.clkmgr_trans.2559156483
Short name	T390
Test name
Test status
Simulation time	24958680 ps
CPU time	1 seconds
Started	Feb 09 08:22:05 AM UTC 25
Finished	Feb 09 08:22:07 AM UTC 25
Peak memory	210028 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559156483 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.2559156483
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/21.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/22.clkmgr_alert_test.1592793503
Short name	T411
Test name
Test status
Simulation time	40904772 ps
CPU time	1.18 seconds
Started	Feb 09 08:22:38 AM UTC 25
Finished	Feb 09 08:22:40 AM UTC 25
Peak memory	209856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592793503 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_alert_test.1592793503
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/22.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.3577311212
Short name	T122
Test name
Test status
Simulation time	31126928 ps
CPU time	1.36 seconds
Started	Feb 09 08:22:33 AM UTC 25
Finished	Feb 09 08:22:36 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577311212 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_handshake_intersig_mubi.3577311212
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/22.clkmgr_clk_status.2165481753
Short name	T404
Test name
Test status
Simulation time	14541561 ps
CPU time	1.14 seconds
Started	Feb 09 08:22:30 AM UTC 25
Finished	Feb 09 08:22:32 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165481753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.2165481753
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/22.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/22.clkmgr_div_intersig_mubi.79765796
Short name	T410
Test name
Test status
Simulation time	25443503 ps
CPU time	1.34 seconds
Started	Feb 09 08:22:34 AM UTC 25
Finished	Feb 09 08:22:37 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79765796 -assert nopostpr oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_div_intersig_mubi.79765796
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/22.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/22.clkmgr_extclk.4118065154
Short name	T403
Test name
Test status
Simulation time	23810271 ps
CPU time	1.14 seconds
Started	Feb 09 08:22:27 AM UTC 25
Finished	Feb 09 08:22:29 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118065154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.4118065154
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/22.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/22.clkmgr_frequency.800652118
Short name	T415
Test name
Test status
Simulation time	1636927826 ps
CPU time	21.95 seconds
Started	Feb 09 08:22:28 AM UTC 25
Finished	Feb 09 08:22:51 AM UTC 25
Peak memory	210248 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800652118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.800652118
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/22.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/22.clkmgr_frequency_timeout.179346622
Short name	T416
Test name
Test status
Simulation time	1821051783 ps
CPU time	19.94 seconds
Started	Feb 09 08:22:30 AM UTC 25
Finished	Feb 09 08:22:51 AM UTC 25
Peak memory	210236 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179346622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_timeout.179346622
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/22.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/22.clkmgr_idle_intersig_mubi.3939376859
Short name	T407
Test name
Test status
Simulation time	136635635 ps
CPU time	1.88 seconds
Started	Feb 09 08:22:30 AM UTC 25
Finished	Feb 09 08:22:33 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939376859 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_idle_intersig_mubi.3939376859
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/22.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.3578412331
Short name	T409
Test name
Test status
Simulation time	105930300 ps
CPU time	1.62 seconds
Started	Feb 09 08:22:33 AM UTC 25
Finished	Feb 09 08:22:36 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578412331 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_lc_clk_byp_req_intersig_mubi.3578412331
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.3679258179
Short name	T408
Test name
Test status
Simulation time	29250440 ps
CPU time	1.33 seconds
Started	Feb 09 08:22:33 AM UTC 25
Finished	Feb 09 08:22:36 AM UTC 25
Peak memory	210028 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679258179 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_lc_ctrl_intersig_mubi.3679258179
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/22.clkmgr_peri.4199372706
Short name	T405
Test name
Test status
Simulation time	60009734 ps
CPU time	1.45 seconds
Started	Feb 09 08:22:30 AM UTC 25
Finished	Feb 09 08:22:33 AM UTC 25
Peak memory	210024 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199372706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.4199372706
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/22.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/22.clkmgr_regwen.3805626651
Short name	T412
Test name
Test status
Simulation time	237807413 ps
CPU time	2.55 seconds
Started	Feb 09 08:22:37 AM UTC 25
Finished	Feb 09 08:22:40 AM UTC 25
Peak memory	210184 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805626651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.3805626651
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/22.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/22.clkmgr_smoke.2474354306
Short name	T402
Test name
Test status
Simulation time	13934718 ps
CPU time	1.2 seconds
Started	Feb 09 08:22:27 AM UTC 25
Finished	Feb 09 08:22:29 AM UTC 25
Peak memory	210324 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474354306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.2474354306
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/22.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/22.clkmgr_stress_all.3911335894
Short name	T463
Test name
Test status
Simulation time	9877012625 ps
CPU time	58.35 seconds
Started	Feb 09 08:22:37 AM UTC 25
Finished	Feb 09 08:23:37 AM UTC 25
Peak memory	210908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911335894 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all.3911335894
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/22.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/22.clkmgr_stress_all_with_rand_reset.2268718533
Short name	T822
Test name
Test status
Simulation time	28080023844 ps
CPU time	512.35 seconds
Started	Feb 09 08:22:37 AM UTC 25
Finished	Feb 09 08:31:15 AM UTC 25
Peak memory	220216 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2268718533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22. clkmgr_stress_all_with_rand_reset.2268718533
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/22.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/22.clkmgr_trans.1070845427
Short name	T406
Test name
Test status
Simulation time	33350473 ps
CPU time	1.54 seconds
Started	Feb 09 08:22:30 AM UTC 25
Finished	Feb 09 08:22:33 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070845427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.1070845427
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/22.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/23.clkmgr_alert_test.2748634570
Short name	T428
Test name
Test status
Simulation time	22064439 ps
CPU time	1.15 seconds
Started	Feb 09 08:22:57 AM UTC 25
Finished	Feb 09 08:22:59 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748634570 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_alert_test.2748634570
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/23.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.282142181
Short name	T426
Test name
Test status
Simulation time	89421686 ps
CPU time	1.52 seconds
Started	Feb 09 08:22:55 AM UTC 25
Finished	Feb 09 08:22:57 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282142181 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_handshake_intersig_mubi.282142181
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/23.clkmgr_clk_status.1703563356
Short name	T421
Test name
Test status
Simulation time	16235930 ps
CPU time	1.13 seconds
Started	Feb 09 08:22:52 AM UTC 25
Finished	Feb 09 08:22:55 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703563356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.1703563356
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/23.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/23.clkmgr_div_intersig_mubi.1909868143
Short name	T425
Test name
Test status
Simulation time	29072664 ps
CPU time	1.12 seconds
Started	Feb 09 08:22:55 AM UTC 25
Finished	Feb 09 08:22:57 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909868143 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_div_intersig_mubi.1909868143
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/23.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/23.clkmgr_extclk.2458913484
Short name	T413
Test name
Test status
Simulation time	102352286 ps
CPU time	1.71 seconds
Started	Feb 09 08:22:41 AM UTC 25
Finished	Feb 09 08:22:44 AM UTC 25
Peak memory	209572 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458913484 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.2458913484
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/23.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/23.clkmgr_frequency.3243652848
Short name	T430
Test name
Test status
Simulation time	2242916670 ps
CPU time	19.92 seconds
Started	Feb 09 08:22:44 AM UTC 25
Finished	Feb 09 08:23:05 AM UTC 25
Peak memory	210584 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243652848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.3243652848
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/23.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/23.clkmgr_frequency_timeout.2434737734
Short name	T420
Test name
Test status
Simulation time	617506724 ps
CPU time	7.44 seconds
Started	Feb 09 08:22:45 AM UTC 25
Finished	Feb 09 08:22:54 AM UTC 25
Peak memory	210272 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434737734 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_timeout.2434737734
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/23.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/23.clkmgr_idle_intersig_mubi.2723136034
Short name	T423
Test name
Test status
Simulation time	68223222 ps
CPU time	1.7 seconds
Started	Feb 09 08:22:52 AM UTC 25
Finished	Feb 09 08:22:55 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723136034 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_idle_intersig_mubi.2723136034
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/23.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.603236250
Short name	T424
Test name
Test status
Simulation time	75544467 ps
CPU time	1.59 seconds
Started	Feb 09 08:22:54 AM UTC 25
Finished	Feb 09 08:22:56 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603236250 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_lc_clk_byp_req_intersig_mubi.603236250
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.1259956887
Short name	T422
Test name
Test status
Simulation time	41483019 ps
CPU time	1.27 seconds
Started	Feb 09 08:22:52 AM UTC 25
Finished	Feb 09 08:22:55 AM UTC 25
Peak memory	210028 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259956887 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_lc_ctrl_intersig_mubi.1259956887
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/23.clkmgr_peri.3920647584
Short name	T414
Test name
Test status
Simulation time	23289056 ps
CPU time	1.19 seconds
Started	Feb 09 08:22:48 AM UTC 25
Finished	Feb 09 08:22:50 AM UTC 25
Peak memory	210088 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920647584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.3920647584
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/23.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/23.clkmgr_regwen.2429782455
Short name	T429
Test name
Test status
Simulation time	309935863 ps
CPU time	2.69 seconds
Started	Feb 09 08:22:56 AM UTC 25
Finished	Feb 09 08:23:00 AM UTC 25
Peak memory	210184 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429782455 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.2429782455
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/23.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/23.clkmgr_smoke.874564470
Short name	T158
Test name
Test status
Simulation time	53221089 ps
CPU time	1.29 seconds
Started	Feb 09 08:22:41 AM UTC 25
Finished	Feb 09 08:22:43 AM UTC 25
Peak memory	209504 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874564470 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.874564470
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/23.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/23.clkmgr_stress_all.231520620
Short name	T445
Test name
Test status
Simulation time	2212422973 ps
CPU time	19.64 seconds
Started	Feb 09 08:22:56 AM UTC 25
Finished	Feb 09 08:23:17 AM UTC 25
Peak memory	210872 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231520620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all.231520620
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/23.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/23.clkmgr_stress_all_with_rand_reset.1136504441
Short name	T836
Test name
Test status
Simulation time	59134441378 ps
CPU time	956.41 seconds
Started	Feb 09 08:22:56 AM UTC 25
Finished	Feb 09 08:39:03 AM UTC 25
Peak memory	220152 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1136504441 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23. clkmgr_stress_all_with_rand_reset.1136504441
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/23.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/23.clkmgr_trans.3332460987
Short name	T419
Test name
Test status
Simulation time	60470635 ps
CPU time	1.23 seconds
Started	Feb 09 08:22:51 AM UTC 25
Finished	Feb 09 08:22:54 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332460987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.3332460987
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/23.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/24.clkmgr_alert_test.286726186
Short name	T443
Test name
Test status
Simulation time	37034956 ps
CPU time	1.15 seconds
Started	Feb 09 08:23:12 AM UTC 25
Finished	Feb 09 08:23:14 AM UTC 25
Peak memory	210036 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286726186 -assert nopostproc +U VM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_alert_test.286726186
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/24.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.1638229892
Short name	T441
Test name
Test status
Simulation time	27212099 ps
CPU time	1.46 seconds
Started	Feb 09 08:23:10 AM UTC 25
Finished	Feb 09 08:23:12 AM UTC 25
Peak memory	209856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638229892 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_handshake_intersig_mubi.1638229892
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/24.clkmgr_clk_status.404367562
Short name	T435
Test name
Test status
Simulation time	12362595 ps
CPU time	1.12 seconds
Started	Feb 09 08:23:06 AM UTC 25
Finished	Feb 09 08:23:09 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404367562 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.404367562
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/24.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/24.clkmgr_div_intersig_mubi.3806531276
Short name	T440
Test name
Test status
Simulation time	31495506 ps
CPU time	1.32 seconds
Started	Feb 09 08:23:10 AM UTC 25
Finished	Feb 09 08:23:12 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806531276 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_div_intersig_mubi.3806531276
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/24.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/24.clkmgr_extclk.4103709428
Short name	T432
Test name
Test status
Simulation time	69590725 ps
CPU time	1.43 seconds
Started	Feb 09 08:23:05 AM UTC 25
Finished	Feb 09 08:23:08 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103709428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.4103709428
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/24.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/24.clkmgr_frequency.3606430820
Short name	T436
Test name
Test status
Simulation time	223710433 ps
CPU time	2.49 seconds
Started	Feb 09 08:23:05 AM UTC 25
Finished	Feb 09 08:23:09 AM UTC 25
Peak memory	210244 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606430820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.3606430820
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/24.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/24.clkmgr_frequency_timeout.3743060819
Short name	T438
Test name
Test status
Simulation time	525055188 ps
CPU time	3.54 seconds
Started	Feb 09 08:23:06 AM UTC 25
Finished	Feb 09 08:23:11 AM UTC 25
Peak memory	210464 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743060819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_timeout.3743060819
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/24.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/24.clkmgr_idle_intersig_mubi.404309687
Short name	T439
Test name
Test status
Simulation time	47974842 ps
CPU time	1.48 seconds
Started	Feb 09 08:23:08 AM UTC 25
Finished	Feb 09 08:23:11 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404309687 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_idle_intersig_mubi.404309687
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/24.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.2161914544
Short name	T442
Test name
Test status
Simulation time	68038925 ps
CPU time	1.6 seconds
Started	Feb 09 08:23:10 AM UTC 25
Finished	Feb 09 08:23:12 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161914544 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_lc_clk_byp_req_intersig_mubi.2161914544
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.3329923094
Short name	T437
Test name
Test status
Simulation time	26384468 ps
CPU time	1.33 seconds
Started	Feb 09 08:23:08 AM UTC 25
Finished	Feb 09 08:23:11 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329923094 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_lc_ctrl_intersig_mubi.3329923094
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/24.clkmgr_peri.1273834920
Short name	T433
Test name
Test status
Simulation time	17565669 ps
CPU time	0.99 seconds
Started	Feb 09 08:23:06 AM UTC 25
Finished	Feb 09 08:23:08 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273834920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.1273834920
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/24.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/24.clkmgr_regwen.2972587787
Short name	T177
Test name
Test status
Simulation time	1148589511 ps
CPU time	12.6 seconds
Started	Feb 09 08:23:10 AM UTC 25
Finished	Feb 09 08:23:24 AM UTC 25
Peak memory	210648 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972587787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.2972587787
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/24.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/24.clkmgr_smoke.2697172141
Short name	T431
Test name
Test status
Simulation time	18527173 ps
CPU time	1.22 seconds
Started	Feb 09 08:23:05 AM UTC 25
Finished	Feb 09 08:23:07 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697172141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.2697172141
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/24.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/24.clkmgr_stress_all.2582755556
Short name	T476
Test name
Test status
Simulation time	4068466720 ps
CPU time	38.84 seconds
Started	Feb 09 08:23:12 AM UTC 25
Finished	Feb 09 08:23:52 AM UTC 25
Peak memory	210716 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582755556 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all.2582755556
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/24.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/24.clkmgr_stress_all_with_rand_reset.1427067345
Short name	T827
Test name
Test status
Simulation time	27660204237 ps
CPU time	544.77 seconds
Started	Feb 09 08:23:12 AM UTC 25
Finished	Feb 09 08:32:23 AM UTC 25
Peak memory	220168 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1427067345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24. clkmgr_stress_all_with_rand_reset.1427067345
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/24.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/24.clkmgr_trans.1446368953
Short name	T434
Test name
Test status
Simulation time	22692437 ps
CPU time	1.14 seconds
Started	Feb 09 08:23:06 AM UTC 25
Finished	Feb 09 08:23:08 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446368953 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.1446368953
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/24.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/25.clkmgr_alert_test.2987761945
Short name	T457
Test name
Test status
Simulation time	29949686 ps
CPU time	1.35 seconds
Started	Feb 09 08:23:24 AM UTC 25
Finished	Feb 09 08:23:27 AM UTC 25
Peak memory	208888 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987761945 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_alert_test.2987761945
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/25.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.3767028883
Short name	T453
Test name
Test status
Simulation time	16729783 ps
CPU time	1.24 seconds
Started	Feb 09 08:23:21 AM UTC 25
Finished	Feb 09 08:23:23 AM UTC 25
Peak memory	209916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767028883 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_handshake_intersig_mubi.3767028883
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/25.clkmgr_clk_status.1274756028
Short name	T449
Test name
Test status
Simulation time	98370166 ps
CPU time	1.4 seconds
Started	Feb 09 08:23:18 AM UTC 25
Finished	Feb 09 08:23:20 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274756028 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.1274756028
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/25.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/25.clkmgr_div_intersig_mubi.2604628546
Short name	T455
Test name
Test status
Simulation time	85313564 ps
CPU time	1.54 seconds
Started	Feb 09 08:23:23 AM UTC 25
Finished	Feb 09 08:23:26 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604628546 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_div_intersig_mubi.2604628546
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/25.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/25.clkmgr_extclk.2408425134
Short name	T444
Test name
Test status
Simulation time	61858058 ps
CPU time	1.54 seconds
Started	Feb 09 08:23:13 AM UTC 25
Finished	Feb 09 08:23:16 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408425134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.2408425134
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/25.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/25.clkmgr_frequency.1389862060
Short name	T454
Test name
Test status
Simulation time	2406551087 ps
CPU time	10.94 seconds
Started	Feb 09 08:23:13 AM UTC 25
Finished	Feb 09 08:23:25 AM UTC 25
Peak memory	210832 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389862060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.1389862060
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/25.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/25.clkmgr_frequency_timeout.649979260
Short name	T446
Test name
Test status
Simulation time	145338573 ps
CPU time	2.17 seconds
Started	Feb 09 08:23:15 AM UTC 25
Finished	Feb 09 08:23:19 AM UTC 25
Peak memory	210272 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649979260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_timeout.649979260
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/25.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/25.clkmgr_idle_intersig_mubi.1217028440
Short name	T452
Test name
Test status
Simulation time	30858064 ps
CPU time	1.38 seconds
Started	Feb 09 08:23:20 AM UTC 25
Finished	Feb 09 08:23:22 AM UTC 25
Peak memory	209852 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217028440 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_idle_intersig_mubi.1217028440
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/25.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.110578446
Short name	T450
Test name
Test status
Simulation time	38897655 ps
CPU time	1.21 seconds
Started	Feb 09 08:23:20 AM UTC 25
Finished	Feb 09 08:23:22 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110578446 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_lc_clk_byp_req_intersig_mubi.110578446
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.688982074
Short name	T451
Test name
Test status
Simulation time	37727391 ps
CPU time	1.24 seconds
Started	Feb 09 08:23:20 AM UTC 25
Finished	Feb 09 08:23:22 AM UTC 25
Peak memory	210028 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688982074 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_lc_ctrl_intersig_mubi.688982074
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/25.clkmgr_peri.1641734978
Short name	T447
Test name
Test status
Simulation time	36543338 ps
CPU time	1.23 seconds
Started	Feb 09 08:23:16 AM UTC 25
Finished	Feb 09 08:23:19 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641734978 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.1641734978
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/25.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/25.clkmgr_regwen.1053175346
Short name	T456
Test name
Test status
Simulation time	96623961 ps
CPU time	1.87 seconds
Started	Feb 09 08:23:23 AM UTC 25
Finished	Feb 09 08:23:26 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053175346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.1053175346
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/25.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/25.clkmgr_smoke.3575976753
Short name	T166
Test name
Test status
Simulation time	18135535 ps
CPU time	1.2 seconds
Started	Feb 09 08:23:13 AM UTC 25
Finished	Feb 09 08:23:15 AM UTC 25
Peak memory	210324 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575976753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.3575976753
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/25.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/25.clkmgr_stress_all.904318286
Short name	T526
Test name
Test status
Simulation time	7559690272 ps
CPU time	93.81 seconds
Started	Feb 09 08:23:24 AM UTC 25
Finished	Feb 09 08:25:00 AM UTC 25
Peak memory	210608 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904318286 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all.904318286
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/25.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/25.clkmgr_stress_all_with_rand_reset.1178175454
Short name	T821
Test name
Test status
Simulation time	26174881651 ps
CPU time	463.6 seconds
Started	Feb 09 08:23:23 AM UTC 25
Finished	Feb 09 08:31:13 AM UTC 25
Peak memory	220424 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1178175454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25. clkmgr_stress_all_with_rand_reset.1178175454
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/25.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/25.clkmgr_trans.1545666413
Short name	T448
Test name
Test status
Simulation time	23383231 ps
CPU time	1.4 seconds
Started	Feb 09 08:23:16 AM UTC 25
Finished	Feb 09 08:23:19 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545666413 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.1545666413
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/25.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/26.clkmgr_alert_test.730058262
Short name	T470
Test name
Test status
Simulation time	95158389 ps
CPU time	1.47 seconds
Started	Feb 09 08:23:41 AM UTC 25
Finished	Feb 09 08:23:44 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730058262 -assert nopostproc +U VM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_alert_test.730058262
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/26.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.1445395880
Short name	T467
Test name
Test status
Simulation time	32508893 ps
CPU time	1.21 seconds
Started	Feb 09 08:23:38 AM UTC 25
Finished	Feb 09 08:23:40 AM UTC 25
Peak memory	209856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445395880 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_handshake_intersig_mubi.1445395880
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/26.clkmgr_clk_status.3670858836
Short name	T460
Test name
Test status
Simulation time	28117962 ps
CPU time	1.17 seconds
Started	Feb 09 08:23:31 AM UTC 25
Finished	Feb 09 08:23:34 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670858836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.3670858836
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/26.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/26.clkmgr_div_intersig_mubi.2758611729
Short name	T468
Test name
Test status
Simulation time	187400022 ps
CPU time	1.7 seconds
Started	Feb 09 08:23:38 AM UTC 25
Finished	Feb 09 08:23:41 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758611729 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_div_intersig_mubi.2758611729
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/26.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/26.clkmgr_extclk.1218892521
Short name	T458
Test name
Test status
Simulation time	45779127 ps
CPU time	1.22 seconds
Started	Feb 09 08:23:26 AM UTC 25
Finished	Feb 09 08:23:29 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218892521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.1218892521
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/26.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/26.clkmgr_frequency.1889479776
Short name	T473
Test name
Test status
Simulation time	1400455819 ps
CPU time	19.09 seconds
Started	Feb 09 08:23:28 AM UTC 25
Finished	Feb 09 08:23:48 AM UTC 25
Peak memory	210240 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889479776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.1889479776
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/26.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/26.clkmgr_frequency_timeout.1089054359
Short name	T479
Test name
Test status
Simulation time	2181052440 ps
CPU time	25.78 seconds
Started	Feb 09 08:23:28 AM UTC 25
Finished	Feb 09 08:23:55 AM UTC 25
Peak memory	210612 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089054359 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_timeout.1089054359
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/26.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/26.clkmgr_idle_intersig_mubi.676436257
Short name	T464
Test name
Test status
Simulation time	29751491 ps
CPU time	1.36 seconds
Started	Feb 09 08:23:35 AM UTC 25
Finished	Feb 09 08:23:37 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676436257 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_idle_intersig_mubi.676436257
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/26.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.506085826
Short name	T466
Test name
Test status
Simulation time	71222563 ps
CPU time	1.58 seconds
Started	Feb 09 08:23:36 AM UTC 25
Finished	Feb 09 08:23:38 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506085826 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_lc_clk_byp_req_intersig_mubi.506085826
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.2445710332
Short name	T465
Test name
Test status
Simulation time	54423805 ps
CPU time	1.49 seconds
Started	Feb 09 08:23:35 AM UTC 25
Finished	Feb 09 08:23:37 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445710332 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_lc_ctrl_intersig_mubi.2445710332
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/26.clkmgr_peri.217451948
Short name	T461
Test name
Test status
Simulation time	53543080 ps
CPU time	1.17 seconds
Started	Feb 09 08:23:31 AM UTC 25
Finished	Feb 09 08:23:34 AM UTC 25
Peak memory	208816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217451948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.217451948
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/26.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/26.clkmgr_regwen.1396073064
Short name	T469
Test name
Test status
Simulation time	429409333 ps
CPU time	4.19 seconds
Started	Feb 09 08:23:38 AM UTC 25
Finished	Feb 09 08:23:43 AM UTC 25
Peak memory	210184 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396073064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.1396073064
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/26.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/26.clkmgr_smoke.3788968053
Short name	T459
Test name
Test status
Simulation time	27414766 ps
CPU time	1.23 seconds
Started	Feb 09 08:23:26 AM UTC 25
Finished	Feb 09 08:23:29 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788968053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.3788968053
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/26.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/26.clkmgr_stress_all.2696910562
Short name	T475
Test name
Test status
Simulation time	1305982976 ps
CPU time	9.95 seconds
Started	Feb 09 08:23:41 AM UTC 25
Finished	Feb 09 08:23:52 AM UTC 25
Peak memory	210060 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696910562 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all.2696910562
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/26.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/26.clkmgr_stress_all_with_rand_reset.1634245243
Short name	T850
Test name
Test status
Simulation time	805310821168 ps
CPU time	4284.71 seconds
Started	Feb 09 08:23:39 AM UTC 25
Finished	Feb 09 09:35:49 AM UTC 25
Peak memory	230024 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1634245243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26. clkmgr_stress_all_with_rand_reset.1634245243
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/26.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/26.clkmgr_trans.3892408542
Short name	T462
Test name
Test status
Simulation time	39957061 ps
CPU time	1.74 seconds
Started	Feb 09 08:23:31 AM UTC 25
Finished	Feb 09 08:23:34 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892408542 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.3892408542
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/26.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/27.clkmgr_alert_test.2458455412
Short name	T487
Test name
Test status
Simulation time	33261703 ps
CPU time	1.22 seconds
Started	Feb 09 08:23:59 AM UTC 25
Finished	Feb 09 08:24:01 AM UTC 25
Peak memory	209856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458455412 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_alert_test.2458455412
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/27.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.1780081964
Short name	T483
Test name
Test status
Simulation time	76626559 ps
CPU time	1.47 seconds
Started	Feb 09 08:23:55 AM UTC 25
Finished	Feb 09 08:23:58 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780081964 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_handshake_intersig_mubi.1780081964
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/27.clkmgr_clk_status.659065065
Short name	T478
Test name
Test status
Simulation time	29511283 ps
CPU time	1.15 seconds
Started	Feb 09 08:23:52 AM UTC 25
Finished	Feb 09 08:23:54 AM UTC 25
Peak memory	209780 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659065065 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.659065065
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/27.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/27.clkmgr_div_intersig_mubi.2660071126
Short name	T482
Test name
Test status
Simulation time	40666233 ps
CPU time	1.4 seconds
Started	Feb 09 08:23:56 AM UTC 25
Finished	Feb 09 08:23:58 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660071126 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_div_intersig_mubi.2660071126
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/27.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/27.clkmgr_extclk.2678551747
Short name	T472
Test name
Test status
Simulation time	43895318 ps
CPU time	1.27 seconds
Started	Feb 09 08:23:44 AM UTC 25
Finished	Feb 09 08:23:47 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678551747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.2678551747
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/27.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/27.clkmgr_frequency.2004501713
Short name	T491
Test name
Test status
Simulation time	2386306672 ps
CPU time	17.07 seconds
Started	Feb 09 08:23:47 AM UTC 25
Finished	Feb 09 08:24:06 AM UTC 25
Peak memory	210684 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004501713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.2004501713
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/27.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/27.clkmgr_frequency_timeout.2444392179
Short name	T485
Test name
Test status
Simulation time	2234968256 ps
CPU time	12.06 seconds
Started	Feb 09 08:23:47 AM UTC 25
Finished	Feb 09 08:24:01 AM UTC 25
Peak memory	210548 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444392179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_timeout.2444392179
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/27.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/27.clkmgr_idle_intersig_mubi.328075519
Short name	T480
Test name
Test status
Simulation time	55244691 ps
CPU time	1.62 seconds
Started	Feb 09 08:23:53 AM UTC 25
Finished	Feb 09 08:23:56 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328075519 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_idle_intersig_mubi.328075519
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/27.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.213805566
Short name	T484
Test name
Test status
Simulation time	193649315 ps
CPU time	2.27 seconds
Started	Feb 09 08:23:55 AM UTC 25
Finished	Feb 09 08:23:59 AM UTC 25
Peak memory	210180 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213805566 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_lc_clk_byp_req_intersig_mubi.213805566
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.3642163973
Short name	T481
Test name
Test status
Simulation time	93035727 ps
CPU time	1.69 seconds
Started	Feb 09 08:23:53 AM UTC 25
Finished	Feb 09 08:23:56 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642163973 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_lc_ctrl_intersig_mubi.3642163973
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/27.clkmgr_peri.1539813208
Short name	T474
Test name
Test status
Simulation time	58170524 ps
CPU time	1.52 seconds
Started	Feb 09 08:23:48 AM UTC 25
Finished	Feb 09 08:23:51 AM UTC 25
Peak memory	210088 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539813208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.1539813208
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/27.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/27.clkmgr_regwen.533907153
Short name	T486
Test name
Test status
Simulation time	322710403 ps
CPU time	2.98 seconds
Started	Feb 09 08:23:57 AM UTC 25
Finished	Feb 09 08:24:01 AM UTC 25
Peak memory	210180 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533907153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.533907153
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/27.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/27.clkmgr_smoke.913038212
Short name	T471
Test name
Test status
Simulation time	17224122 ps
CPU time	1.16 seconds
Started	Feb 09 08:23:44 AM UTC 25
Finished	Feb 09 08:23:46 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913038212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.913038212
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/27.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/27.clkmgr_stress_all.1534805705
Short name	T514
Test name
Test status
Simulation time	6573066467 ps
CPU time	36.1 seconds
Started	Feb 09 08:23:59 AM UTC 25
Finished	Feb 09 08:24:36 AM UTC 25
Peak memory	210744 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534805705 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all.1534805705
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/27.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/27.clkmgr_stress_all_with_rand_reset.4242328636
Short name	T834
Test name
Test status
Simulation time	72070091639 ps
CPU time	787.49 seconds
Started	Feb 09 08:23:57 AM UTC 25
Finished	Feb 09 08:37:13 AM UTC 25
Peak memory	227212 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=4242328636 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27. clkmgr_stress_all_with_rand_reset.4242328636
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/27.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/27.clkmgr_trans.1491273780
Short name	T477
Test name
Test status
Simulation time	18173833 ps
CPU time	1.24 seconds
Started	Feb 09 08:23:52 AM UTC 25
Finished	Feb 09 08:23:54 AM UTC 25
Peak memory	209592 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491273780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.1491273780
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/27.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/28.clkmgr_alert_test.33225779
Short name	T500
Test name
Test status
Simulation time	37505432 ps
CPU time	1.38 seconds
Started	Feb 09 08:24:16 AM UTC 25
Finished	Feb 09 08:24:19 AM UTC 25
Peak memory	208948 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33225779 -assert nopostproc +UV M_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_alert_test.33225779
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/28.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.2415172832
Short name	T497
Test name
Test status
Simulation time	186490452 ps
CPU time	2.3 seconds
Started	Feb 09 08:24:10 AM UTC 25
Finished	Feb 09 08:24:13 AM UTC 25
Peak memory	210188 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415172832 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_handshake_intersig_mubi.2415172832
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/28.clkmgr_clk_status.3859567618
Short name	T493
Test name
Test status
Simulation time	38075679 ps
CPU time	1.23 seconds
Started	Feb 09 08:24:06 AM UTC 25
Finished	Feb 09 08:24:09 AM UTC 25
Peak memory	208784 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859567618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.3859567618
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/28.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/28.clkmgr_div_intersig_mubi.2519063151
Short name	T499
Test name
Test status
Simulation time	24870047 ps
CPU time	1.18 seconds
Started	Feb 09 08:24:13 AM UTC 25
Finished	Feb 09 08:24:15 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519063151 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_div_intersig_mubi.2519063151
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/28.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/28.clkmgr_extclk.1275563177
Short name	T489
Test name
Test status
Simulation time	15551953 ps
CPU time	1.11 seconds
Started	Feb 09 08:24:02 AM UTC 25
Finished	Feb 09 08:24:04 AM UTC 25
Peak memory	209856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275563177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.1275563177
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/28.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/28.clkmgr_frequency.1322764167
Short name	T505
Test name
Test status
Simulation time	2130153299 ps
CPU time	22.36 seconds
Started	Feb 09 08:24:02 AM UTC 25
Finished	Feb 09 08:24:26 AM UTC 25
Peak memory	210580 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322764167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.1322764167
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/28.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/28.clkmgr_frequency_timeout.1232080837
Short name	T498
Test name
Test status
Simulation time	978772985 ps
CPU time	10.04 seconds
Started	Feb 09 08:24:02 AM UTC 25
Finished	Feb 09 08:24:13 AM UTC 25
Peak memory	210272 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232080837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_timeout.1232080837
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/28.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/28.clkmgr_idle_intersig_mubi.1112554325
Short name	T494
Test name
Test status
Simulation time	72598592 ps
CPU time	1.67 seconds
Started	Feb 09 08:24:06 AM UTC 25
Finished	Feb 09 08:24:09 AM UTC 25
Peak memory	209940 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112554325 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_idle_intersig_mubi.1112554325
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/28.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.1392256769
Short name	T496
Test name
Test status
Simulation time	60408160 ps
CPU time	1.49 seconds
Started	Feb 09 08:24:10 AM UTC 25
Finished	Feb 09 08:24:12 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392256769 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_lc_clk_byp_req_intersig_mubi.1392256769
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.797738073
Short name	T495
Test name
Test status
Simulation time	95506989 ps
CPU time	1.88 seconds
Started	Feb 09 08:24:09 AM UTC 25
Finished	Feb 09 08:24:12 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797738073 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_lc_ctrl_intersig_mubi.797738073
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/28.clkmgr_peri.2128498684
Short name	T490
Test name
Test status
Simulation time	15137640 ps
CPU time	1.12 seconds
Started	Feb 09 08:24:03 AM UTC 25
Finished	Feb 09 08:24:05 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128498684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.2128498684
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/28.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/28.clkmgr_regwen.3337450073
Short name	T501
Test name
Test status
Simulation time	1271416517 ps
CPU time	6.36 seconds
Started	Feb 09 08:24:13 AM UTC 25
Finished	Feb 09 08:24:20 AM UTC 25
Peak memory	210520 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337450073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.3337450073
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/28.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/28.clkmgr_smoke.1243706669
Short name	T488
Test name
Test status
Simulation time	49945651 ps
CPU time	1.3 seconds
Started	Feb 09 08:24:00 AM UTC 25
Finished	Feb 09 08:24:02 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243706669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.1243706669
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/28.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/28.clkmgr_stress_all.2745154191
Short name	T504
Test name
Test status
Simulation time	1057993317 ps
CPU time	8.96 seconds
Started	Feb 09 08:24:14 AM UTC 25
Finished	Feb 09 08:24:24 AM UTC 25
Peak memory	210800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745154191 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all.2745154191
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/28.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/28.clkmgr_stress_all_with_rand_reset.2341133814
Short name	T838
Test name
Test status
Simulation time	92761541779 ps
CPU time	918.62 seconds
Started	Feb 09 08:24:14 AM UTC 25
Finished	Feb 09 08:39:43 AM UTC 25
Peak memory	224304 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2341133814 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28. clkmgr_stress_all_with_rand_reset.2341133814
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/28.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/28.clkmgr_trans.135491055
Short name	T492
Test name
Test status
Simulation time	56435114 ps
CPU time	1.42 seconds
Started	Feb 09 08:24:05 AM UTC 25
Finished	Feb 09 08:24:08 AM UTC 25
Peak memory	209852 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135491055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.135491055
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/28.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/29.clkmgr_alert_test.1497226250
Short name	T517
Test name
Test status
Simulation time	18914306 ps
CPU time	1.16 seconds
Started	Feb 09 08:24:46 AM UTC 25
Finished	Feb 09 08:24:48 AM UTC 25
Peak memory	209916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497226250 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_alert_test.1497226250
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/29.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.2090492660
Short name	T515
Test name
Test status
Simulation time	49452682 ps
CPU time	1.3 seconds
Started	Feb 09 08:24:44 AM UTC 25
Finished	Feb 09 08:24:47 AM UTC 25
Peak memory	210036 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090492660 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_handshake_intersig_mubi.2090492660
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/29.clkmgr_clk_status.3290236384
Short name	T508
Test name
Test status
Simulation time	34345915 ps
CPU time	1.21 seconds
Started	Feb 09 08:24:27 AM UTC 25
Finished	Feb 09 08:24:29 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290236384 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.3290236384
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/29.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/29.clkmgr_div_intersig_mubi.2490337983
Short name	T516
Test name
Test status
Simulation time	28539641 ps
CPU time	1.53 seconds
Started	Feb 09 08:24:44 AM UTC 25
Finished	Feb 09 08:24:47 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490337983 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_div_intersig_mubi.2490337983
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/29.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/29.clkmgr_extclk.1122601045
Short name	T503
Test name
Test status
Simulation time	49031918 ps
CPU time	1.36 seconds
Started	Feb 09 08:24:21 AM UTC 25
Finished	Feb 09 08:24:24 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122601045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.1122601045
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/29.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/29.clkmgr_frequency.2614512276
Short name	T506
Test name
Test status
Simulation time	223411671 ps
CPU time	2.62 seconds
Started	Feb 09 08:24:22 AM UTC 25
Finished	Feb 09 08:24:26 AM UTC 25
Peak memory	210244 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614512276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.2614512276
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/29.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/29.clkmgr_frequency_timeout.2733632758
Short name	T511
Test name
Test status
Simulation time	1506018529 ps
CPU time	6.99 seconds
Started	Feb 09 08:24:24 AM UTC 25
Finished	Feb 09 08:24:33 AM UTC 25
Peak memory	210264 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733632758 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_timeout.2733632758
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/29.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/29.clkmgr_idle_intersig_mubi.213766189
Short name	T510
Test name
Test status
Simulation time	28419427 ps
CPU time	1.53 seconds
Started	Feb 09 08:24:29 AM UTC 25
Finished	Feb 09 08:24:32 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213766189 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_idle_intersig_mubi.213766189
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/29.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.2664562742
Short name	T512
Test name
Test status
Simulation time	19670997 ps
CPU time	1.03 seconds
Started	Feb 09 08:24:31 AM UTC 25
Finished	Feb 09 08:24:33 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664562742 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_lc_clk_byp_req_intersig_mubi.2664562742
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.384242759
Short name	T513
Test name
Test status
Simulation time	180246460 ps
CPU time	2.11 seconds
Started	Feb 09 08:24:30 AM UTC 25
Finished	Feb 09 08:24:33 AM UTC 25
Peak memory	210184 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384242759 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_lc_ctrl_intersig_mubi.384242759
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/29.clkmgr_peri.3147375087
Short name	T507
Test name
Test status
Simulation time	39451112 ps
CPU time	1.25 seconds
Started	Feb 09 08:24:25 AM UTC 25
Finished	Feb 09 08:24:28 AM UTC 25
Peak memory	210088 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147375087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.3147375087
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/29.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/29.clkmgr_regwen.860115974
Short name	T521
Test name
Test status
Simulation time	848522157 ps
CPU time	7.54 seconds
Started	Feb 09 08:24:46 AM UTC 25
Finished	Feb 09 08:24:54 AM UTC 25
Peak memory	210404 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860115974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.860115974
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/29.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/29.clkmgr_smoke.1837489012
Short name	T502
Test name
Test status
Simulation time	17557571 ps
CPU time	1.12 seconds
Started	Feb 09 08:24:19 AM UTC 25
Finished	Feb 09 08:24:21 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837489012 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.1837489012
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/29.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/29.clkmgr_stress_all.3931830090
Short name	T522
Test name
Test status
Simulation time	813206523 ps
CPU time	8.05 seconds
Started	Feb 09 08:24:46 AM UTC 25
Finished	Feb 09 08:24:55 AM UTC 25
Peak memory	210244 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931830090 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all.3931830090
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/29.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/29.clkmgr_stress_all_with_rand_reset.3977375582
Short name	T830
Test name
Test status
Simulation time	31508598241 ps
CPU time	579.11 seconds
Started	Feb 09 08:24:46 AM UTC 25
Finished	Feb 09 08:34:32 AM UTC 25
Peak memory	220328 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3977375582 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29. clkmgr_stress_all_with_rand_reset.3977375582
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/29.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/29.clkmgr_trans.1626510144
Short name	T509
Test name
Test status
Simulation time	98170437 ps
CPU time	1.76 seconds
Started	Feb 09 08:24:27 AM UTC 25
Finished	Feb 09 08:24:29 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626510144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.1626510144
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/29.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_alert_test.2687611169
Short name	T205
Test name
Test status
Simulation time	47907397 ps
CPU time	1.17 seconds
Started	Feb 09 08:16:49 AM UTC 25
Finished	Feb 09 08:16:51 AM UTC 25
Peak memory	209792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687611169 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_alert_test.2687611169
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.1586662536
Short name	T48
Test name
Test status
Simulation time	34788241 ps
CPU time	1.12 seconds
Started	Feb 09 08:16:45 AM UTC 25
Finished	Feb 09 08:16:47 AM UTC 25
Peak memory	210036 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586662536 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_handshake_intersig_mubi.1586662536
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_clk_status.118517668
Short name	T44
Test name
Test status
Simulation time	126800349 ps
CPU time	1.56 seconds
Started	Feb 09 08:16:42 AM UTC 25
Finished	Feb 09 08:16:45 AM UTC 25
Peak memory	208824 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118517668 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.118517668
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_div_intersig_mubi.139831087
Short name	T49
Test name
Test status
Simulation time	19728038 ps
CPU time	1.22 seconds
Started	Feb 09 08:16:46 AM UTC 25
Finished	Feb 09 08:16:48 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139831087 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_div_intersig_mubi.139831087
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_extclk.1611400248
Short name	T203
Test name
Test status
Simulation time	18829279 ps
CPU time	1.15 seconds
Started	Feb 09 08:16:36 AM UTC 25
Finished	Feb 09 08:16:38 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611400248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.1611400248
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_frequency.709504067
Short name	T39
Test name
Test status
Simulation time	236249148 ps
CPU time	3.09 seconds
Started	Feb 09 08:16:38 AM UTC 25
Finished	Feb 09 08:16:42 AM UTC 25
Peak memory	210244 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709504067 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.709504067
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_frequency_timeout.3085459389
Short name	T137
Test name
Test status
Simulation time	2422489144 ps
CPU time	36.52 seconds
Started	Feb 09 08:16:38 AM UTC 25
Finished	Feb 09 08:17:16 AM UTC 25
Peak memory	210600 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085459389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_timeout.3085459389
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_idle_intersig_mubi.1959155684
Short name	T47
Test name
Test status
Simulation time	65559739 ps
CPU time	1.41 seconds
Started	Feb 09 08:16:43 AM UTC 25
Finished	Feb 09 08:16:46 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959155684 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_idle_intersig_mubi.1959155684
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.152468096
Short name	T46
Test name
Test status
Simulation time	33304733 ps
CPU time	1.12 seconds
Started	Feb 09 08:16:44 AM UTC 25
Finished	Feb 09 08:16:46 AM UTC 25
Peak memory	210036 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152468096 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_lc_clk_byp_req_intersig_mubi.152468096
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.1014210168
Short name	T45
Test name
Test status
Simulation time	12922990 ps
CPU time	1.06 seconds
Started	Feb 09 08:16:43 AM UTC 25
Finished	Feb 09 08:16:46 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014210168 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_lc_ctrl_intersig_mubi.1014210168
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_peri.1205662841
Short name	T198
Test name
Test status
Simulation time	50253289 ps
CPU time	1.39 seconds
Started	Feb 09 08:16:39 AM UTC 25
Finished	Feb 09 08:16:42 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205662841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.1205662841
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_regwen.418768081
Short name	T167
Test name
Test status
Simulation time	459470135 ps
CPU time	4.96 seconds
Started	Feb 09 08:16:47 AM UTC 25
Finished	Feb 09 08:16:53 AM UTC 25
Peak memory	210440 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418768081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.418768081
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_sec_cm.1312245438
Short name	T77
Test name
Test status
Simulation time	221451964 ps
CPU time	3.21 seconds
Started	Feb 09 08:16:47 AM UTC 25
Finished	Feb 09 08:16:51 AM UTC 25
Peak memory	242404 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312245438 -assert nopostproc +U VM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_sec_cm.1312245438
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_smoke.783202949
Short name	T65
Test name
Test status
Simulation time	20834732 ps
CPU time	1.18 seconds
Started	Feb 09 08:16:35 AM UTC 25
Finished	Feb 09 08:16:37 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783202949 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.783202949
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_stress_all.1031676430
Short name	T14
Test name
Test status
Simulation time	6345457738 ps
CPU time	35.81 seconds
Started	Feb 09 08:16:48 AM UTC 25
Finished	Feb 09 08:17:25 AM UTC 25
Peak memory	210652 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031676430 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all.1031676430
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_stress_all_with_rand_reset.396029631
Short name	T73
Test name
Test status
Simulation time	20602774862 ps
CPU time	192.53 seconds
Started	Feb 09 08:16:47 AM UTC 25
Finished	Feb 09 08:20:02 AM UTC 25
Peak memory	220232 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=396029631 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.cl kmgr_stress_all_with_rand_reset.396029631
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/3.clkmgr_trans.1746342481
Short name	T43
Test name
Test status
Simulation time	151989196 ps
CPU time	2.49 seconds
Started	Feb 09 08:16:39 AM UTC 25
Finished	Feb 09 08:16:43 AM UTC 25
Peak memory	210176 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746342481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.1746342481
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/3.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/30.clkmgr_alert_test.538740183
Short name	T533
Test name
Test status
Simulation time	16993421 ps
CPU time	1.26 seconds
Started	Feb 09 08:25:05 AM UTC 25
Finished	Feb 09 08:25:07 AM UTC 25
Peak memory	209852 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538740183 -assert nopostproc +U VM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_alert_test.538740183
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/30.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.999224047
Short name	T529
Test name
Test status
Simulation time	25472229 ps
CPU time	1.39 seconds
Started	Feb 09 08:25:01 AM UTC 25
Finished	Feb 09 08:25:03 AM UTC 25
Peak memory	209852 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999224047 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_handshake_intersig_mubi.999224047
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/30.clkmgr_clk_status.2584205196
Short name	T523
Test name
Test status
Simulation time	41532776 ps
CPU time	1.24 seconds
Started	Feb 09 08:24:55 AM UTC 25
Finished	Feb 09 08:24:58 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584205196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.2584205196
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/30.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/30.clkmgr_div_intersig_mubi.2739199893
Short name	T530
Test name
Test status
Simulation time	91434388 ps
CPU time	1.67 seconds
Started	Feb 09 08:25:02 AM UTC 25
Finished	Feb 09 08:25:05 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739199893 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_div_intersig_mubi.2739199893
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/30.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/30.clkmgr_extclk.1101382699
Short name	T518
Test name
Test status
Simulation time	15355378 ps
CPU time	1.17 seconds
Started	Feb 09 08:24:48 AM UTC 25
Finished	Feb 09 08:24:50 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101382699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.1101382699
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/30.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/30.clkmgr_frequency.625492279
Short name	T532
Test name
Test status
Simulation time	2007946606 ps
CPU time	16.47 seconds
Started	Feb 09 08:24:49 AM UTC 25
Finished	Feb 09 08:25:07 AM UTC 25
Peak memory	210556 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625492279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.625492279
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/30.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/30.clkmgr_frequency_timeout.1489339392
Short name	T536
Test name
Test status
Simulation time	1457944773 ps
CPU time	17.58 seconds
Started	Feb 09 08:24:51 AM UTC 25
Finished	Feb 09 08:25:10 AM UTC 25
Peak memory	210272 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489339392 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_timeout.1489339392
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/30.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/30.clkmgr_idle_intersig_mubi.3231342562
Short name	T525
Test name
Test status
Simulation time	331269713 ps
CPU time	3.01 seconds
Started	Feb 09 08:24:55 AM UTC 25
Finished	Feb 09 08:25:00 AM UTC 25
Peak memory	210184 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231342562 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_idle_intersig_mubi.3231342562
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/30.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.1718211249
Short name	T527
Test name
Test status
Simulation time	16855396 ps
CPU time	1.25 seconds
Started	Feb 09 08:24:58 AM UTC 25
Finished	Feb 09 08:25:01 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718211249 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_lc_clk_byp_req_intersig_mubi.1718211249
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.1050626528
Short name	T528
Test name
Test status
Simulation time	67026593 ps
CPU time	1.43 seconds
Started	Feb 09 08:24:58 AM UTC 25
Finished	Feb 09 08:25:01 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050626528 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_lc_ctrl_intersig_mubi.1050626528
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/30.clkmgr_peri.109682122
Short name	T520
Test name
Test status
Simulation time	43025067 ps
CPU time	1.28 seconds
Started	Feb 09 08:24:51 AM UTC 25
Finished	Feb 09 08:24:53 AM UTC 25
Peak memory	210084 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109682122 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.109682122
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/30.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/30.clkmgr_regwen.2546957546
Short name	T531
Test name
Test status
Simulation time	201540681 ps
CPU time	2.24 seconds
Started	Feb 09 08:25:02 AM UTC 25
Finished	Feb 09 08:25:05 AM UTC 25
Peak memory	210180 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546957546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.2546957546
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/30.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/30.clkmgr_smoke.3678002167
Short name	T519
Test name
Test status
Simulation time	43496160 ps
CPU time	1.29 seconds
Started	Feb 09 08:24:48 AM UTC 25
Finished	Feb 09 08:24:50 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678002167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.3678002167
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/30.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/30.clkmgr_stress_all.1092641825
Short name	T534
Test name
Test status
Simulation time	296766077 ps
CPU time	3.12 seconds
Started	Feb 09 08:25:04 AM UTC 25
Finished	Feb 09 08:25:08 AM UTC 25
Peak memory	210400 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092641825 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all.1092641825
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/30.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/30.clkmgr_stress_all_with_rand_reset.2378897643
Short name	T832
Test name
Test status
Simulation time	83250991407 ps
CPU time	648.48 seconds
Started	Feb 09 08:25:02 AM UTC 25
Finished	Feb 09 08:35:58 AM UTC 25
Peak memory	227180 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2378897643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30. clkmgr_stress_all_with_rand_reset.2378897643
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/30.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/30.clkmgr_trans.333911467
Short name	T524
Test name
Test status
Simulation time	218970573 ps
CPU time	2.43 seconds
Started	Feb 09 08:24:54 AM UTC 25
Finished	Feb 09 08:24:58 AM UTC 25
Peak memory	210180 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333911467 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.333911467
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/30.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/31.clkmgr_alert_test.2385523710
Short name	T546
Test name
Test status
Simulation time	22600301 ps
CPU time	1.29 seconds
Started	Feb 09 08:25:20 AM UTC 25
Finished	Feb 09 08:25:22 AM UTC 25
Peak memory	209916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385523710 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_alert_test.2385523710
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/31.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.283212602
Short name	T544
Test name
Test status
Simulation time	27973875 ps
CPU time	1.45 seconds
Started	Feb 09 08:25:16 AM UTC 25
Finished	Feb 09 08:25:18 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283212602 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_handshake_intersig_mubi.283212602
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/31.clkmgr_clk_status.320274309
Short name	T538
Test name
Test status
Simulation time	24070176 ps
CPU time	1.18 seconds
Started	Feb 09 08:25:11 AM UTC 25
Finished	Feb 09 08:25:14 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320274309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.320274309
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/31.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/31.clkmgr_div_intersig_mubi.30761924
Short name	T545
Test name
Test status
Simulation time	45382078 ps
CPU time	1.54 seconds
Started	Feb 09 08:25:18 AM UTC 25
Finished	Feb 09 08:25:21 AM UTC 25
Peak memory	209992 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30761924 -assert nopostpr oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_div_intersig_mubi.30761924
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/31.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/31.clkmgr_extclk.2155184816
Short name	T539
Test name
Test status
Simulation time	40323207 ps
CPU time	1.27 seconds
Started	Feb 09 08:25:11 AM UTC 25
Finished	Feb 09 08:25:14 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155184816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.2155184816
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/31.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/31.clkmgr_frequency.178608125
Short name	T552
Test name
Test status
Simulation time	1396237964 ps
CPU time	18.82 seconds
Started	Feb 09 08:25:11 AM UTC 25
Finished	Feb 09 08:25:32 AM UTC 25
Peak memory	210248 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178608125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.178608125
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/31.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/31.clkmgr_frequency_timeout.2098516410
Short name	T562
Test name
Test status
Simulation time	2180472288 ps
CPU time	30.13 seconds
Started	Feb 09 08:25:11 AM UTC 25
Finished	Feb 09 08:25:43 AM UTC 25
Peak memory	210608 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098516410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_timeout.2098516410
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/31.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/31.clkmgr_idle_intersig_mubi.269967557
Short name	T543
Test name
Test status
Simulation time	77931831 ps
CPU time	1.43 seconds
Started	Feb 09 08:25:15 AM UTC 25
Finished	Feb 09 08:25:17 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269967557 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_idle_intersig_mubi.269967557
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/31.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.1242809903
Short name	T542
Test name
Test status
Simulation time	25663331 ps
CPU time	1.36 seconds
Started	Feb 09 08:25:15 AM UTC 25
Finished	Feb 09 08:25:17 AM UTC 25
Peak memory	209084 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242809903 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_lc_clk_byp_req_intersig_mubi.1242809903
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.3579691553
Short name	T541
Test name
Test status
Simulation time	29058961 ps
CPU time	1.22 seconds
Started	Feb 09 08:25:15 AM UTC 25
Finished	Feb 09 08:25:17 AM UTC 25
Peak memory	208948 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579691553 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_lc_ctrl_intersig_mubi.3579691553
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/31.clkmgr_peri.1417322976
Short name	T537
Test name
Test status
Simulation time	22989506 ps
CPU time	1.16 seconds
Started	Feb 09 08:25:11 AM UTC 25
Finished	Feb 09 08:25:14 AM UTC 25
Peak memory	210088 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417322976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.1417322976
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/31.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/31.clkmgr_regwen.8883950
Short name	T547
Test name
Test status
Simulation time	203419042 ps
CPU time	3.2 seconds
Started	Feb 09 08:25:19 AM UTC 25
Finished	Feb 09 08:25:23 AM UTC 25
Peak memory	210312 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8883950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.8883950
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/31.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/31.clkmgr_smoke.932459282
Short name	T535
Test name
Test status
Simulation time	16491936 ps
CPU time	1.16 seconds
Started	Feb 09 08:25:06 AM UTC 25
Finished	Feb 09 08:25:08 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932459282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.932459282
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/31.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/31.clkmgr_stress_all.534110699
Short name	T625
Test name
Test status
Simulation time	9696543362 ps
CPU time	100.98 seconds
Started	Feb 09 08:25:19 AM UTC 25
Finished	Feb 09 08:27:02 AM UTC 25
Peak memory	210616 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534110699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all.534110699
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/31.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/31.clkmgr_stress_all_with_rand_reset.2047402077
Short name	T849
Test name
Test status
Simulation time	368782660203 ps
CPU time	1913.94 seconds
Started	Feb 09 08:25:19 AM UTC 25
Finished	Feb 09 08:57:33 AM UTC 25
Peak memory	227216 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2047402077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31. clkmgr_stress_all_with_rand_reset.2047402077
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/31.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/31.clkmgr_trans.3736302027
Short name	T540
Test name
Test status
Simulation time	90787067 ps
CPU time	1.81 seconds
Started	Feb 09 08:25:11 AM UTC 25
Finished	Feb 09 08:25:14 AM UTC 25
Peak memory	209888 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736302027 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.3736302027
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/31.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/32.clkmgr_alert_test.1906408140
Short name	T560
Test name
Test status
Simulation time	25679153 ps
CPU time	1.11 seconds
Started	Feb 09 08:25:39 AM UTC 25
Finished	Feb 09 08:25:42 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906408140 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_alert_test.1906408140
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/32.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.3892094394
Short name	T557
Test name
Test status
Simulation time	17441979 ps
CPU time	1.19 seconds
Started	Feb 09 08:25:35 AM UTC 25
Finished	Feb 09 08:25:37 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892094394 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_handshake_intersig_mubi.3892094394
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/32.clkmgr_clk_status.3195710412
Short name	T553
Test name
Test status
Simulation time	30690700 ps
CPU time	1.11 seconds
Started	Feb 09 08:25:32 AM UTC 25
Finished	Feb 09 08:25:34 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195710412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.3195710412
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/32.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/32.clkmgr_div_intersig_mubi.2184341371
Short name	T559
Test name
Test status
Simulation time	28690458 ps
CPU time	1.41 seconds
Started	Feb 09 08:25:36 AM UTC 25
Finished	Feb 09 08:25:38 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184341371 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_div_intersig_mubi.2184341371
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/32.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/32.clkmgr_extclk.1224790991
Short name	T549
Test name
Test status
Simulation time	21695750 ps
CPU time	1.24 seconds
Started	Feb 09 08:25:25 AM UTC 25
Finished	Feb 09 08:25:28 AM UTC 25
Peak memory	209784 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224790991 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.1224790991
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/32.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/32.clkmgr_frequency.1228446710
Short name	T564
Test name
Test status
Simulation time	1996618143 ps
CPU time	18.08 seconds
Started	Feb 09 08:25:25 AM UTC 25
Finished	Feb 09 08:25:45 AM UTC 25
Peak memory	210444 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228446710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.1228446710
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/32.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/32.clkmgr_frequency_timeout.1244164583
Short name	T555
Test name
Test status
Simulation time	991142839 ps
CPU time	8.44 seconds
Started	Feb 09 08:25:25 AM UTC 25
Finished	Feb 09 08:25:35 AM UTC 25
Peak memory	210272 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244164583 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_timeout.1244164583
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/32.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/32.clkmgr_idle_intersig_mubi.1549243145
Short name	T554
Test name
Test status
Simulation time	15315716 ps
CPU time	1.2 seconds
Started	Feb 09 08:25:32 AM UTC 25
Finished	Feb 09 08:25:34 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549243145 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_idle_intersig_mubi.1549243145
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/32.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.343134170
Short name	T558
Test name
Test status
Simulation time	22776861 ps
CPU time	1.2 seconds
Started	Feb 09 08:25:35 AM UTC 25
Finished	Feb 09 08:25:37 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343134170 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_lc_clk_byp_req_intersig_mubi.343134170
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.2117616777
Short name	T556
Test name
Test status
Simulation time	94902291 ps
CPU time	1.86 seconds
Started	Feb 09 08:25:33 AM UTC 25
Finished	Feb 09 08:25:36 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117616777 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_lc_ctrl_intersig_mubi.2117616777
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/32.clkmgr_peri.1306576477
Short name	T550
Test name
Test status
Simulation time	15219199 ps
CPU time	1.15 seconds
Started	Feb 09 08:25:28 AM UTC 25
Finished	Feb 09 08:25:31 AM UTC 25
Peak memory	210088 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306576477 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.1306576477
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/32.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/32.clkmgr_regwen.1064045682
Short name	T563
Test name
Test status
Simulation time	414835680 ps
CPU time	4.92 seconds
Started	Feb 09 08:25:37 AM UTC 25
Finished	Feb 09 08:25:43 AM UTC 25
Peak memory	210184 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064045682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.1064045682
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/32.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/32.clkmgr_smoke.2663218763
Short name	T548
Test name
Test status
Simulation time	15267599 ps
CPU time	1.14 seconds
Started	Feb 09 08:25:25 AM UTC 25
Finished	Feb 09 08:25:27 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663218763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.2663218763
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/32.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/32.clkmgr_stress_all.555261315
Short name	T575
Test name
Test status
Simulation time	2498055600 ps
CPU time	21.32 seconds
Started	Feb 09 08:25:38 AM UTC 25
Finished	Feb 09 08:26:01 AM UTC 25
Peak memory	210836 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555261315 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all.555261315
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/32.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/32.clkmgr_stress_all_with_rand_reset.2862412781
Short name	T833
Test name
Test status
Simulation time	29883784966 ps
CPU time	653.59 seconds
Started	Feb 09 08:25:38 AM UTC 25
Finished	Feb 09 08:36:40 AM UTC 25
Peak memory	227180 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2862412781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32. clkmgr_stress_all_with_rand_reset.2862412781
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/32.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/32.clkmgr_trans.2130770860
Short name	T551
Test name
Test status
Simulation time	30680734 ps
CPU time	1.37 seconds
Started	Feb 09 08:25:28 AM UTC 25
Finished	Feb 09 08:25:31 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130770860 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.2130770860
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/32.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/33.clkmgr_alert_test.2002411417
Short name	T578
Test name
Test status
Simulation time	21078848 ps
CPU time	1.16 seconds
Started	Feb 09 08:26:13 AM UTC 25
Finished	Feb 09 08:26:16 AM UTC 25
Peak memory	209980 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002411417 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_alert_test.2002411417
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/33.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.605461031
Short name	T571
Test name
Test status
Simulation time	50932170 ps
CPU time	1.39 seconds
Started	Feb 09 08:25:50 AM UTC 25
Finished	Feb 09 08:25:53 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605461031 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_handshake_intersig_mubi.605461031
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/33.clkmgr_clk_status.2084319015
Short name	T567
Test name
Test status
Simulation time	13389618 ps
CPU time	1.06 seconds
Started	Feb 09 08:25:46 AM UTC 25
Finished	Feb 09 08:25:48 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084319015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.2084319015
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/33.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/33.clkmgr_div_intersig_mubi.2380017657
Short name	T574
Test name
Test status
Simulation time	32329252 ps
CPU time	1.18 seconds
Started	Feb 09 08:25:53 AM UTC 25
Finished	Feb 09 08:25:56 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380017657 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_div_intersig_mubi.2380017657
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/33.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/33.clkmgr_extclk.879263896
Short name	T565
Test name
Test status
Simulation time	37324939 ps
CPU time	1.37 seconds
Started	Feb 09 08:25:42 AM UTC 25
Finished	Feb 09 08:25:45 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879263896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.879263896
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/33.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/33.clkmgr_frequency.2568449763
Short name	T573
Test name
Test status
Simulation time	2020011117 ps
CPU time	9.38 seconds
Started	Feb 09 08:25:44 AM UTC 25
Finished	Feb 09 08:25:54 AM UTC 25
Peak memory	210556 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568449763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.2568449763
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/33.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/33.clkmgr_frequency_timeout.2997736554
Short name	T577
Test name
Test status
Simulation time	1939997007 ps
CPU time	22.25 seconds
Started	Feb 09 08:25:44 AM UTC 25
Finished	Feb 09 08:26:07 AM UTC 25
Peak memory	210272 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997736554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_timeout.2997736554
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/33.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/33.clkmgr_idle_intersig_mubi.1650831259
Short name	T569
Test name
Test status
Simulation time	31795318 ps
CPU time	1.33 seconds
Started	Feb 09 08:25:47 AM UTC 25
Finished	Feb 09 08:25:49 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650831259 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_idle_intersig_mubi.1650831259
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/33.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.1881714627
Short name	T572
Test name
Test status
Simulation time	61356000 ps
CPU time	1.56 seconds
Started	Feb 09 08:25:50 AM UTC 25
Finished	Feb 09 08:25:53 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881714627 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_lc_clk_byp_req_intersig_mubi.1881714627
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.3793311523
Short name	T570
Test name
Test status
Simulation time	85421565 ps
CPU time	1.7 seconds
Started	Feb 09 08:25:49 AM UTC 25
Finished	Feb 09 08:25:52 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793311523 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_lc_ctrl_intersig_mubi.3793311523
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/33.clkmgr_peri.2960899752
Short name	T566
Test name
Test status
Simulation time	68131631 ps
CPU time	1.48 seconds
Started	Feb 09 08:25:44 AM UTC 25
Finished	Feb 09 08:25:46 AM UTC 25
Peak memory	210088 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960899752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.2960899752
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/33.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/33.clkmgr_regwen.1091511494
Short name	T576
Test name
Test status
Simulation time	1006981677 ps
CPU time	7.47 seconds
Started	Feb 09 08:25:54 AM UTC 25
Finished	Feb 09 08:26:03 AM UTC 25
Peak memory	210640 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091511494 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.1091511494
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/33.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/33.clkmgr_smoke.1087200059
Short name	T561
Test name
Test status
Simulation time	14473191 ps
CPU time	1.22 seconds
Started	Feb 09 08:25:40 AM UTC 25
Finished	Feb 09 08:25:43 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087200059 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.1087200059
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/33.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/33.clkmgr_stress_all.1771285778
Short name	T589
Test name
Test status
Simulation time	3841411034 ps
CPU time	24.92 seconds
Started	Feb 09 08:25:55 AM UTC 25
Finished	Feb 09 08:26:22 AM UTC 25
Peak memory	210932 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771285778 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all.1771285778
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/33.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/33.clkmgr_stress_all_with_rand_reset.2765550048
Short name	T824
Test name
Test status
Simulation time	17713020826 ps
CPU time	342.12 seconds
Started	Feb 09 08:25:54 AM UTC 25
Finished	Feb 09 08:31:41 AM UTC 25
Peak memory	227396 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2765550048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33. clkmgr_stress_all_with_rand_reset.2765550048
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/33.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/33.clkmgr_trans.1295880836
Short name	T568
Test name
Test status
Simulation time	69522095 ps
CPU time	1.47 seconds
Started	Feb 09 08:25:46 AM UTC 25
Finished	Feb 09 08:25:49 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295880836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.1295880836
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/33.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/34.clkmgr_alert_test.2152824945
Short name	T592
Test name
Test status
Simulation time	26330437 ps
CPU time	1.16 seconds
Started	Feb 09 08:26:22 AM UTC 25
Finished	Feb 09 08:26:25 AM UTC 25
Peak memory	209916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152824945 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_alert_test.2152824945
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/34.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.2329662640
Short name	T588
Test name
Test status
Simulation time	30335183 ps
CPU time	1.34 seconds
Started	Feb 09 08:26:19 AM UTC 25
Finished	Feb 09 08:26:21 AM UTC 25
Peak memory	209856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329662640 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_handshake_intersig_mubi.2329662640
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/34.clkmgr_clk_status.1873626057
Short name	T583
Test name
Test status
Simulation time	13930012 ps
CPU time	1.07 seconds
Started	Feb 09 08:26:17 AM UTC 25
Finished	Feb 09 08:26:19 AM UTC 25
Peak memory	209956 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873626057 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.1873626057
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/34.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/34.clkmgr_div_intersig_mubi.1628991713
Short name	T590
Test name
Test status
Simulation time	49897871 ps
CPU time	1.4 seconds
Started	Feb 09 08:26:20 AM UTC 25
Finished	Feb 09 08:26:23 AM UTC 25
Peak memory	209772 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628991713 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_div_intersig_mubi.1628991713
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/34.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/34.clkmgr_extclk.3820213547
Short name	T581
Test name
Test status
Simulation time	48442045 ps
CPU time	1.66 seconds
Started	Feb 09 08:26:13 AM UTC 25
Finished	Feb 09 08:26:16 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820213547 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.3820213547
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/34.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/34.clkmgr_frequency.370436895
Short name	T598
Test name
Test status
Simulation time	1522731209 ps
CPU time	15.33 seconds
Started	Feb 09 08:26:13 AM UTC 25
Finished	Feb 09 08:26:30 AM UTC 25
Peak memory	210440 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370436895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.370436895
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/34.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/34.clkmgr_frequency_timeout.3677007233
Short name	T587
Test name
Test status
Simulation time	741238225 ps
CPU time	6.18 seconds
Started	Feb 09 08:26:14 AM UTC 25
Finished	Feb 09 08:26:21 AM UTC 25
Peak memory	210272 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677007233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_timeout.3677007233
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/34.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/34.clkmgr_idle_intersig_mubi.1700774867
Short name	T585
Test name
Test status
Simulation time	104197183 ps
CPU time	1.28 seconds
Started	Feb 09 08:26:17 AM UTC 25
Finished	Feb 09 08:26:19 AM UTC 25
Peak memory	209852 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700774867 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_idle_intersig_mubi.1700774867
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/34.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.2512990219
Short name	T586
Test name
Test status
Simulation time	73729906 ps
CPU time	1.58 seconds
Started	Feb 09 08:26:18 AM UTC 25
Finished	Feb 09 08:26:21 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512990219 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_lc_clk_byp_req_intersig_mubi.2512990219
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.38183075
Short name	T584
Test name
Test status
Simulation time	18008562 ps
CPU time	1.18 seconds
Started	Feb 09 08:26:17 AM UTC 25
Finished	Feb 09 08:26:19 AM UTC 25
Peak memory	209892 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38183075 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_lc_ctrl_intersig_mubi.38183075
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/34.clkmgr_peri.1753841673
Short name	T579
Test name
Test status
Simulation time	21885328 ps
CPU time	1.09 seconds
Started	Feb 09 08:26:14 AM UTC 25
Finished	Feb 09 08:26:16 AM UTC 25
Peak memory	210088 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753841673 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.1753841673
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/34.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/34.clkmgr_regwen.192073543
Short name	T594
Test name
Test status
Simulation time	1079705358 ps
CPU time	6.39 seconds
Started	Feb 09 08:26:20 AM UTC 25
Finished	Feb 09 08:26:28 AM UTC 25
Peak memory	210168 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192073543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.192073543
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/34.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/34.clkmgr_smoke.4152314136
Short name	T580
Test name
Test status
Simulation time	77947554 ps
CPU time	1.51 seconds
Started	Feb 09 08:26:13 AM UTC 25
Finished	Feb 09 08:26:16 AM UTC 25
Peak memory	210324 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152314136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.4152314136
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/34.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/34.clkmgr_stress_all.3905503054
Short name	T71
Test name
Test status
Simulation time	4085272899 ps
CPU time	24.44 seconds
Started	Feb 09 08:26:21 AM UTC 25
Finished	Feb 09 08:26:47 AM UTC 25
Peak memory	210616 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905503054 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all.3905503054
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/34.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/34.clkmgr_stress_all_with_rand_reset.744890095
Short name	T848
Test name
Test status
Simulation time	314008747013 ps
CPU time	1666.72 seconds
Started	Feb 09 08:26:20 AM UTC 25
Finished	Feb 09 08:54:25 AM UTC 25
Peak memory	224308 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=744890095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.c lkmgr_stress_all_with_rand_reset.744890095
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/34.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/34.clkmgr_trans.3059007907
Short name	T582
Test name
Test status
Simulation time	54950248 ps
CPU time	1.52 seconds
Started	Feb 09 08:26:16 AM UTC 25
Finished	Feb 09 08:26:18 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059007907 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.3059007907
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/34.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/35.clkmgr_alert_test.825576924
Short name	T606
Test name
Test status
Simulation time	18659863 ps
CPU time	1.18 seconds
Started	Feb 09 08:26:34 AM UTC 25
Finished	Feb 09 08:26:37 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825576924 -assert nopostproc +U VM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_alert_test.825576924
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/35.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.761894019
Short name	T603
Test name
Test status
Simulation time	22967647 ps
CPU time	1.3 seconds
Started	Feb 09 08:26:31 AM UTC 25
Finished	Feb 09 08:26:34 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761894019 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_handshake_intersig_mubi.761894019
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/35.clkmgr_clk_status.2122576161
Short name	T599
Test name
Test status
Simulation time	16254259 ps
CPU time	0.95 seconds
Started	Feb 09 08:26:29 AM UTC 25
Finished	Feb 09 08:26:31 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122576161 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.2122576161
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/35.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/35.clkmgr_div_intersig_mubi.57039210
Short name	T604
Test name
Test status
Simulation time	150920897 ps
CPU time	1.92 seconds
Started	Feb 09 08:26:32 AM UTC 25
Finished	Feb 09 08:26:35 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57039210 -assert nopostpr oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_div_intersig_mubi.57039210
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/35.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/35.clkmgr_extclk.4131503434
Short name	T593
Test name
Test status
Simulation time	25360824 ps
CPU time	1.21 seconds
Started	Feb 09 08:26:22 AM UTC 25
Finished	Feb 09 08:26:25 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131503434 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.4131503434
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/35.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/35.clkmgr_frequency.503455119
Short name	T597
Test name
Test status
Simulation time	317955843 ps
CPU time	5.36 seconds
Started	Feb 09 08:26:24 AM UTC 25
Finished	Feb 09 08:26:30 AM UTC 25
Peak memory	210248 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503455119 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.503455119
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/35.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/35.clkmgr_frequency_timeout.3448281229
Short name	T610
Test name
Test status
Simulation time	2005862008 ps
CPU time	15.63 seconds
Started	Feb 09 08:26:26 AM UTC 25
Finished	Feb 09 08:26:43 AM UTC 25
Peak memory	210264 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448281229 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_timeout.3448281229
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/35.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/35.clkmgr_idle_intersig_mubi.1294497836
Short name	T600
Test name
Test status
Simulation time	69186089 ps
CPU time	1.17 seconds
Started	Feb 09 08:26:29 AM UTC 25
Finished	Feb 09 08:26:31 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294497836 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_idle_intersig_mubi.1294497836
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/35.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.2737272554
Short name	T602
Test name
Test status
Simulation time	17142468 ps
CPU time	1.16 seconds
Started	Feb 09 08:26:31 AM UTC 25
Finished	Feb 09 08:26:33 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737272554 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_lc_clk_byp_req_intersig_mubi.2737272554
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.230624164
Short name	T601
Test name
Test status
Simulation time	22954776 ps
CPU time	1.31 seconds
Started	Feb 09 08:26:30 AM UTC 25
Finished	Feb 09 08:26:32 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230624164 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_lc_ctrl_intersig_mubi.230624164
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/35.clkmgr_peri.3458481671
Short name	T595
Test name
Test status
Simulation time	21652448 ps
CPU time	1.18 seconds
Started	Feb 09 08:26:26 AM UTC 25
Finished	Feb 09 08:26:28 AM UTC 25
Peak memory	210088 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458481671 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.3458481671
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/35.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/35.clkmgr_regwen.3093554125
Short name	T605
Test name
Test status
Simulation time	262531023 ps
CPU time	2.11 seconds
Started	Feb 09 08:26:32 AM UTC 25
Finished	Feb 09 08:26:36 AM UTC 25
Peak memory	210184 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093554125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.3093554125
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/35.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/35.clkmgr_smoke.2145448680
Short name	T591
Test name
Test status
Simulation time	24239722 ps
CPU time	1.13 seconds
Started	Feb 09 08:26:22 AM UTC 25
Finished	Feb 09 08:26:25 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145448680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.2145448680
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/35.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/35.clkmgr_stress_all.3599282237
Short name	T627
Test name
Test status
Simulation time	2305446282 ps
CPU time	28.98 seconds
Started	Feb 09 08:26:33 AM UTC 25
Finished	Feb 09 08:27:04 AM UTC 25
Peak memory	210804 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599282237 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all.3599282237
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/35.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/35.clkmgr_stress_all_with_rand_reset.3006263183
Short name	T837
Test name
Test status
Simulation time	55698312621 ps
CPU time	748.89 seconds
Started	Feb 09 08:26:32 AM UTC 25
Finished	Feb 09 08:39:10 AM UTC 25
Peak memory	227432 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3006263183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35. clkmgr_stress_all_with_rand_reset.3006263183
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/35.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/35.clkmgr_trans.1826734819
Short name	T596
Test name
Test status
Simulation time	205072744 ps
CPU time	1.8 seconds
Started	Feb 09 08:26:26 AM UTC 25
Finished	Feb 09 08:26:29 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826734819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.1826734819
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/35.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/36.clkmgr_alert_test.3914063880
Short name	T620
Test name
Test status
Simulation time	24812234 ps
CPU time	1.26 seconds
Started	Feb 09 08:26:51 AM UTC 25
Finished	Feb 09 08:26:53 AM UTC 25
Peak memory	208828 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914063880 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_alert_test.3914063880
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/36.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.355006743
Short name	T616
Test name
Test status
Simulation time	18200955 ps
CPU time	1.08 seconds
Started	Feb 09 08:26:46 AM UTC 25
Finished	Feb 09 08:26:48 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355006743 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_handshake_intersig_mubi.355006743
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/36.clkmgr_clk_status.4087252794
Short name	T612
Test name
Test status
Simulation time	43457640 ps
CPU time	1.16 seconds
Started	Feb 09 08:26:41 AM UTC 25
Finished	Feb 09 08:26:43 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087252794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.4087252794
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/36.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/36.clkmgr_div_intersig_mubi.2327201186
Short name	T618
Test name
Test status
Simulation time	22347977 ps
CPU time	1.37 seconds
Started	Feb 09 08:26:47 AM UTC 25
Finished	Feb 09 08:26:50 AM UTC 25
Peak memory	209856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327201186 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_div_intersig_mubi.2327201186
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/36.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/36.clkmgr_extclk.1748815710
Short name	T608
Test name
Test status
Simulation time	25132434 ps
CPU time	1.3 seconds
Started	Feb 09 08:26:37 AM UTC 25
Finished	Feb 09 08:26:39 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748815710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.1748815710
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/36.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/36.clkmgr_frequency.944622254
Short name	T617
Test name
Test status
Simulation time	1547912069 ps
CPU time	11.57 seconds
Started	Feb 09 08:26:37 AM UTC 25
Finished	Feb 09 08:26:49 AM UTC 25
Peak memory	210440 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944622254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.944622254
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/36.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/36.clkmgr_frequency_timeout.997722432
Short name	T628
Test name
Test status
Simulation time	2419127858 ps
CPU time	29.58 seconds
Started	Feb 09 08:26:38 AM UTC 25
Finished	Feb 09 08:27:09 AM UTC 25
Peak memory	210800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997722432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_timeout.997722432
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/36.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/36.clkmgr_idle_intersig_mubi.599578163
Short name	T613
Test name
Test status
Simulation time	35185189 ps
CPU time	1.3 seconds
Started	Feb 09 08:26:43 AM UTC 25
Finished	Feb 09 08:26:45 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599578163 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_idle_intersig_mubi.599578163
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/36.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.2372275672
Short name	T614
Test name
Test status
Simulation time	21198495 ps
CPU time	1.24 seconds
Started	Feb 09 08:26:44 AM UTC 25
Finished	Feb 09 08:26:46 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372275672 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_lc_clk_byp_req_intersig_mubi.2372275672
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.822097737
Short name	T615
Test name
Test status
Simulation time	48309538 ps
CPU time	1.39 seconds
Started	Feb 09 08:26:44 AM UTC 25
Finished	Feb 09 08:26:47 AM UTC 25
Peak memory	210028 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822097737 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_lc_ctrl_intersig_mubi.822097737
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/36.clkmgr_peri.2737026889
Short name	T609
Test name
Test status
Simulation time	21230036 ps
CPU time	1.26 seconds
Started	Feb 09 08:26:38 AM UTC 25
Finished	Feb 09 08:26:40 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737026889 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.2737026889
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/36.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/36.clkmgr_regwen.3572921584
Short name	T622
Test name
Test status
Simulation time	1102693085 ps
CPU time	8.12 seconds
Started	Feb 09 08:26:47 AM UTC 25
Finished	Feb 09 08:26:57 AM UTC 25
Peak memory	210288 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572921584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.3572921584
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/36.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/36.clkmgr_smoke.751432874
Short name	T607
Test name
Test status
Simulation time	46810867 ps
CPU time	1.33 seconds
Started	Feb 09 08:26:35 AM UTC 25
Finished	Feb 09 08:26:37 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751432874 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.751432874
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/36.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/36.clkmgr_stress_all.1687700371
Short name	T635
Test name
Test status
Simulation time	3219479786 ps
CPU time	27.29 seconds
Started	Feb 09 08:26:49 AM UTC 25
Finished	Feb 09 08:27:18 AM UTC 25
Peak memory	210684 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687700371 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all.1687700371
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/36.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/36.clkmgr_stress_all_with_rand_reset.694414213
Short name	T841
Test name
Test status
Simulation time	74219464416 ps
CPU time	885.24 seconds
Started	Feb 09 08:26:48 AM UTC 25
Finished	Feb 09 08:41:44 AM UTC 25
Peak memory	220304 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=694414213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.c lkmgr_stress_all_with_rand_reset.694414213
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/36.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/36.clkmgr_trans.2426081201
Short name	T611
Test name
Test status
Simulation time	88464933 ps
CPU time	1.79 seconds
Started	Feb 09 08:26:40 AM UTC 25
Finished	Feb 09 08:26:43 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426081201 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.2426081201
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/36.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/37.clkmgr_alert_test.606559590
Short name	T639
Test name
Test status
Simulation time	14523671 ps
CPU time	1.18 seconds
Started	Feb 09 08:27:17 AM UTC 25
Finished	Feb 09 08:27:20 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606559590 -assert nopostproc +U VM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_alert_test.606559590
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/37.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.2281907687
Short name	T634
Test name
Test status
Simulation time	92741709 ps
CPU time	1.82 seconds
Started	Feb 09 08:27:14 AM UTC 25
Finished	Feb 09 08:27:17 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281907687 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_handshake_intersig_mubi.2281907687
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/37.clkmgr_clk_status.3830225771
Short name	T629
Test name
Test status
Simulation time	47535829 ps
CPU time	1.15 seconds
Started	Feb 09 08:27:13 AM UTC 25
Finished	Feb 09 08:27:15 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830225771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.3830225771
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/37.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/37.clkmgr_div_intersig_mubi.2692742658
Short name	T633
Test name
Test status
Simulation time	16681746 ps
CPU time	1.1 seconds
Started	Feb 09 08:27:14 AM UTC 25
Finished	Feb 09 08:27:16 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692742658 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_div_intersig_mubi.2692742658
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/37.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/37.clkmgr_extclk.2417228786
Short name	T621
Test name
Test status
Simulation time	44500851 ps
CPU time	1.33 seconds
Started	Feb 09 08:26:54 AM UTC 25
Finished	Feb 09 08:26:56 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417228786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.2417228786
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/37.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/37.clkmgr_frequency.2342961205
Short name	T637
Test name
Test status
Simulation time	2488862037 ps
CPU time	23.88 seconds
Started	Feb 09 08:26:54 AM UTC 25
Finished	Feb 09 08:27:19 AM UTC 25
Peak memory	210896 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342961205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.2342961205
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/37.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/37.clkmgr_frequency_timeout.3389551512
Short name	T626
Test name
Test status
Simulation time	689388449 ps
CPU time	5.03 seconds
Started	Feb 09 08:26:56 AM UTC 25
Finished	Feb 09 08:27:02 AM UTC 25
Peak memory	210272 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389551512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_timeout.3389551512
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/37.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/37.clkmgr_idle_intersig_mubi.543874343
Short name	T630
Test name
Test status
Simulation time	34993534 ps
CPU time	1.52 seconds
Started	Feb 09 08:27:13 AM UTC 25
Finished	Feb 09 08:27:15 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543874343 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_idle_intersig_mubi.543874343
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/37.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.1132280009
Short name	T631
Test name
Test status
Simulation time	16433540 ps
CPU time	1.11 seconds
Started	Feb 09 08:27:14 AM UTC 25
Finished	Feb 09 08:27:16 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132280009 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_lc_clk_byp_req_intersig_mubi.1132280009
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.2646589823
Short name	T632
Test name
Test status
Simulation time	18211772 ps
CPU time	1.17 seconds
Started	Feb 09 08:27:14 AM UTC 25
Finished	Feb 09 08:27:16 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646589823 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_lc_ctrl_intersig_mubi.2646589823
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/37.clkmgr_peri.1055258351
Short name	T623
Test name
Test status
Simulation time	26227490 ps
CPU time	1.18 seconds
Started	Feb 09 08:26:57 AM UTC 25
Finished	Feb 09 08:26:59 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055258351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.1055258351
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/37.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/37.clkmgr_regwen.3045154041
Short name	T636
Test name
Test status
Simulation time	279113204 ps
CPU time	3.02 seconds
Started	Feb 09 08:27:14 AM UTC 25
Finished	Feb 09 08:27:18 AM UTC 25
Peak memory	210188 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045154041 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.3045154041
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/37.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/37.clkmgr_smoke.94235311
Short name	T619
Test name
Test status
Simulation time	28682668 ps
CPU time	1.24 seconds
Started	Feb 09 08:26:51 AM UTC 25
Finished	Feb 09 08:26:53 AM UTC 25
Peak memory	209732 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94235311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.94235311
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/37.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/37.clkmgr_stress_all.2729067172
Short name	T666
Test name
Test status
Simulation time	5984578872 ps
CPU time	24.51 seconds
Started	Feb 09 08:27:16 AM UTC 25
Finished	Feb 09 08:27:42 AM UTC 25
Peak memory	210908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729067172 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all.2729067172
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/37.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/37.clkmgr_stress_all_with_rand_reset.830397842
Short name	T843
Test name
Test status
Simulation time	54254062586 ps
CPU time	1140.93 seconds
Started	Feb 09 08:27:15 AM UTC 25
Finished	Feb 09 08:46:29 AM UTC 25
Peak memory	227368 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=830397842 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.c lkmgr_stress_all_with_rand_reset.830397842
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/37.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/37.clkmgr_trans.127769605
Short name	T624
Test name
Test status
Simulation time	27538778 ps
CPU time	1.27 seconds
Started	Feb 09 08:26:58 AM UTC 25
Finished	Feb 09 08:27:00 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127769605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.127769605
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/37.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/38.clkmgr_alert_test.681145910
Short name	T649
Test name
Test status
Simulation time	23757194 ps
CPU time	1.02 seconds
Started	Feb 09 08:27:26 AM UTC 25
Finished	Feb 09 08:27:29 AM UTC 25
Peak memory	209852 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681145910 -assert nopostproc +U VM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_alert_test.681145910
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/38.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.1505498843
Short name	T647
Test name
Test status
Simulation time	39029105 ps
CPU time	1.17 seconds
Started	Feb 09 08:27:23 AM UTC 25
Finished	Feb 09 08:27:25 AM UTC 25
Peak memory	210036 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505498843 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_handshake_intersig_mubi.1505498843
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/38.clkmgr_clk_status.2091610754
Short name	T645
Test name
Test status
Simulation time	114792765 ps
CPU time	1.58 seconds
Started	Feb 09 08:27:21 AM UTC 25
Finished	Feb 09 08:27:23 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091610754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.2091610754
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/38.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/38.clkmgr_div_intersig_mubi.899053479
Short name	T648
Test name
Test status
Simulation time	41677705 ps
CPU time	1.47 seconds
Started	Feb 09 08:27:24 AM UTC 25
Finished	Feb 09 08:27:27 AM UTC 25
Peak memory	209372 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899053479 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_div_intersig_mubi.899053479
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/38.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/38.clkmgr_extclk.3039766526
Short name	T640
Test name
Test status
Simulation time	29045748 ps
CPU time	1.2 seconds
Started	Feb 09 08:27:17 AM UTC 25
Finished	Feb 09 08:27:20 AM UTC 25
Peak memory	209916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039766526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.3039766526
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/38.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/38.clkmgr_frequency.2684741533
Short name	T662
Test name
Test status
Simulation time	2474669388 ps
CPU time	20.17 seconds
Started	Feb 09 08:27:17 AM UTC 25
Finished	Feb 09 08:27:39 AM UTC 25
Peak memory	210840 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684741533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.2684741533
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/38.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/38.clkmgr_frequency_timeout.2078840579
Short name	T652
Test name
Test status
Simulation time	1946592447 ps
CPU time	12.05 seconds
Started	Feb 09 08:27:18 AM UTC 25
Finished	Feb 09 08:27:32 AM UTC 25
Peak memory	210456 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078840579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_timeout.2078840579
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/38.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/38.clkmgr_idle_intersig_mubi.19636080
Short name	T643
Test name
Test status
Simulation time	34992291 ps
CPU time	1.29 seconds
Started	Feb 09 08:27:21 AM UTC 25
Finished	Feb 09 08:27:23 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19636080 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_idle_intersig_mubi.19636080
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/38.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.1407282613
Short name	T646
Test name
Test status
Simulation time	16157097 ps
CPU time	1.2 seconds
Started	Feb 09 08:27:23 AM UTC 25
Finished	Feb 09 08:27:25 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407282613 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_lc_clk_byp_req_intersig_mubi.1407282613
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.3234870103
Short name	T644
Test name
Test status
Simulation time	57387148 ps
CPU time	1.41 seconds
Started	Feb 09 08:27:21 AM UTC 25
Finished	Feb 09 08:27:23 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234870103 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_lc_ctrl_intersig_mubi.3234870103
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/38.clkmgr_peri.3028111098
Short name	T641
Test name
Test status
Simulation time	20091547 ps
CPU time	1.22 seconds
Started	Feb 09 08:27:20 AM UTC 25
Finished	Feb 09 08:27:22 AM UTC 25
Peak memory	210324 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028111098 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.3028111098
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/38.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/38.clkmgr_regwen.3520231039
Short name	T651
Test name
Test status
Simulation time	757294362 ps
CPU time	5.59 seconds
Started	Feb 09 08:27:24 AM UTC 25
Finished	Feb 09 08:27:31 AM UTC 25
Peak memory	210624 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520231039 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.3520231039
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/38.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/38.clkmgr_smoke.681276884
Short name	T638
Test name
Test status
Simulation time	18898874 ps
CPU time	1 seconds
Started	Feb 09 08:27:17 AM UTC 25
Finished	Feb 09 08:27:20 AM UTC 25
Peak memory	209784 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681276884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.681276884
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/38.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/38.clkmgr_stress_all.1167020816
Short name	T740
Test name
Test status
Simulation time	8716939626 ps
CPU time	82.54 seconds
Started	Feb 09 08:27:24 AM UTC 25
Finished	Feb 09 08:28:49 AM UTC 25
Peak memory	210712 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167020816 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all.1167020816
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/38.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/38.clkmgr_stress_all_with_rand_reset.3336724544
Short name	T829
Test name
Test status
Simulation time	16917542428 ps
CPU time	356.64 seconds
Started	Feb 09 08:27:24 AM UTC 25
Finished	Feb 09 08:33:26 AM UTC 25
Peak memory	220344 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3336724544 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38. clkmgr_stress_all_with_rand_reset.3336724544
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/38.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/38.clkmgr_trans.4095259871
Short name	T642
Test name
Test status
Simulation time	71163151 ps
CPU time	1.81 seconds
Started	Feb 09 08:27:20 AM UTC 25
Finished	Feb 09 08:27:23 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095259871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.4095259871
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/38.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/39.clkmgr_alert_test.1108318489
Short name	T664
Test name
Test status
Simulation time	61189440 ps
CPU time	1.52 seconds
Started	Feb 09 08:27:38 AM UTC 25
Finished	Feb 09 08:27:41 AM UTC 25
Peak memory	208888 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108318489 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_alert_test.1108318489
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/39.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.1164853705
Short name	T660
Test name
Test status
Simulation time	41741647 ps
CPU time	1.4 seconds
Started	Feb 09 08:27:34 AM UTC 25
Finished	Feb 09 08:27:37 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164853705 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_handshake_intersig_mubi.1164853705
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/39.clkmgr_clk_status.1552167893
Short name	T656
Test name
Test status
Simulation time	16283621 ps
CPU time	1.07 seconds
Started	Feb 09 08:27:32 AM UTC 25
Finished	Feb 09 08:27:35 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552167893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.1552167893
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/39.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/39.clkmgr_div_intersig_mubi.3590010648
Short name	T661
Test name
Test status
Simulation time	40709733 ps
CPU time	1.43 seconds
Started	Feb 09 08:27:35 AM UTC 25
Finished	Feb 09 08:27:38 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590010648 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_div_intersig_mubi.3590010648
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/39.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/39.clkmgr_extclk.3765960960
Short name	T654
Test name
Test status
Simulation time	83727810 ps
CPU time	1.66 seconds
Started	Feb 09 08:27:30 AM UTC 25
Finished	Feb 09 08:27:33 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765960960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.3765960960
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/39.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/39.clkmgr_frequency.508708841
Short name	T667
Test name
Test status
Simulation time	1046199731 ps
CPU time	11.15 seconds
Started	Feb 09 08:27:30 AM UTC 25
Finished	Feb 09 08:27:43 AM UTC 25
Peak memory	210248 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508708841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.508708841
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/39.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/39.clkmgr_frequency_timeout.2369201052
Short name	T663
Test name
Test status
Simulation time	1229458836 ps
CPU time	7.79 seconds
Started	Feb 09 08:27:30 AM UTC 25
Finished	Feb 09 08:27:39 AM UTC 25
Peak memory	210272 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369201052 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_timeout.2369201052
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/39.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/39.clkmgr_idle_intersig_mubi.2474121841
Short name	T659
Test name
Test status
Simulation time	65003610 ps
CPU time	1.45 seconds
Started	Feb 09 08:27:33 AM UTC 25
Finished	Feb 09 08:27:36 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474121841 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_idle_intersig_mubi.2474121841
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/39.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.2634990079
Short name	T658
Test name
Test status
Simulation time	46758175 ps
CPU time	1.39 seconds
Started	Feb 09 08:27:33 AM UTC 25
Finished	Feb 09 08:27:36 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634990079 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_lc_clk_byp_req_intersig_mubi.2634990079
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.1911761740
Short name	T657
Test name
Test status
Simulation time	25232454 ps
CPU time	1.25 seconds
Started	Feb 09 08:27:33 AM UTC 25
Finished	Feb 09 08:27:36 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911761740 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_lc_ctrl_intersig_mubi.1911761740
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/39.clkmgr_peri.1741266417
Short name	T653
Test name
Test status
Simulation time	32524974 ps
CPU time	1.25 seconds
Started	Feb 09 08:27:30 AM UTC 25
Finished	Feb 09 08:27:33 AM UTC 25
Peak memory	210088 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741266417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.1741266417
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/39.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/39.clkmgr_regwen.2504481165
Short name	T669
Test name
Test status
Simulation time	550524149 ps
CPU time	6.43 seconds
Started	Feb 09 08:27:37 AM UTC 25
Finished	Feb 09 08:27:44 AM UTC 25
Peak memory	210184 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504481165 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.2504481165
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/39.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/39.clkmgr_smoke.890264534
Short name	T650
Test name
Test status
Simulation time	35701928 ps
CPU time	1.23 seconds
Started	Feb 09 08:27:26 AM UTC 25
Finished	Feb 09 08:27:29 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890264534 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.890264534
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/39.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/39.clkmgr_stress_all.3741137305
Short name	T701
Test name
Test status
Simulation time	5701718878 ps
CPU time	33.96 seconds
Started	Feb 09 08:27:37 AM UTC 25
Finished	Feb 09 08:28:12 AM UTC 25
Peak memory	210680 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741137305 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all.3741137305
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/39.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/39.clkmgr_stress_all_with_rand_reset.2649271639
Short name	T845
Test name
Test status
Simulation time	166699452610 ps
CPU time	1133.43 seconds
Started	Feb 09 08:27:37 AM UTC 25
Finished	Feb 09 08:46:43 AM UTC 25
Peak memory	227244 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2649271639 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39. clkmgr_stress_all_with_rand_reset.2649271639
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/39.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/39.clkmgr_trans.2921188966
Short name	T655
Test name
Test status
Simulation time	47916908 ps
CPU time	1.56 seconds
Started	Feb 09 08:27:30 AM UTC 25
Finished	Feb 09 08:27:33 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921188966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.2921188966
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/39.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_alert_test.2864573161
Short name	T208
Test name
Test status
Simulation time	16247204 ps
CPU time	1.13 seconds
Started	Feb 09 08:17:18 AM UTC 25
Finished	Feb 09 08:17:20 AM UTC 25
Peak memory	208824 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864573161 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_alert_test.2864573161
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.105572452
Short name	T168
Test name
Test status
Simulation time	99176533 ps
CPU time	1.72 seconds
Started	Feb 09 08:17:11 AM UTC 25
Finished	Feb 09 08:17:14 AM UTC 25
Peak memory	209916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105572452 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_handshake_intersig_mubi.105572452
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_clk_status.1119664071
Short name	T161
Test name
Test status
Simulation time	16339855 ps
CPU time	1.13 seconds
Started	Feb 09 08:17:02 AM UTC 25
Finished	Feb 09 08:17:04 AM UTC 25
Peak memory	208816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119664071 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.1119664071
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_div_intersig_mubi.863549618
Short name	T165
Test name
Test status
Simulation time	28355196 ps
CPU time	1.37 seconds
Started	Feb 09 08:17:11 AM UTC 25
Finished	Feb 09 08:17:13 AM UTC 25
Peak memory	210092 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863549618 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_div_intersig_mubi.863549618
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_extclk.604388366
Short name	T206
Test name
Test status
Simulation time	38160476 ps
CPU time	1.09 seconds
Started	Feb 09 08:16:52 AM UTC 25
Finished	Feb 09 08:16:54 AM UTC 25
Peak memory	209852 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604388366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.604388366
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_frequency.1682585655
Short name	T12
Test name
Test status
Simulation time	1327884750 ps
CPU time	12.91 seconds
Started	Feb 09 08:16:53 AM UTC 25
Finished	Feb 09 08:17:07 AM UTC 25
Peak memory	210436 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682585655 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.1682585655
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_frequency_timeout.3635383990
Short name	T66
Test name
Test status
Simulation time	2341348311 ps
CPU time	15.85 seconds
Started	Feb 09 08:16:55 AM UTC 25
Finished	Feb 09 08:17:13 AM UTC 25
Peak memory	210812 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635383990 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_timeout.3635383990
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_idle_intersig_mubi.3058476774
Short name	T163
Test name
Test status
Simulation time	20221035 ps
CPU time	1.12 seconds
Started	Feb 09 08:17:07 AM UTC 25
Finished	Feb 09 08:17:10 AM UTC 25
Peak memory	209832 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058476774 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_idle_intersig_mubi.3058476774
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.2379144853
Short name	T164
Test name
Test status
Simulation time	45205952 ps
CPU time	1.23 seconds
Started	Feb 09 08:17:09 AM UTC 25
Finished	Feb 09 08:17:11 AM UTC 25
Peak memory	210028 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379144853 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_lc_clk_byp_req_intersig_mubi.2379144853
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.2587195231
Short name	T162
Test name
Test status
Simulation time	22364474 ps
CPU time	1.05 seconds
Started	Feb 09 08:17:07 AM UTC 25
Finished	Feb 09 08:17:10 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587195231 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_lc_ctrl_intersig_mubi.2587195231
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_peri.3562489743
Short name	T159
Test name
Test status
Simulation time	37567866 ps
CPU time	1.19 seconds
Started	Feb 09 08:16:55 AM UTC 25
Finished	Feb 09 08:16:58 AM UTC 25
Peak memory	210096 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562489743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.3562489743
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_regwen.651904842
Short name	T105
Test name
Test status
Simulation time	382080100 ps
CPU time	3.79 seconds
Started	Feb 09 08:17:12 AM UTC 25
Finished	Feb 09 08:17:17 AM UTC 25
Peak memory	210184 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651904842 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.651904842
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_sec_cm.4188818341
Short name	T76
Test name
Test status
Simulation time	900453296 ps
CPU time	8.12 seconds
Started	Feb 09 08:17:13 AM UTC 25
Finished	Feb 09 08:17:22 AM UTC 25
Peak memory	242616 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188818341 -assert nopostproc +U VM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_sec_cm.4188818341
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_smoke.2295661841
Short name	T136
Test name
Test status
Simulation time	51049260 ps
CPU time	1.4 seconds
Started	Feb 09 08:16:52 AM UTC 25
Finished	Feb 09 08:16:55 AM UTC 25
Peak memory	209792 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295661841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.2295661841
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_stress_all.1698863575
Short name	T15
Test name
Test status
Simulation time	598988038 ps
CPU time	11.35 seconds
Started	Feb 09 08:17:15 AM UTC 25
Finished	Feb 09 08:17:28 AM UTC 25
Peak memory	210244 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698863575 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all.1698863575
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/4.clkmgr_trans.2581108594
Short name	T160
Test name
Test status
Simulation time	28516390 ps
CPU time	1.4 seconds
Started	Feb 09 08:16:58 AM UTC 25
Finished	Feb 09 08:17:01 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581108594 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.2581108594
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/4.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/40.clkmgr_alert_test.1127536677
Short name	T680
Test name
Test status
Simulation time	12425437 ps
CPU time	1.08 seconds
Started	Feb 09 08:27:50 AM UTC 25
Finished	Feb 09 08:27:53 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127536677 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_alert_test.1127536677
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/40.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.3925463313
Short name	T677
Test name
Test status
Simulation time	66544948 ps
CPU time	1.36 seconds
Started	Feb 09 08:27:47 AM UTC 25
Finished	Feb 09 08:27:49 AM UTC 25
Peak memory	209856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925463313 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_handshake_intersig_mubi.3925463313
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/40.clkmgr_clk_status.3334121373
Short name	T671
Test name
Test status
Simulation time	28264013 ps
CPU time	1.11 seconds
Started	Feb 09 08:27:43 AM UTC 25
Finished	Feb 09 08:27:46 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334121373 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.3334121373
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/40.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/40.clkmgr_div_intersig_mubi.1370271535
Short name	T678
Test name
Test status
Simulation time	20335398 ps
CPU time	1.32 seconds
Started	Feb 09 08:27:48 AM UTC 25
Finished	Feb 09 08:27:50 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370271535 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_div_intersig_mubi.1370271535
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/40.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/40.clkmgr_extclk.1787916447
Short name	T668
Test name
Test status
Simulation time	79992526 ps
CPU time	1.55 seconds
Started	Feb 09 08:27:40 AM UTC 25
Finished	Feb 09 08:27:43 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787916447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.1787916447
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/40.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/40.clkmgr_frequency.1442223924
Short name	T676
Test name
Test status
Simulation time	1166493092 ps
CPU time	7.3 seconds
Started	Feb 09 08:27:40 AM UTC 25
Finished	Feb 09 08:27:49 AM UTC 25
Peak memory	210240 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442223924 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.1442223924
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/40.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/40.clkmgr_frequency_timeout.562108046
Short name	T687
Test name
Test status
Simulation time	1582287532 ps
CPU time	13.93 seconds
Started	Feb 09 08:27:42 AM UTC 25
Finished	Feb 09 08:27:57 AM UTC 25
Peak memory	210268 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562108046 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_timeout.562108046
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/40.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/40.clkmgr_idle_intersig_mubi.3226886602
Short name	T673
Test name
Test status
Simulation time	294647609 ps
CPU time	3.04 seconds
Started	Feb 09 08:27:43 AM UTC 25
Finished	Feb 09 08:27:48 AM UTC 25
Peak memory	210376 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226886602 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_idle_intersig_mubi.3226886602
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/40.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.874264512
Short name	T674
Test name
Test status
Simulation time	37034459 ps
CPU time	1.36 seconds
Started	Feb 09 08:27:45 AM UTC 25
Finished	Feb 09 08:27:48 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874264512 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_lc_clk_byp_req_intersig_mubi.874264512
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.3785978798
Short name	T675
Test name
Test status
Simulation time	72135974 ps
CPU time	1.63 seconds
Started	Feb 09 08:27:45 AM UTC 25
Finished	Feb 09 08:27:48 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785978798 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_lc_ctrl_intersig_mubi.3785978798
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/40.clkmgr_peri.2134426858
Short name	T670
Test name
Test status
Simulation time	30021137 ps
CPU time	1.11 seconds
Started	Feb 09 08:27:42 AM UTC 25
Finished	Feb 09 08:27:45 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134426858 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.2134426858
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/40.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/40.clkmgr_regwen.3591552533
Short name	T679
Test name
Test status
Simulation time	322920496 ps
CPU time	2.34 seconds
Started	Feb 09 08:27:49 AM UTC 25
Finished	Feb 09 08:27:52 AM UTC 25
Peak memory	210376 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591552533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.3591552533
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/40.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/40.clkmgr_smoke.1072140028
Short name	T665
Test name
Test status
Simulation time	34975916 ps
CPU time	1.28 seconds
Started	Feb 09 08:27:39 AM UTC 25
Finished	Feb 09 08:27:41 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072140028 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.1072140028
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/40.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/40.clkmgr_stress_all.2570077967
Short name	T716
Test name
Test status
Simulation time	8584337873 ps
CPU time	36.7 seconds
Started	Feb 09 08:27:49 AM UTC 25
Finished	Feb 09 08:28:27 AM UTC 25
Peak memory	210620 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570077967 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all.2570077967
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/40.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/40.clkmgr_stress_all_with_rand_reset.1867846324
Short name	T179
Test name
Test status
Simulation time	16305479564 ps
CPU time	268.45 seconds
Started	Feb 09 08:27:49 AM UTC 25
Finished	Feb 09 08:32:21 AM UTC 25
Peak memory	227208 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1867846324 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40. clkmgr_stress_all_with_rand_reset.1867846324
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/40.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/40.clkmgr_trans.2271894048
Short name	T672
Test name
Test status
Simulation time	54792707 ps
CPU time	1.56 seconds
Started	Feb 09 08:27:43 AM UTC 25
Finished	Feb 09 08:27:46 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271894048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.2271894048
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/40.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/41.clkmgr_alert_test.3385241118
Short name	T692
Test name
Test status
Simulation time	25065246 ps
CPU time	1.23 seconds
Started	Feb 09 08:28:00 AM UTC 25
Finished	Feb 09 08:28:03 AM UTC 25
Peak memory	209780 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385241118 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_alert_test.3385241118
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/41.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.566859355
Short name	T690
Test name
Test status
Simulation time	21053347 ps
CPU time	1.29 seconds
Started	Feb 09 08:27:57 AM UTC 25
Finished	Feb 09 08:27:59 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566859355 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_handshake_intersig_mubi.566859355
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/41.clkmgr_clk_status.2434057176
Short name	T684
Test name
Test status
Simulation time	27319750 ps
CPU time	1.09 seconds
Started	Feb 09 08:27:53 AM UTC 25
Finished	Feb 09 08:27:56 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434057176 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.2434057176
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/41.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/41.clkmgr_div_intersig_mubi.1173122632
Short name	T691
Test name
Test status
Simulation time	51748128 ps
CPU time	1.56 seconds
Started	Feb 09 08:27:57 AM UTC 25
Finished	Feb 09 08:28:00 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173122632 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_div_intersig_mubi.1173122632
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/41.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/41.clkmgr_extclk.577864979
Short name	T682
Test name
Test status
Simulation time	33217305 ps
CPU time	1.1 seconds
Started	Feb 09 08:27:50 AM UTC 25
Finished	Feb 09 08:27:53 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577864979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.577864979
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/41.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/41.clkmgr_frequency.3104824863
Short name	T694
Test name
Test status
Simulation time	1425480892 ps
CPU time	12.34 seconds
Started	Feb 09 08:27:51 AM UTC 25
Finished	Feb 09 08:28:05 AM UTC 25
Peak memory	210244 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104824863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.3104824863
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/41.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/41.clkmgr_frequency_timeout.1111276519
Short name	T698
Test name
Test status
Simulation time	1592352605 ps
CPU time	14.99 seconds
Started	Feb 09 08:27:53 AM UTC 25
Finished	Feb 09 08:28:10 AM UTC 25
Peak memory	210336 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111276519 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_timeout.1111276519
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/41.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/41.clkmgr_idle_intersig_mubi.2718577365
Short name	T686
Test name
Test status
Simulation time	74669214 ps
CPU time	1.47 seconds
Started	Feb 09 08:27:53 AM UTC 25
Finished	Feb 09 08:27:56 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718577365 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_idle_intersig_mubi.2718577365
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/41.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.158696631
Short name	T688
Test name
Test status
Simulation time	13776450 ps
CPU time	1.11 seconds
Started	Feb 09 08:27:57 AM UTC 25
Finished	Feb 09 08:27:59 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158696631 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_lc_clk_byp_req_intersig_mubi.158696631
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.353341598
Short name	T689
Test name
Test status
Simulation time	35633604 ps
CPU time	1.27 seconds
Started	Feb 09 08:27:57 AM UTC 25
Finished	Feb 09 08:27:59 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353341598 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_lc_ctrl_intersig_mubi.353341598
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/41.clkmgr_peri.1215373118
Short name	T683
Test name
Test status
Simulation time	13723482 ps
CPU time	0.99 seconds
Started	Feb 09 08:27:53 AM UTC 25
Finished	Feb 09 08:27:56 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215373118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.1215373118
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/41.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/41.clkmgr_regwen.3749210443
Short name	T696
Test name
Test status
Simulation time	1041440126 ps
CPU time	7.74 seconds
Started	Feb 09 08:27:58 AM UTC 25
Finished	Feb 09 08:28:07 AM UTC 25
Peak memory	210496 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749210443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.3749210443
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/41.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/41.clkmgr_smoke.3455807738
Short name	T681
Test name
Test status
Simulation time	15285656 ps
CPU time	1.16 seconds
Started	Feb 09 08:27:50 AM UTC 25
Finished	Feb 09 08:27:53 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455807738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.3455807738
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/41.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/41.clkmgr_stress_all.598641209
Short name	T706
Test name
Test status
Simulation time	2058835461 ps
CPU time	15.39 seconds
Started	Feb 09 08:28:00 AM UTC 25
Finished	Feb 09 08:28:17 AM UTC 25
Peak memory	210428 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598641209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all.598641209
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/41.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/41.clkmgr_stress_all_with_rand_reset.3619743333
Short name	T183
Test name
Test status
Simulation time	94286803899 ps
CPU time	634 seconds
Started	Feb 09 08:28:00 AM UTC 25
Finished	Feb 09 08:38:42 AM UTC 25
Peak memory	227152 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3619743333 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41. clkmgr_stress_all_with_rand_reset.3619743333
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/41.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/41.clkmgr_trans.738808828
Short name	T685
Test name
Test status
Simulation time	28950356 ps
CPU time	1.24 seconds
Started	Feb 09 08:27:53 AM UTC 25
Finished	Feb 09 08:27:56 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738808828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.738808828
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/41.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/42.clkmgr_alert_test.1862832898
Short name	T708
Test name
Test status
Simulation time	33273628 ps
CPU time	1.23 seconds
Started	Feb 09 08:28:17 AM UTC 25
Finished	Feb 09 08:28:20 AM UTC 25
Peak memory	209856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862832898 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_alert_test.1862832898
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/42.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.678685118
Short name	T705
Test name
Test status
Simulation time	30776165 ps
CPU time	1.49 seconds
Started	Feb 09 08:28:13 AM UTC 25
Finished	Feb 09 08:28:16 AM UTC 25
Peak memory	209852 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678685118 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_handshake_intersig_mubi.678685118
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/42.clkmgr_clk_status.1883170455
Short name	T700
Test name
Test status
Simulation time	32287071 ps
CPU time	1.19 seconds
Started	Feb 09 08:28:10 AM UTC 25
Finished	Feb 09 08:28:12 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883170455 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.1883170455
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/42.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/42.clkmgr_div_intersig_mubi.3862015554
Short name	T707
Test name
Test status
Simulation time	165863939 ps
CPU time	2.19 seconds
Started	Feb 09 08:28:14 AM UTC 25
Finished	Feb 09 08:28:17 AM UTC 25
Peak memory	209924 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862015554 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_div_intersig_mubi.3862015554
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/42.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/42.clkmgr_extclk.1263595516
Short name	T695
Test name
Test status
Simulation time	13407159 ps
CPU time	0.99 seconds
Started	Feb 09 08:28:03 AM UTC 25
Finished	Feb 09 08:28:05 AM UTC 25
Peak memory	209904 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263595516 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.1263595516
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/42.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/42.clkmgr_frequency.1583482401
Short name	T710
Test name
Test status
Simulation time	1530210366 ps
CPU time	16.91 seconds
Started	Feb 09 08:28:03 AM UTC 25
Finished	Feb 09 08:28:22 AM UTC 25
Peak memory	210156 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583482401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.1583482401
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/42.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/42.clkmgr_frequency_timeout.1374553984
Short name	T711
Test name
Test status
Simulation time	2235445061 ps
CPU time	15.24 seconds
Started	Feb 09 08:28:06 AM UTC 25
Finished	Feb 09 08:28:23 AM UTC 25
Peak memory	210836 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374553984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_timeout.1374553984
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/42.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/42.clkmgr_idle_intersig_mubi.3098022471
Short name	T703
Test name
Test status
Simulation time	23104910 ps
CPU time	1.4 seconds
Started	Feb 09 08:28:11 AM UTC 25
Finished	Feb 09 08:28:13 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098022471 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_idle_intersig_mubi.3098022471
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/42.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.329839351
Short name	T704
Test name
Test status
Simulation time	51395733 ps
CPU time	1.24 seconds
Started	Feb 09 08:28:13 AM UTC 25
Finished	Feb 09 08:28:15 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329839351 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_lc_clk_byp_req_intersig_mubi.329839351
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.1747909676
Short name	T702
Test name
Test status
Simulation time	18203512 ps
CPU time	1.24 seconds
Started	Feb 09 08:28:11 AM UTC 25
Finished	Feb 09 08:28:13 AM UTC 25
Peak memory	210028 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747909676 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_lc_ctrl_intersig_mubi.1747909676
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/42.clkmgr_peri.1758939313
Short name	T697
Test name
Test status
Simulation time	35877960 ps
CPU time	1.26 seconds
Started	Feb 09 08:28:06 AM UTC 25
Finished	Feb 09 08:28:09 AM UTC 25
Peak memory	210088 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758939313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.1758939313
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/42.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/42.clkmgr_regwen.1707307218
Short name	T714
Test name
Test status
Simulation time	1160387878 ps
CPU time	10.86 seconds
Started	Feb 09 08:28:14 AM UTC 25
Finished	Feb 09 08:28:26 AM UTC 25
Peak memory	210172 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707307218 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.1707307218
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/42.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/42.clkmgr_smoke.2799000889
Short name	T693
Test name
Test status
Simulation time	43987728 ps
CPU time	1.31 seconds
Started	Feb 09 08:28:00 AM UTC 25
Finished	Feb 09 08:28:03 AM UTC 25
Peak memory	210324 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799000889 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.2799000889
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/42.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/42.clkmgr_stress_all.340129320
Short name	T756
Test name
Test status
Simulation time	4813539164 ps
CPU time	49.47 seconds
Started	Feb 09 08:28:16 AM UTC 25
Finished	Feb 09 08:29:08 AM UTC 25
Peak memory	210608 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340129320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all.340129320
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/42.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/42.clkmgr_stress_all_with_rand_reset.2473100421
Short name	T839
Test name
Test status
Simulation time	98136769723 ps
CPU time	703.08 seconds
Started	Feb 09 08:28:16 AM UTC 25
Finished	Feb 09 08:40:07 AM UTC 25
Peak memory	220212 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2473100421 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42. clkmgr_stress_all_with_rand_reset.2473100421
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/42.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/42.clkmgr_trans.2380943036
Short name	T699
Test name
Test status
Simulation time	27385565 ps
CPU time	1.5 seconds
Started	Feb 09 08:28:08 AM UTC 25
Finished	Feb 09 08:28:10 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380943036 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.2380943036
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/42.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/43.clkmgr_alert_test.821291921
Short name	T725
Test name
Test status
Simulation time	16042015 ps
CPU time	1.16 seconds
Started	Feb 09 08:28:32 AM UTC 25
Finished	Feb 09 08:28:34 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821291921 -assert nopostproc +U VM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_alert_test.821291921
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/43.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.1183810309
Short name	T723
Test name
Test status
Simulation time	21251273 ps
CPU time	1.28 seconds
Started	Feb 09 08:28:30 AM UTC 25
Finished	Feb 09 08:28:33 AM UTC 25
Peak memory	209916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183810309 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_handshake_intersig_mubi.1183810309
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/43.clkmgr_clk_status.3959495894
Short name	T718
Test name
Test status
Simulation time	12900135 ps
CPU time	1.09 seconds
Started	Feb 09 08:28:27 AM UTC 25
Finished	Feb 09 08:28:29 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959495894 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.3959495894
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/43.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/43.clkmgr_div_intersig_mubi.2052858339
Short name	T724
Test name
Test status
Simulation time	27691841 ps
CPU time	1.4 seconds
Started	Feb 09 08:28:30 AM UTC 25
Finished	Feb 09 08:28:33 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052858339 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_div_intersig_mubi.2052858339
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/43.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/43.clkmgr_extclk.1857393757
Short name	T712
Test name
Test status
Simulation time	278901648 ps
CPU time	2.79 seconds
Started	Feb 09 08:28:20 AM UTC 25
Finished	Feb 09 08:28:25 AM UTC 25
Peak memory	210184 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857393757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.1857393757
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/43.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/43.clkmgr_frequency.1536714317
Short name	T719
Test name
Test status
Simulation time	1103622485 ps
CPU time	6.75 seconds
Started	Feb 09 08:28:22 AM UTC 25
Finished	Feb 09 08:28:30 AM UTC 25
Peak memory	210244 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536714317 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.1536714317
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/43.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/43.clkmgr_frequency_timeout.55640858
Short name	T715
Test name
Test status
Simulation time	282250078 ps
CPU time	2.82 seconds
Started	Feb 09 08:28:23 AM UTC 25
Finished	Feb 09 08:28:27 AM UTC 25
Peak memory	210464 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55640858 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_timeout.55640858
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/43.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/43.clkmgr_idle_intersig_mubi.3386462214
Short name	T720
Test name
Test status
Simulation time	83707214 ps
CPU time	1.66 seconds
Started	Feb 09 08:28:27 AM UTC 25
Finished	Feb 09 08:28:30 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386462214 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_idle_intersig_mubi.3386462214
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/43.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.2578465435
Short name	T722
Test name
Test status
Simulation time	48886686 ps
CPU time	1.31 seconds
Started	Feb 09 08:28:28 AM UTC 25
Finished	Feb 09 08:28:31 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578465435 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_lc_clk_byp_req_intersig_mubi.2578465435
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.117438548
Short name	T721
Test name
Test status
Simulation time	21945078 ps
CPU time	1.16 seconds
Started	Feb 09 08:28:28 AM UTC 25
Finished	Feb 09 08:28:31 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117438548 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_lc_ctrl_intersig_mubi.117438548
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/43.clkmgr_peri.1053552133
Short name	T713
Test name
Test status
Simulation time	19696173 ps
CPU time	1.21 seconds
Started	Feb 09 08:28:24 AM UTC 25
Finished	Feb 09 08:28:26 AM UTC 25
Peak memory	210088 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053552133 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.1053552133
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/43.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/43.clkmgr_regwen.3490463147
Short name	T729
Test name
Test status
Simulation time	866491011 ps
CPU time	5.46 seconds
Started	Feb 09 08:28:30 AM UTC 25
Finished	Feb 09 08:28:37 AM UTC 25
Peak memory	210396 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490463147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.3490463147
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/43.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/43.clkmgr_smoke.3563187124
Short name	T709
Test name
Test status
Simulation time	89949672 ps
CPU time	1.52 seconds
Started	Feb 09 08:28:18 AM UTC 25
Finished	Feb 09 08:28:21 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563187124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.3563187124
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/43.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/43.clkmgr_stress_all.955592709
Short name	T726
Test name
Test status
Simulation time	21894719 ps
CPU time	1.18 seconds
Started	Feb 09 08:28:32 AM UTC 25
Finished	Feb 09 08:28:34 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955592709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all.955592709
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/43.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/43.clkmgr_stress_all_with_rand_reset.3909120378
Short name	T846
Test name
Test status
Simulation time	257674016558 ps
CPU time	1104.01 seconds
Started	Feb 09 08:28:30 AM UTC 25
Finished	Feb 09 08:47:06 AM UTC 25
Peak memory	227100 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3909120378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43. clkmgr_stress_all_with_rand_reset.3909120378
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/43.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/43.clkmgr_trans.917206181
Short name	T717
Test name
Test status
Simulation time	231152116 ps
CPU time	2.05 seconds
Started	Feb 09 08:28:26 AM UTC 25
Finished	Feb 09 08:28:29 AM UTC 25
Peak memory	210180 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917206181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.917206181
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/43.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/44.clkmgr_alert_test.2013062138
Short name	T741
Test name
Test status
Simulation time	25356872 ps
CPU time	1.01 seconds
Started	Feb 09 08:28:48 AM UTC 25
Finished	Feb 09 08:28:50 AM UTC 25
Peak memory	209916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013062138 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_alert_test.2013062138
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/44.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.3058363704
Short name	T736
Test name
Test status
Simulation time	23443539 ps
CPU time	1.41 seconds
Started	Feb 09 08:28:43 AM UTC 25
Finished	Feb 09 08:28:46 AM UTC 25
Peak memory	209916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058363704 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_handshake_intersig_mubi.3058363704
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/44.clkmgr_clk_status.2025089707
Short name	T732
Test name
Test status
Simulation time	18296832 ps
CPU time	1.17 seconds
Started	Feb 09 08:28:38 AM UTC 25
Finished	Feb 09 08:28:41 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025089707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.2025089707
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/44.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/44.clkmgr_div_intersig_mubi.4220156130
Short name	T737
Test name
Test status
Simulation time	25508064 ps
CPU time	1.32 seconds
Started	Feb 09 08:28:44 AM UTC 25
Finished	Feb 09 08:28:47 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220156130 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_div_intersig_mubi.4220156130
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/44.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/44.clkmgr_extclk.3523703284
Short name	T727
Test name
Test status
Simulation time	27013787 ps
CPU time	1.18 seconds
Started	Feb 09 08:28:34 AM UTC 25
Finished	Feb 09 08:28:36 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523703284 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.3523703284
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/44.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/44.clkmgr_frequency.2653163601
Short name	T739
Test name
Test status
Simulation time	1573770902 ps
CPU time	11.44 seconds
Started	Feb 09 08:28:35 AM UTC 25
Finished	Feb 09 08:28:48 AM UTC 25
Peak memory	210192 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653163601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.2653163601
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/44.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/44.clkmgr_frequency_timeout.1551955736
Short name	T743
Test name
Test status
Simulation time	1217098221 ps
CPU time	15.86 seconds
Started	Feb 09 08:28:35 AM UTC 25
Finished	Feb 09 08:28:52 AM UTC 25
Peak memory	210240 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551955736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_timeout.1551955736
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/44.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/44.clkmgr_idle_intersig_mubi.2258802029
Short name	T733
Test name
Test status
Simulation time	35002400 ps
CPU time	1.47 seconds
Started	Feb 09 08:28:40 AM UTC 25
Finished	Feb 09 08:28:43 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258802029 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_idle_intersig_mubi.2258802029
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/44.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.3216724011
Short name	T735
Test name
Test status
Simulation time	32645501 ps
CPU time	1.32 seconds
Started	Feb 09 08:28:41 AM UTC 25
Finished	Feb 09 08:28:44 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216724011 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_lc_clk_byp_req_intersig_mubi.3216724011
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.2328871206
Short name	T734
Test name
Test status
Simulation time	143331349 ps
CPU time	2 seconds
Started	Feb 09 08:28:40 AM UTC 25
Finished	Feb 09 08:28:43 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328871206 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_lc_ctrl_intersig_mubi.2328871206
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/44.clkmgr_peri.2697951212
Short name	T730
Test name
Test status
Simulation time	18491314 ps
CPU time	1.18 seconds
Started	Feb 09 08:28:37 AM UTC 25
Finished	Feb 09 08:28:39 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697951212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.2697951212
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/44.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/44.clkmgr_regwen.2789136028
Short name	T738
Test name
Test status
Simulation time	194793935 ps
CPU time	1.65 seconds
Started	Feb 09 08:28:45 AM UTC 25
Finished	Feb 09 08:28:47 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789136028 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.2789136028
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/44.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/44.clkmgr_smoke.162972469
Short name	T728
Test name
Test status
Simulation time	49941668 ps
CPU time	1.29 seconds
Started	Feb 09 08:28:34 AM UTC 25
Finished	Feb 09 08:28:36 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162972469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.162972469
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/44.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/44.clkmgr_stress_all.1047450017
Short name	T790
Test name
Test status
Simulation time	6366459848 ps
CPU time	60.52 seconds
Started	Feb 09 08:28:48 AM UTC 25
Finished	Feb 09 08:29:50 AM UTC 25
Peak memory	210808 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047450017 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all.1047450017
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/44.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/44.clkmgr_stress_all_with_rand_reset.3828490511
Short name	T844
Test name
Test status
Simulation time	47434673393 ps
CPU time	1052.28 seconds
Started	Feb 09 08:28:47 AM UTC 25
Finished	Feb 09 08:46:32 AM UTC 25
Peak memory	222200 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3828490511 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44. clkmgr_stress_all_with_rand_reset.3828490511
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/44.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/44.clkmgr_trans.356417047
Short name	T731
Test name
Test status
Simulation time	40908172 ps
CPU time	1.35 seconds
Started	Feb 09 08:28:37 AM UTC 25
Finished	Feb 09 08:28:40 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356417047 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.356417047
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/44.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/45.clkmgr_alert_test.2081179659
Short name	T757
Test name
Test status
Simulation time	21655875 ps
CPU time	1.17 seconds
Started	Feb 09 08:29:06 AM UTC 25
Finished	Feb 09 08:29:08 AM UTC 25
Peak memory	208888 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081179659 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_alert_test.2081179659
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/45.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.333165208
Short name	T752
Test name
Test status
Simulation time	26364603 ps
CPU time	1.38 seconds
Started	Feb 09 08:29:00 AM UTC 25
Finished	Feb 09 08:29:02 AM UTC 25
Peak memory	209852 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333165208 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_handshake_intersig_mubi.333165208
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/45.clkmgr_clk_status.3402379127
Short name	T748
Test name
Test status
Simulation time	17180096 ps
CPU time	1.08 seconds
Started	Feb 09 08:28:56 AM UTC 25
Finished	Feb 09 08:28:59 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402379127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.3402379127
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/45.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/45.clkmgr_div_intersig_mubi.3268707976
Short name	T753
Test name
Test status
Simulation time	24145932 ps
CPU time	1.18 seconds
Started	Feb 09 08:29:02 AM UTC 25
Finished	Feb 09 08:29:04 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268707976 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_div_intersig_mubi.3268707976
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/45.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/45.clkmgr_extclk.1150650099
Short name	T744
Test name
Test status
Simulation time	84524343 ps
CPU time	1.56 seconds
Started	Feb 09 08:28:50 AM UTC 25
Finished	Feb 09 08:28:53 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150650099 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.1150650099
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/45.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/45.clkmgr_frequency.3694213058
Short name	T754
Test name
Test status
Simulation time	1486891458 ps
CPU time	12.43 seconds
Started	Feb 09 08:28:51 AM UTC 25
Finished	Feb 09 08:29:05 AM UTC 25
Peak memory	210244 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694213058 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.3694213058
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/45.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/45.clkmgr_frequency_timeout.1520943960
Short name	T747
Test name
Test status
Simulation time	499618906 ps
CPU time	4.64 seconds
Started	Feb 09 08:28:52 AM UTC 25
Finished	Feb 09 08:28:58 AM UTC 25
Peak memory	210272 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520943960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_timeout.1520943960
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/45.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/45.clkmgr_idle_intersig_mubi.262762635
Short name	T749
Test name
Test status
Simulation time	87405512 ps
CPU time	1.68 seconds
Started	Feb 09 08:28:56 AM UTC 25
Finished	Feb 09 08:28:59 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262762635 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_idle_intersig_mubi.262762635
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/45.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.2210541713
Short name	T751
Test name
Test status
Simulation time	37870806 ps
CPU time	1.3 seconds
Started	Feb 09 08:29:00 AM UTC 25
Finished	Feb 09 08:29:02 AM UTC 25
Peak memory	209912 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210541713 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_lc_clk_byp_req_intersig_mubi.2210541713
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.4112103898
Short name	T750
Test name
Test status
Simulation time	102626963 ps
CPU time	1.74 seconds
Started	Feb 09 08:28:58 AM UTC 25
Finished	Feb 09 08:29:01 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112103898 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_lc_ctrl_intersig_mubi.4112103898
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/45.clkmgr_peri.1524914148
Short name	T745
Test name
Test status
Simulation time	27896175 ps
CPU time	1.12 seconds
Started	Feb 09 08:28:53 AM UTC 25
Finished	Feb 09 08:28:55 AM UTC 25
Peak memory	210088 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524914148 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.1524914148
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/45.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/45.clkmgr_regwen.3988269239
Short name	T759
Test name
Test status
Simulation time	1501507613 ps
CPU time	6.24 seconds
Started	Feb 09 08:29:03 AM UTC 25
Finished	Feb 09 08:29:10 AM UTC 25
Peak memory	210456 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988269239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.3988269239
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/45.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/45.clkmgr_smoke.914654723
Short name	T742
Test name
Test status
Simulation time	18403274 ps
CPU time	1.23 seconds
Started	Feb 09 08:28:49 AM UTC 25
Finished	Feb 09 08:28:51 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914654723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.914654723
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/45.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/45.clkmgr_stress_all.823342604
Short name	T768
Test name
Test status
Simulation time	2496968722 ps
CPU time	18.31 seconds
Started	Feb 09 08:29:05 AM UTC 25
Finished	Feb 09 08:29:25 AM UTC 25
Peak memory	210608 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823342604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all.823342604
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/45.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/45.clkmgr_stress_all_with_rand_reset.1573504451
Short name	T847
Test name
Test status
Simulation time	101054088964 ps
CPU time	1269.16 seconds
Started	Feb 09 08:29:03 AM UTC 25
Finished	Feb 09 08:50:27 AM UTC 25
Peak memory	226296 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1573504451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45. clkmgr_stress_all_with_rand_reset.1573504451
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/45.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/45.clkmgr_trans.267978799
Short name	T746
Test name
Test status
Simulation time	21809197 ps
CPU time	1.24 seconds
Started	Feb 09 08:28:53 AM UTC 25
Finished	Feb 09 08:28:55 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267978799 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.267978799
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/45.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/46.clkmgr_alert_test.1268930089
Short name	T773
Test name
Test status
Simulation time	25943927 ps
CPU time	1.14 seconds
Started	Feb 09 08:29:28 AM UTC 25
Finished	Feb 09 08:29:30 AM UTC 25
Peak memory	209916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268930089 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_alert_test.1268930089
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/46.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.2243851077
Short name	T770
Test name
Test status
Simulation time	35720208 ps
CPU time	1.33 seconds
Started	Feb 09 08:29:24 AM UTC 25
Finished	Feb 09 08:29:27 AM UTC 25
Peak memory	208672 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243851077 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_handshake_intersig_mubi.2243851077
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/46.clkmgr_clk_status.41850071
Short name	T763
Test name
Test status
Simulation time	24750565 ps
CPU time	1.12 seconds
Started	Feb 09 08:29:15 AM UTC 25
Finished	Feb 09 08:29:17 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41850071 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.41850071
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/46.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/46.clkmgr_div_intersig_mubi.1950590096
Short name	T771
Test name
Test status
Simulation time	155868099 ps
CPU time	1.88 seconds
Started	Feb 09 08:29:24 AM UTC 25
Finished	Feb 09 08:29:27 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950590096 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_div_intersig_mubi.1950590096
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/46.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/46.clkmgr_extclk.3697960535
Short name	T760
Test name
Test status
Simulation time	27740180 ps
CPU time	1.4 seconds
Started	Feb 09 08:29:08 AM UTC 25
Finished	Feb 09 08:29:11 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697960535 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.3697960535
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/46.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/46.clkmgr_frequency.1097567432
Short name	T767
Test name
Test status
Simulation time	677951014 ps
CPU time	10.72 seconds
Started	Feb 09 08:29:09 AM UTC 25
Finished	Feb 09 08:29:21 AM UTC 25
Peak memory	210432 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097567432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.1097567432
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/46.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/46.clkmgr_frequency_timeout.645981059
Short name	T772
Test name
Test status
Simulation time	2420619293 ps
CPU time	18.11 seconds
Started	Feb 09 08:29:10 AM UTC 25
Finished	Feb 09 08:29:30 AM UTC 25
Peak memory	210612 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645981059 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_timeout.645981059
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/46.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/46.clkmgr_idle_intersig_mubi.2641288652
Short name	T764
Test name
Test status
Simulation time	327995824 ps
CPU time	3.01 seconds
Started	Feb 09 08:29:16 AM UTC 25
Finished	Feb 09 08:29:20 AM UTC 25
Peak memory	210376 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641288652 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_idle_intersig_mubi.2641288652
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/46.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.3462632781
Short name	T769
Test name
Test status
Simulation time	30073505 ps
CPU time	1.14 seconds
Started	Feb 09 08:29:24 AM UTC 25
Finished	Feb 09 08:29:27 AM UTC 25
Peak memory	208652 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462632781 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_lc_clk_byp_req_intersig_mubi.3462632781
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.3006339179
Short name	T766
Test name
Test status
Simulation time	14185182 ps
CPU time	1.07 seconds
Started	Feb 09 08:29:18 AM UTC 25
Finished	Feb 09 08:29:20 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006339179 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_lc_ctrl_intersig_mubi.3006339179
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/46.clkmgr_peri.3639830310
Short name	T761
Test name
Test status
Simulation time	22690806 ps
CPU time	1.06 seconds
Started	Feb 09 08:29:11 AM UTC 25
Finished	Feb 09 08:29:13 AM UTC 25
Peak memory	210088 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639830310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.3639830310
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/46.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/46.clkmgr_regwen.569863457
Short name	T8
Test name
Test status
Simulation time	898851938 ps
CPU time	9.5 seconds
Started	Feb 09 08:29:24 AM UTC 25
Finished	Feb 09 08:29:35 AM UTC 25
Peak memory	210392 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569863457 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.569863457
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/46.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/46.clkmgr_smoke.484397882
Short name	T758
Test name
Test status
Simulation time	17839356 ps
CPU time	1.13 seconds
Started	Feb 09 08:29:07 AM UTC 25
Finished	Feb 09 08:29:09 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484397882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.484397882
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/46.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/46.clkmgr_stress_all.1138384767
Short name	T792
Test name
Test status
Simulation time	2873158830 ps
CPU time	26.69 seconds
Started	Feb 09 08:29:25 AM UTC 25
Finished	Feb 09 08:29:54 AM UTC 25
Peak memory	210716 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138384767 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all.1138384767
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/46.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/46.clkmgr_stress_all_with_rand_reset.3710645601
Short name	T185
Test name
Test status
Simulation time	40336365452 ps
CPU time	682.45 seconds
Started	Feb 09 08:29:24 AM UTC 25
Finished	Feb 09 08:40:55 AM UTC 25
Peak memory	227160 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=3710645601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46. clkmgr_stress_all_with_rand_reset.3710645601
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/46.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/46.clkmgr_trans.354009757
Short name	T762
Test name
Test status
Simulation time	83032146 ps
CPU time	1.73 seconds
Started	Feb 09 08:29:11 AM UTC 25
Finished	Feb 09 08:29:14 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354009757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.354009757
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/46.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/47.clkmgr_alert_test.42855691
Short name	T786
Test name
Test status
Simulation time	17291011 ps
CPU time	1.13 seconds
Started	Feb 09 08:29:43 AM UTC 25
Finished	Feb 09 08:29:45 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42855691 -assert nopostproc +UV M_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_alert_test.42855691
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/47.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.2372410425
Short name	T785
Test name
Test status
Simulation time	301825049 ps
CPU time	2.84 seconds
Started	Feb 09 08:29:38 AM UTC 25
Finished	Feb 09 08:29:42 AM UTC 25
Peak memory	210380 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372410425 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_handshake_intersig_mubi.2372410425
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/47.clkmgr_clk_status.1120230898
Short name	T778
Test name
Test status
Simulation time	15991240 ps
CPU time	1.12 seconds
Started	Feb 09 08:29:34 AM UTC 25
Finished	Feb 09 08:29:36 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120230898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.1120230898
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/47.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/47.clkmgr_div_intersig_mubi.228614572
Short name	T783
Test name
Test status
Simulation time	13926328 ps
CPU time	1.17 seconds
Started	Feb 09 08:29:38 AM UTC 25
Finished	Feb 09 08:29:41 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228614572 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_div_intersig_mubi.228614572
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/47.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/47.clkmgr_extclk.2372687153
Short name	T775
Test name
Test status
Simulation time	74142389 ps
CPU time	1.52 seconds
Started	Feb 09 08:29:29 AM UTC 25
Finished	Feb 09 08:29:32 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372687153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.2372687153
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/47.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/47.clkmgr_frequency.3550828810
Short name	T784
Test name
Test status
Simulation time	1303239610 ps
CPU time	10.15 seconds
Started	Feb 09 08:29:31 AM UTC 25
Finished	Feb 09 08:29:42 AM UTC 25
Peak memory	210432 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550828810 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.3550828810
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/47.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/47.clkmgr_frequency_timeout.1172243972
Short name	T779
Test name
Test status
Simulation time	630716865 ps
CPU time	4.92 seconds
Started	Feb 09 08:29:31 AM UTC 25
Finished	Feb 09 08:29:37 AM UTC 25
Peak memory	210272 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172243972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_timeout.1172243972
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/47.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/47.clkmgr_idle_intersig_mubi.176002132
Short name	T780
Test name
Test status
Simulation time	33250461 ps
CPU time	1.55 seconds
Started	Feb 09 08:29:35 AM UTC 25
Finished	Feb 09 08:29:38 AM UTC 25
Peak memory	209852 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176002132 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_idle_intersig_mubi.176002132
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/47.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.3135327934
Short name	T782
Test name
Test status
Simulation time	38560918 ps
CPU time	1.49 seconds
Started	Feb 09 08:29:37 AM UTC 25
Finished	Feb 09 08:29:40 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135327934 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_lc_clk_byp_req_intersig_mubi.3135327934
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.9885317
Short name	T781
Test name
Test status
Simulation time	38501500 ps
CPU time	1.29 seconds
Started	Feb 09 08:29:36 AM UTC 25
Finished	Feb 09 08:29:39 AM UTC 25
Peak memory	209916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9885317 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_lc_ctrl_intersig_mubi.9885317
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/47.clkmgr_peri.3403127789
Short name	T776
Test name
Test status
Simulation time	13628394 ps
CPU time	1.08 seconds
Started	Feb 09 08:29:31 AM UTC 25
Finished	Feb 09 08:29:33 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403127789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.3403127789
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/47.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/47.clkmgr_regwen.2472216874
Short name	T788
Test name
Test status
Simulation time	899953603 ps
CPU time	6.53 seconds
Started	Feb 09 08:29:40 AM UTC 25
Finished	Feb 09 08:29:47 AM UTC 25
Peak memory	210712 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472216874 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.2472216874
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/47.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/47.clkmgr_smoke.3830451798
Short name	T774
Test name
Test status
Simulation time	16576425 ps
CPU time	1.21 seconds
Started	Feb 09 08:29:28 AM UTC 25
Finished	Feb 09 08:29:30 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830451798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.3830451798
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/47.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/47.clkmgr_stress_all.3243270816
Short name	T806
Test name
Test status
Simulation time	4472564787 ps
CPU time	32.62 seconds
Started	Feb 09 08:29:42 AM UTC 25
Finished	Feb 09 08:30:16 AM UTC 25
Peak memory	210780 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243270816 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all.3243270816
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/47.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/47.clkmgr_stress_all_with_rand_reset.874591757
Short name	T181
Test name
Test status
Simulation time	52512601017 ps
CPU time	368.2 seconds
Started	Feb 09 08:29:41 AM UTC 25
Finished	Feb 09 08:35:54 AM UTC 25
Peak memory	220168 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=874591757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.c lkmgr_stress_all_with_rand_reset.874591757
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/47.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/47.clkmgr_trans.3041480139
Short name	T777
Test name
Test status
Simulation time	31743793 ps
CPU time	1.58 seconds
Started	Feb 09 08:29:32 AM UTC 25
Finished	Feb 09 08:29:35 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041480139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.3041480139
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/47.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/48.clkmgr_alert_test.3450638227
Short name	T801
Test name
Test status
Simulation time	17965477 ps
CPU time	1.19 seconds
Started	Feb 09 08:30:01 AM UTC 25
Finished	Feb 09 08:30:03 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450638227 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_alert_test.3450638227
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/48.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.1854383850
Short name	T799
Test name
Test status
Simulation time	40369878 ps
CPU time	1.4 seconds
Started	Feb 09 08:29:58 AM UTC 25
Finished	Feb 09 08:30:00 AM UTC 25
Peak memory	210036 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854383850 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_handshake_intersig_mubi.1854383850
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/48.clkmgr_clk_status.1546915389
Short name	T794
Test name
Test status
Simulation time	51330539 ps
CPU time	1.28 seconds
Started	Feb 09 08:29:52 AM UTC 25
Finished	Feb 09 08:29:55 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546915389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.1546915389
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/48.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/48.clkmgr_div_intersig_mubi.1117708441
Short name	T800
Test name
Test status
Simulation time	83388752 ps
CPU time	1.59 seconds
Started	Feb 09 08:29:58 AM UTC 25
Finished	Feb 09 08:30:01 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117708441 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_div_intersig_mubi.1117708441
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/48.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/48.clkmgr_extclk.3474391925
Short name	T789
Test name
Test status
Simulation time	15440409 ps
CPU time	1.21 seconds
Started	Feb 09 08:29:46 AM UTC 25
Finished	Feb 09 08:29:48 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474391925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.3474391925
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/48.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/48.clkmgr_frequency.383499405
Short name	T797
Test name
Test status
Simulation time	676938233 ps
CPU time	8.92 seconds
Started	Feb 09 08:29:47 AM UTC 25
Finished	Feb 09 08:29:57 AM UTC 25
Peak memory	210248 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383499405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.383499405
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/48.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/48.clkmgr_frequency_timeout.3873495825
Short name	T807
Test name
Test status
Simulation time	2056215498 ps
CPU time	26.33 seconds
Started	Feb 09 08:29:48 AM UTC 25
Finished	Feb 09 08:30:16 AM UTC 25
Peak memory	210476 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873495825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_timeout.3873495825
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/48.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/48.clkmgr_idle_intersig_mubi.618058543
Short name	T796
Test name
Test status
Simulation time	36632602 ps
CPU time	1.63 seconds
Started	Feb 09 08:29:54 AM UTC 25
Finished	Feb 09 08:29:57 AM UTC 25
Peak memory	209800 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618058543 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_idle_intersig_mubi.618058543
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/48.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.4007660268
Short name	T798
Test name
Test status
Simulation time	19058183 ps
CPU time	1.15 seconds
Started	Feb 09 08:29:55 AM UTC 25
Finished	Feb 09 08:29:58 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007660268 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_lc_clk_byp_req_intersig_mubi.4007660268
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.3493675608
Short name	T795
Test name
Test status
Simulation time	26886702 ps
CPU time	1.18 seconds
Started	Feb 09 08:29:54 AM UTC 25
Finished	Feb 09 08:29:57 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493675608 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_lc_ctrl_intersig_mubi.3493675608
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/48.clkmgr_peri.1091223485
Short name	T791
Test name
Test status
Simulation time	47454266 ps
CPU time	1.31 seconds
Started	Feb 09 08:29:49 AM UTC 25
Finished	Feb 09 08:29:52 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091223485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.1091223485
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/48.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/48.clkmgr_regwen.2239640084
Short name	T802
Test name
Test status
Simulation time	447843756 ps
CPU time	5.2 seconds
Started	Feb 09 08:29:59 AM UTC 25
Finished	Feb 09 08:30:05 AM UTC 25
Peak memory	210184 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239640084 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.2239640084
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/48.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/48.clkmgr_smoke.1214165547
Short name	T787
Test name
Test status
Simulation time	26770691 ps
CPU time	1.17 seconds
Started	Feb 09 08:29:44 AM UTC 25
Finished	Feb 09 08:29:46 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214165547 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.1214165547
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/48.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/48.clkmgr_stress_all.3987731009
Short name	T820
Test name
Test status
Simulation time	6169946757 ps
CPU time	49.3 seconds
Started	Feb 09 08:30:01 AM UTC 25
Finished	Feb 09 08:30:52 AM UTC 25
Peak memory	210432 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987731009 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all.3987731009
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/48.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/48.clkmgr_stress_all_with_rand_reset.2965900216
Short name	T180
Test name
Test status
Simulation time	18967964834 ps
CPU time	285.05 seconds
Started	Feb 09 08:29:59 AM UTC 25
Finished	Feb 09 08:34:48 AM UTC 25
Peak memory	220112 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2965900216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48. clkmgr_stress_all_with_rand_reset.2965900216
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/48.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/48.clkmgr_trans.1360490892
Short name	T793
Test name
Test status
Simulation time	51707231 ps
CPU time	1.22 seconds
Started	Feb 09 08:29:51 AM UTC 25
Finished	Feb 09 08:29:54 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360490892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.1360490892
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/48.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_alert_test.3327237400
Short name	T818
Test name
Test status
Simulation time	16912830 ps
CPU time	1.17 seconds
Started	Feb 09 08:30:27 AM UTC 25
Finished	Feb 09 08:30:30 AM UTC 25
Peak memory	209856 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327237400 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_alert_test.3327237400
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/49.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.3233153568
Short name	T816
Test name
Test status
Simulation time	78887732 ps
CPU time	1.63 seconds
Started	Feb 09 08:30:24 AM UTC 25
Finished	Feb 09 08:30:27 AM UTC 25
Peak memory	210036 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233153568 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_handshake_intersig_mubi.3233153568
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_clk_status.1685133210
Short name	T812
Test name
Test status
Simulation time	37048665 ps
CPU time	1.07 seconds
Started	Feb 09 08:30:24 AM UTC 25
Finished	Feb 09 08:30:26 AM UTC 25
Peak memory	208480 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685133210 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.1685133210
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/49.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_div_intersig_mubi.192045882
Short name	T814
Test name
Test status
Simulation time	55218461 ps
CPU time	1.42 seconds
Started	Feb 09 08:30:24 AM UTC 25
Finished	Feb 09 08:30:27 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192045882 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_div_intersig_mubi.192045882
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/49.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_extclk.2120500690
Short name	T804
Test name
Test status
Simulation time	113632503 ps
CPU time	1.67 seconds
Started	Feb 09 08:30:06 AM UTC 25
Finished	Feb 09 08:30:10 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120500690 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.2120500690
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/49.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_frequency.2923009490
Short name	T808
Test name
Test status
Simulation time	943205100 ps
CPU time	8.16 seconds
Started	Feb 09 08:30:07 AM UTC 25
Finished	Feb 09 08:30:17 AM UTC 25
Peak memory	210244 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923009490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.2923009490
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/49.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_frequency_timeout.1537368784
Short name	T811
Test name
Test status
Simulation time	1246814471 ps
CPU time	8.29 seconds
Started	Feb 09 08:30:10 AM UTC 25
Finished	Feb 09 08:30:20 AM UTC 25
Peak memory	210464 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537368784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_timeout.1537368784
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/49.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_idle_intersig_mubi.1614704948
Short name	T815
Test name
Test status
Simulation time	90382079 ps
CPU time	1.7 seconds
Started	Feb 09 08:30:24 AM UTC 25
Finished	Feb 09 08:30:27 AM UTC 25
Peak memory	209668 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614704948 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_idle_intersig_mubi.1614704948
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/49.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.3096586000
Short name	T817
Test name
Test status
Simulation time	81465184 ps
CPU time	1.76 seconds
Started	Feb 09 08:30:24 AM UTC 25
Finished	Feb 09 08:30:27 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096586000 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_lc_clk_byp_req_intersig_mubi.3096586000
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.356053113
Short name	T813
Test name
Test status
Simulation time	39351330 ps
CPU time	1.42 seconds
Started	Feb 09 08:30:24 AM UTC 25
Finished	Feb 09 08:30:27 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356053113 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_lc_ctrl_intersig_mubi.356053113
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_peri.1059780958
Short name	T805
Test name
Test status
Simulation time	166063551 ps
CPU time	2.1 seconds
Started	Feb 09 08:30:10 AM UTC 25
Finished	Feb 09 08:30:14 AM UTC 25
Peak memory	210176 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059780958 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.1059780958
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/49.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_regwen.937628925
Short name	T819
Test name
Test status
Simulation time	1495429194 ps
CPU time	11.76 seconds
Started	Feb 09 08:30:24 AM UTC 25
Finished	Feb 09 08:30:37 AM UTC 25
Peak memory	210580 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937628925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.937628925
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/49.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_smoke.2995933898
Short name	T803
Test name
Test status
Simulation time	15811503 ps
CPU time	1.15 seconds
Started	Feb 09 08:30:04 AM UTC 25
Finished	Feb 09 08:30:06 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995933898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.2995933898
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/49.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_stress_all.975055839
Short name	T825
Test name
Test status
Simulation time	8660002675 ps
CPU time	73.49 seconds
Started	Feb 09 08:30:27 AM UTC 25
Finished	Feb 09 08:31:43 AM UTC 25
Peak memory	210528 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975055839 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all.975055839
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/49.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_stress_all_with_rand_reset.556593733
Short name	T842
Test name
Test status
Simulation time	36303377553 ps
CPU time	735.85 seconds
Started	Feb 09 08:30:27 AM UTC 25
Finished	Feb 09 08:42:52 AM UTC 25
Peak memory	227036 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=556593733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.c lkmgr_stress_all_with_rand_reset.556593733
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/49.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/49.clkmgr_trans.2379841354
Short name	T810
Test name
Test status
Simulation time	20552566 ps
CPU time	1.26 seconds
Started	Feb 09 08:30:14 AM UTC 25
Finished	Feb 09 08:30:18 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379841354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.2379841354
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/49.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_alert_test.2255465496
Short name	T216
Test name
Test status
Simulation time	57896134 ps
CPU time	1.34 seconds
Started	Feb 09 08:17:28 AM UTC 25
Finished	Feb 09 08:17:32 AM UTC 25
Peak memory	209852 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255465496 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_alert_test.2255465496
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.3285285179
Short name	T114
Test name
Test status
Simulation time	84096928 ps
CPU time	1.68 seconds
Started	Feb 09 08:17:26 AM UTC 25
Finished	Feb 09 08:17:30 AM UTC 25
Peak memory	210036 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285285179 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_handshake_intersig_mubi.3285285179
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_clk_status.791706444
Short name	T192
Test name
Test status
Simulation time	194595472 ps
CPU time	2.05 seconds
Started	Feb 09 08:17:24 AM UTC 25
Finished	Feb 09 08:17:27 AM UTC 25
Peak memory	210136 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791706444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.791706444
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_div_intersig_mubi.1446481442
Short name	T215
Test name
Test status
Simulation time	36681420 ps
CPU time	1.38 seconds
Started	Feb 09 08:17:26 AM UTC 25
Finished	Feb 09 08:17:29 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446481442 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_div_intersig_mubi.1446481442
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_extclk.4050247690
Short name	T209
Test name
Test status
Simulation time	45141673 ps
CPU time	1.52 seconds
Started	Feb 09 08:17:18 AM UTC 25
Finished	Feb 09 08:17:21 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050247690 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.4050247690
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_frequency.137696033
Short name	T16
Test name
Test status
Simulation time	1045443065 ps
CPU time	11.01 seconds
Started	Feb 09 08:17:19 AM UTC 25
Finished	Feb 09 08:17:32 AM UTC 25
Peak memory	210244 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137696033 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.137696033
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_frequency_timeout.4178851528
Short name	T212
Test name
Test status
Simulation time	410195216 ps
CPU time	2.8 seconds
Started	Feb 09 08:17:21 AM UTC 25
Finished	Feb 09 08:17:25 AM UTC 25
Peak memory	210472 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178851528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_timeout.4178851528
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_idle_intersig_mubi.3028050728
Short name	T213
Test name
Test status
Simulation time	18812112 ps
CPU time	1.28 seconds
Started	Feb 09 08:17:24 AM UTC 25
Finished	Feb 09 08:17:27 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028050728 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_idle_intersig_mubi.3028050728
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.3860772526
Short name	T214
Test name
Test status
Simulation time	17939921 ps
CPU time	1.13 seconds
Started	Feb 09 08:17:25 AM UTC 25
Finished	Feb 09 08:17:28 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860772526 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_lc_clk_byp_req_intersig_mubi.3860772526
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.256564372
Short name	T169
Test name
Test status
Simulation time	323945314 ps
CPU time	2.61 seconds
Started	Feb 09 08:17:25 AM UTC 25
Finished	Feb 09 08:17:29 AM UTC 25
Peak memory	210180 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256564372 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_lc_ctrl_intersig_mubi.256564372
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_peri.3367583384
Short name	T210
Test name
Test status
Simulation time	70390424 ps
CPU time	1.39 seconds
Started	Feb 09 08:17:21 AM UTC 25
Finished	Feb 09 08:17:24 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367583384 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.3367583384
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_regwen.1855816567
Short name	T106
Test name
Test status
Simulation time	219690993 ps
CPU time	2.09 seconds
Started	Feb 09 08:17:27 AM UTC 25
Finished	Feb 09 08:17:31 AM UTC 25
Peak memory	210180 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855816567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.1855816567
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_smoke.3949763402
Short name	T207
Test name
Test status
Simulation time	16590479 ps
CPU time	1.1 seconds
Started	Feb 09 08:17:18 AM UTC 25
Finished	Feb 09 08:17:20 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949763402 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.3949763402
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_stress_all.2196680764
Short name	T155
Test name
Test status
Simulation time	18576131717 ps
CPU time	241.37 seconds
Started	Feb 09 08:17:28 AM UTC 25
Finished	Feb 09 08:21:34 AM UTC 25
Peak memory	210676 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196680764 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all.2196680764
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_stress_all_with_rand_reset.2756505350
Short name	T826
Test name
Test status
Simulation time	131399590807 ps
CPU time	853.26 seconds
Started	Feb 09 08:17:28 AM UTC 25
Finished	Feb 09 08:31:52 AM UTC 25
Peak memory	227220 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2756505350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.c lkmgr_stress_all_with_rand_reset.2756505350
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/5.clkmgr_trans.3551350468
Short name	T211
Test name
Test status
Simulation time	32302594 ps
CPU time	1.33 seconds
Started	Feb 09 08:17:21 AM UTC 25
Finished	Feb 09 08:17:24 AM UTC 25
Peak memory	209944 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551350468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.3551350468
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/5.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_alert_test.12048930
Short name	T226
Test name
Test status
Simulation time	54496560 ps
CPU time	1.35 seconds
Started	Feb 09 08:17:44 AM UTC 25
Finished	Feb 09 08:17:47 AM UTC 25
Peak memory	209796 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12048930 -assert nopostproc +UV M_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_alert_test.12048930
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.3003349334
Short name	T115
Test name
Test status
Simulation time	41889986 ps
CPU time	1.44 seconds
Started	Feb 09 08:17:41 AM UTC 25
Finished	Feb 09 08:17:44 AM UTC 25
Peak memory	210036 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003349334 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_handshake_intersig_mubi.3003349334
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_clk_status.3657273914
Short name	T193
Test name
Test status
Simulation time	27192147 ps
CPU time	1.06 seconds
Started	Feb 09 08:17:41 AM UTC 25
Finished	Feb 09 08:17:43 AM UTC 25
Peak memory	208816 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657273914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.3657273914
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_div_intersig_mubi.465641758
Short name	T204
Test name
Test status
Simulation time	22795998 ps
CPU time	1.44 seconds
Started	Feb 09 08:17:44 AM UTC 25
Finished	Feb 09 08:17:47 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465641758 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_div_intersig_mubi.465641758
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_extclk.376847207
Short name	T218
Test name
Test status
Simulation time	23699475 ps
CPU time	1.28 seconds
Started	Feb 09 08:17:31 AM UTC 25
Finished	Feb 09 08:17:33 AM UTC 25
Peak memory	209852 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376847207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.376847207
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_frequency.3191107079
Short name	T17
Test name
Test status
Simulation time	1018815032 ps
CPU time	7.52 seconds
Started	Feb 09 08:17:31 AM UTC 25
Finished	Feb 09 08:17:40 AM UTC 25
Peak memory	210436 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191107079 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.3191107079
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_frequency_timeout.228174089
Short name	T224
Test name
Test status
Simulation time	147016779 ps
CPU time	2.18 seconds
Started	Feb 09 08:17:41 AM UTC 25
Finished	Feb 09 08:17:44 AM UTC 25
Peak memory	210280 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228174089 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_timeout.228174089
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_idle_intersig_mubi.516367688
Short name	T220
Test name
Test status
Simulation time	17622826 ps
CPU time	1.07 seconds
Started	Feb 09 08:17:41 AM UTC 25
Finished	Feb 09 08:17:43 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516367688 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_idle_intersig_mubi.516367688
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.3575651861
Short name	T222
Test name
Test status
Simulation time	15401499 ps
CPU time	1.16 seconds
Started	Feb 09 08:17:41 AM UTC 25
Finished	Feb 09 08:17:43 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575651861 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_lc_clk_byp_req_intersig_mubi.3575651861
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.2514807186
Short name	T221
Test name
Test status
Simulation time	15645243 ps
CPU time	1.18 seconds
Started	Feb 09 08:17:41 AM UTC 25
Finished	Feb 09 08:17:43 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514807186 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_lc_ctrl_intersig_mubi.2514807186
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_peri.2534988528
Short name	T219
Test name
Test status
Simulation time	17150348 ps
CPU time	1.17 seconds
Started	Feb 09 08:17:41 AM UTC 25
Finished	Feb 09 08:17:43 AM UTC 25
Peak memory	210088 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534988528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.2534988528
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_regwen.2870781307
Short name	T230
Test name
Test status
Simulation time	487578238 ps
CPU time	6.25 seconds
Started	Feb 09 08:17:44 AM UTC 25
Finished	Feb 09 08:17:52 AM UTC 25
Peak memory	210308 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870781307 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.2870781307
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_smoke.274070403
Short name	T217
Test name
Test status
Simulation time	16035071 ps
CPU time	1.1 seconds
Started	Feb 09 08:17:30 AM UTC 25
Finished	Feb 09 08:17:32 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274070403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.274070403
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_stress_all.1419853547
Short name	T36
Test name
Test status
Simulation time	3175809490 ps
CPU time	25.56 seconds
Started	Feb 09 08:17:44 AM UTC 25
Finished	Feb 09 08:18:11 AM UTC 25
Peak memory	210688 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419853547 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all.1419853547
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_stress_all_with_rand_reset.311409921
Short name	T89
Test name
Test status
Simulation time	28458999662 ps
CPU time	504.97 seconds
Started	Feb 09 08:17:44 AM UTC 25
Finished	Feb 09 08:26:15 AM UTC 25
Peak memory	227052 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=311409921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.cl kmgr_stress_all_with_rand_reset.311409921
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/6.clkmgr_trans.3860344618
Short name	T223
Test name
Test status
Simulation time	23344766 ps
CPU time	1.39 seconds
Started	Feb 09 08:17:41 AM UTC 25
Finished	Feb 09 08:17:43 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860344618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.3860344618
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/6.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_alert_test.2382330862
Short name	T233
Test name
Test status
Simulation time	18457826 ps
CPU time	1.28 seconds
Started	Feb 09 08:17:54 AM UTC 25
Finished	Feb 09 08:17:57 AM UTC 25
Peak memory	208824 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382330862 -assert nopostproc + UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_alert_test.2382330862
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.923399402
Short name	T116
Test name
Test status
Simulation time	71341969 ps
CPU time	1.61 seconds
Started	Feb 09 08:17:51 AM UTC 25
Finished	Feb 09 08:17:54 AM UTC 25
Peak memory	209972 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923399402 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_handshake_intersig_mubi.923399402
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_clk_status.4096722475
Short name	T194
Test name
Test status
Simulation time	50390526 ps
CPU time	1.21 seconds
Started	Feb 09 08:17:48 AM UTC 25
Finished	Feb 09 08:17:50 AM UTC 25
Peak memory	210028 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096722475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.4096722475
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_div_intersig_mubi.3200375740
Short name	T232
Test name
Test status
Simulation time	16830283 ps
CPU time	1.16 seconds
Started	Feb 09 08:17:52 AM UTC 25
Finished	Feb 09 08:17:55 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200375740 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_div_intersig_mubi.3200375740
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_extclk.3817489505
Short name	T227
Test name
Test status
Simulation time	24711757 ps
CPU time	1.42 seconds
Started	Feb 09 08:17:44 AM UTC 25
Finished	Feb 09 08:17:47 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817489505 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.3817489505
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_frequency.148964336
Short name	T41
Test name
Test status
Simulation time	799400576 ps
CPU time	11.77 seconds
Started	Feb 09 08:17:45 AM UTC 25
Finished	Feb 09 08:17:59 AM UTC 25
Peak memory	210372 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148964336 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.148964336
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_frequency_timeout.3631618701
Short name	T239
Test name
Test status
Simulation time	2429357023 ps
CPU time	20.85 seconds
Started	Feb 09 08:17:48 AM UTC 25
Finished	Feb 09 08:18:10 AM UTC 25
Peak memory	210672 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631618701 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_timeout.3631618701
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_idle_intersig_mubi.3379817857
Short name	T231
Test name
Test status
Simulation time	161484471 ps
CPU time	2.19 seconds
Started	Feb 09 08:17:49 AM UTC 25
Finished	Feb 09 08:17:52 AM UTC 25
Peak memory	210184 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379817857 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_idle_intersig_mubi.3379817857
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.198603720
Short name	T170
Test name
Test status
Simulation time	17471848 ps
CPU time	1.14 seconds
Started	Feb 09 08:17:51 AM UTC 25
Finished	Feb 09 08:17:53 AM UTC 25
Peak memory	210036 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198603720 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_lc_clk_byp_req_intersig_mubi.198603720
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.3031431883
Short name	T171
Test name
Test status
Simulation time	13122700 ps
CPU time	1.14 seconds
Started	Feb 09 08:17:51 AM UTC 25
Finished	Feb 09 08:17:53 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031431883 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_lc_ctrl_intersig_mubi.3031431883
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_peri.1415541255
Short name	T228
Test name
Test status
Simulation time	30010498 ps
CPU time	1.23 seconds
Started	Feb 09 08:17:48 AM UTC 25
Finished	Feb 09 08:17:50 AM UTC 25
Peak memory	210096 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415541255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.1415541255
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_regwen.4121976036
Short name	T172
Test name
Test status
Simulation time	1448516553 ps
CPU time	10.92 seconds
Started	Feb 09 08:17:53 AM UTC 25
Finished	Feb 09 08:18:05 AM UTC 25
Peak memory	210684 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121976036 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.4121976036
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_smoke.2282205983
Short name	T225
Test name
Test status
Simulation time	14368809 ps
CPU time	1.09 seconds
Started	Feb 09 08:17:44 AM UTC 25
Finished	Feb 09 08:17:47 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282205983 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.2282205983
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_stress_all.4218065790
Short name	T234
Test name
Test status
Simulation time	190149173 ps
CPU time	2.68 seconds
Started	Feb 09 08:17:54 AM UTC 25
Finished	Feb 09 08:17:58 AM UTC 25
Peak memory	210376 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218065790 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all.4218065790
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_stress_all_with_rand_reset.1998567698
Short name	T755
Test name
Test status
Simulation time	40541779075 ps
CPU time	663.83 seconds
Started	Feb 09 08:17:54 AM UTC 25
Finished	Feb 09 08:29:06 AM UTC 25
Peak memory	220208 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=1998567698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.c lkmgr_stress_all_with_rand_reset.1998567698
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/7.clkmgr_trans.2621092766
Short name	T229
Test name
Test status
Simulation time	40535203 ps
CPU time	1.7 seconds
Started	Feb 09 08:17:48 AM UTC 25
Finished	Feb 09 08:17:51 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621092766 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.2621092766
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/7.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_alert_test.664511054
Short name	T242
Test name
Test status
Simulation time	21778193 ps
CPU time	1.19 seconds
Started	Feb 09 08:18:11 AM UTC 25
Finished	Feb 09 08:18:13 AM UTC 25
Peak memory	209916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664511054 -assert nopostproc +U VM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_alert_test.664511054
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.3618432889
Short name	T240
Test name
Test status
Simulation time	77705553 ps
CPU time	1.63 seconds
Started	Feb 09 08:18:07 AM UTC 25
Finished	Feb 09 08:18:10 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618432889 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_handshake_intersig_mubi.3618432889
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_clk_status.31691892
Short name	T195
Test name
Test status
Simulation time	35488317 ps
CPU time	1.06 seconds
Started	Feb 09 08:18:03 AM UTC 25
Finished	Feb 09 08:18:05 AM UTC 25
Peak memory	208824 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31691892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.31691892
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_div_intersig_mubi.262177547
Short name	T241
Test name
Test status
Simulation time	19662226 ps
CPU time	1.2 seconds
Started	Feb 09 08:18:10 AM UTC 25
Finished	Feb 09 08:18:12 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262177547 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_div_intersig_mubi.262177547
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_extclk.3853021053
Short name	T202
Test name
Test status
Simulation time	15636824 ps
CPU time	1.17 seconds
Started	Feb 09 08:17:58 AM UTC 25
Finished	Feb 09 08:18:00 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853021053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.3853021053
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_frequency.1346002164
Short name	T37
Test name
Test status
Simulation time	1162465399 ps
CPU time	18.11 seconds
Started	Feb 09 08:17:59 AM UTC 25
Finished	Feb 09 08:18:18 AM UTC 25
Peak memory	210132 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346002164 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.1346002164
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_frequency_timeout.1772951258
Short name	T251
Test name
Test status
Simulation time	1940386489 ps
CPU time	23.35 seconds
Started	Feb 09 08:17:59 AM UTC 25
Finished	Feb 09 08:18:24 AM UTC 25
Peak memory	210280 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772951258 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_timeout.1772951258
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_idle_intersig_mubi.242650912
Short name	T237
Test name
Test status
Simulation time	78339398 ps
CPU time	1.67 seconds
Started	Feb 09 08:18:04 AM UTC 25
Finished	Feb 09 08:18:07 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242650912 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_idle_intersig_mubi.242650912
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.366627537
Short name	T238
Test name
Test status
Simulation time	101226633 ps
CPU time	1.78 seconds
Started	Feb 09 08:18:06 AM UTC 25
Finished	Feb 09 08:18:09 AM UTC 25
Peak memory	210036 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366627537 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_lc_clk_byp_req_intersig_mubi.366627537
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.1324792625
Short name	T173
Test name
Test status
Simulation time	22826029 ps
CPU time	1.21 seconds
Started	Feb 09 08:18:06 AM UTC 25
Finished	Feb 09 08:18:09 AM UTC 25
Peak memory	209968 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324792625 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_lc_ctrl_intersig_mubi.1324792625
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_peri.821890168
Short name	T235
Test name
Test status
Simulation time	38683516 ps
CPU time	1.18 seconds
Started	Feb 09 08:18:00 AM UTC 25
Finished	Feb 09 08:18:02 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821890168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.821890168
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_regwen.231177417
Short name	T246
Test name
Test status
Simulation time	1183649094 ps
CPU time	7.44 seconds
Started	Feb 09 08:18:10 AM UTC 25
Finished	Feb 09 08:18:18 AM UTC 25
Peak memory	209708 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231177417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.231177417
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_smoke.3022619145
Short name	T151
Test name
Test status
Simulation time	30441893 ps
CPU time	1.21 seconds
Started	Feb 09 08:17:56 AM UTC 25
Finished	Feb 09 08:17:58 AM UTC 25
Peak memory	208820 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022619145 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.3022619145
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_stress_all.2738412401
Short name	T243
Test name
Test status
Simulation time	50596643 ps
CPU time	1.6 seconds
Started	Feb 09 08:18:11 AM UTC 25
Finished	Feb 09 08:18:14 AM UTC 25
Peak memory	209852 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738412401 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all.2738412401
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_stress_all_with_rand_reset.2559907462
Short name	T809
Test name
Test status
Simulation time	53145656780 ps
CPU time	718.83 seconds
Started	Feb 09 08:18:10 AM UTC 25
Finished	Feb 09 08:30:17 AM UTC 25
Peak memory	227156 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=2559907462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.c lkmgr_stress_all_with_rand_reset.2559907462
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/8.clkmgr_trans.308100764
Short name	T236
Test name
Test status
Simulation time	54820003 ps
CPU time	1.36 seconds
Started	Feb 09 08:18:01 AM UTC 25
Finished	Feb 09 08:18:03 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308100764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.308100764
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/8.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_alert_test.543439460
Short name	T254
Test name
Test status
Simulation time	51401178 ps
CPU time	1.21 seconds
Started	Feb 09 08:18:25 AM UTC 25
Finished	Feb 09 08:18:27 AM UTC 25
Peak memory	209916 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543439460 -assert nopostproc +U VM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_alert_test.543439460
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.4076813859
Short name	T252
Test name
Test status
Simulation time	46107955 ps
CPU time	1.29 seconds
Started	Feb 09 08:18:22 AM UTC 25
Finished	Feb 09 08:18:24 AM UTC 25
Peak memory	209976 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076813859 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_handshake_intersig_mubi.4076813859
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_clk_status.121693833
Short name	T196
Test name
Test status
Simulation time	14824656 ps
CPU time	1.1 seconds
Started	Feb 09 08:18:18 AM UTC 25
Finished	Feb 09 08:18:21 AM UTC 25
Peak memory	208824 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121693833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.121693833
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_div_intersig_mubi.531720434
Short name	T253
Test name
Test status
Simulation time	35707087 ps
CPU time	1.22 seconds
Started	Feb 09 08:18:23 AM UTC 25
Finished	Feb 09 08:18:25 AM UTC 25
Peak memory	210032 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531720434 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_div_intersig_mubi.531720434
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_extclk.3510086553
Short name	T244
Test name
Test status
Simulation time	69672815 ps
CPU time	1.68 seconds
Started	Feb 09 08:18:13 AM UTC 25
Finished	Feb 09 08:18:16 AM UTC 25
Peak memory	209848 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510086553 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.3510086553
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_frequency.2684650466
Short name	T38
Test name
Test status
Simulation time	2525290700 ps
CPU time	10.96 seconds
Started	Feb 09 08:18:14 AM UTC 25
Finished	Feb 09 08:18:26 AM UTC 25
Peak memory	210688 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684650466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.2684650466
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_frequency_timeout.1209430929
Short name	T265
Test name
Test status
Simulation time	2415511563 ps
CPU time	25.55 seconds
Started	Feb 09 08:18:14 AM UTC 25
Finished	Feb 09 08:18:41 AM UTC 25
Peak memory	210620 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209430929 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_timeout.1209430929
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_idle_intersig_mubi.1053439524
Short name	T248
Test name
Test status
Simulation time	92462647 ps
CPU time	1.2 seconds
Started	Feb 09 08:18:19 AM UTC 25
Finished	Feb 09 08:18:22 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053439524 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_idle_intersig_mubi.1053439524
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.2381444207
Short name	T250
Test name
Test status
Simulation time	38434931 ps
CPU time	1.03 seconds
Started	Feb 09 08:18:21 AM UTC 25
Finished	Feb 09 08:18:23 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381444207 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_lc_clk_byp_req_intersig_mubi.2381444207
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.825220966
Short name	T249
Test name
Test status
Simulation time	63854643 ps
CPU time	1.58 seconds
Started	Feb 09 08:18:20 AM UTC 25
Finished	Feb 09 08:18:22 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825220966 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_lc_ctrl_intersig_mubi.825220966
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_peri.3635582194
Short name	T245
Test name
Test status
Simulation time	43709220 ps
CPU time	1.25 seconds
Started	Feb 09 08:18:15 AM UTC 25
Finished	Feb 09 08:18:18 AM UTC 25
Peak memory	210096 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635582194 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.3635582194
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_regwen.2358565884
Short name	T255
Test name
Test status
Simulation time	870668345 ps
CPU time	4.63 seconds
Started	Feb 09 08:18:23 AM UTC 25
Finished	Feb 09 08:18:29 AM UTC 25
Peak memory	210492 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358565884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.2358565884
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_smoke.913450827
Short name	T152
Test name
Test status
Simulation time	52651914 ps
CPU time	1.23 seconds
Started	Feb 09 08:18:12 AM UTC 25
Finished	Feb 09 08:18:14 AM UTC 25
Peak memory	209788 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913450827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.913450827
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_stress_all.3852095272
Short name	T42
Test name
Test status
Simulation time	2998563713 ps
CPU time	23.01 seconds
Started	Feb 09 08:18:25 AM UTC 25
Finished	Feb 09 08:18:49 AM UTC 25
Peak memory	210648 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852095272 -assert nopostpro c +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all.3852095272
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_stress_all_with_rand_reset.4034333387
Short name	T823
Test name
Test status
Simulation time	145757279440 ps
CPU time	770.86 seconds
Started	Feb 09 08:18:24 AM UTC 25
Finished	Feb 09 08:31:23 AM UTC 25
Peak memory	220364 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_str ess_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/rep o/hw/dv/tools/sim.tcl +ntb_random_seed=4034333387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.c lkmgr_stress_all_with_rand_reset.4034333387
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/coverage/default/9.clkmgr_trans.2355109712
Short name	T247
Test name
Test status
Simulation time	66518328 ps
CPU time	1.43 seconds
Started	Feb 09 08:18:17 AM UTC 25
Finished	Feb 09 08:18:20 AM UTC 25
Peak memory	209908 kb
Host	ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355109712 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t est +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.2355109712
Directory	/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/9.clkmgr_trans/latest

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%