FLASH_CTRL Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: `349bab6601`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.879m	704.131us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	25.960s	43.934us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.570s	28.616us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.050s	136.632us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.425m	6.551ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.099m	2.577ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.780s	2.047ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.050s	136.632us	20	20	100.00
		flash_ctrl_csr_aliasing	1.099m	2.577ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.440s	45.572us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.670s	54.418us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.820s	49.547us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.015m	83.665us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	37.776m	143.680ms	3	3	100.00
		flash_ctrl_hw_rma_reset	16.340m	160.170ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.820s	46.376us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	47.497m	274.336ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.481m	11.193ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.462m	3.644ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	54.289m	372.528ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.335m	1.436ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.430s	51.696us	28	40	70.00
		flash_ctrl_rw_evict_all_en	32.810s	32.897us	35	40	87.50
		flash_ctrl_re_evict	38.640s	268.209us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.821m	2.043ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.821m	2.043ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	19.461m	31.298ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	29.790s	574.287us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	23.532m	763.694us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	43.944m	5.911ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.766m	1.042ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	47.073m	1.290ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.960s	25.532us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.397m	2.417ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	23.300s	15.429us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.460s	54.728us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	30.122m	284.796us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	3.772m	5.239ms	50	50	100.00
		flash_ctrl_otp_reset	2.254m	154.720us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	37.776m	143.680ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.426m	21.536ms	38	40	95.00
		flash_ctrl_intr_wr	1.447m	3.069ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	5.971m	50.288ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	4.004m	195.386ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.606m	1.011ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.247m	1.895ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.910s	34.086us	4	5	80.00
		flash_ctrl_ro_derr	2.731m	2.796ms	10	10	100.00
		flash_ctrl_rw_derr	12.542m	4.624ms	9	10	90.00
		flash_ctrl_derr_detect	1.782m	132.028us	5	5	100.00
		flash_ctrl_integrity	12.230m	7.702ms	3	5	60.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.780s	29.534us	4	5	80.00
		flash_ctrl_ro_serr	2.487m	701.162us	10	10	100.00
		flash_ctrl_rw_serr	11.383m	11.880ms	8	10	80.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.722m	4.108ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.520m	2.194ms	4	5	80.00
V2	scramble	flash_ctrl_wo	4.142m	8.287ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.250s	75.977us	1	1	100.00
		flash_ctrl_read_word_sweep	13.880s	23.430us	1	1	100.00
		flash_ctrl_ro	2.202m	557.582us	19	20	95.00
		flash_ctrl_rw	11.057m	11.361ms	18	20	90.00
V2	filesystem_support	flash_ctrl_fs_sup	43.870s	736.962us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.437m	235.405ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.451m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.520s	141.428us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.810s	56.352us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.750s	702.229us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.750s	702.229us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.570s	28.616us	5	5	100.00
		flash_ctrl_csr_rw	18.050s	136.632us	20	20	100.00
		flash_ctrl_csr_aliasing	1.099m	2.577ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.510s	126.235us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.570s	28.616us	5	5	100.00
		flash_ctrl_csr_rw	18.050s	136.632us	20	20	100.00
		flash_ctrl_csr_aliasing	1.099m	2.577ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.510s	126.235us	20	20	100.00
V2		TOTAL			983	1013	97.04
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	15.840s	42.437us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	15.840s	42.437us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	15.840s	42.437us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	15.840s	42.437us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	15.820s	14.936us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.367h	2.242ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.189m	904.315us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.189m	904.315us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.189m	904.315us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.360s	123.234us	3	3	100.00
		flash_ctrl_wr_intg	15.090s	47.497us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.879m	704.131us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.254m	154.720us	80	80	100.00
		flash_ctrl_disable	23.300s	15.429us	50	50	100.00
		flash_ctrl_sec_info_access	1.515m	23.592ms	50	50	100.00
		flash_ctrl_connect	16.460s	54.728us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.690s	70.107us	1	5	20.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.050s	136.632us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.840s	42.437us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.050s	136.632us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.840s	42.437us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.050s	136.632us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	15.840s	42.437us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	23.300s	15.429us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.360s	123.234us	3	3	100.00
		flash_ctrl_access_after_disable	13.980s	42.361us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	23.300s	15.429us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	29.790s	574.287us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.057m	11.361ms	18	20	90.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	11.383m	11.880ms	8	10	80.00
		flash_ctrl_rw_derr	12.542m	4.624ms	9	10	90.00
		flash_ctrl_integrity	12.230m	7.702ms	3	5	60.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	37.776m	143.680ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.367h	2.242ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.367h	2.242ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.367h	2.242ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.367h	2.242ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	22.350s	666.320us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.670s	18.494us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.410s	15.608us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.367h	2.242ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.367h	2.242ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.367h	2.242ms	5	5	100.00
V2S		TOTAL			140	144	97.22
V3	asymmetric_read_path	flash_ctrl_rd_ooo	44.760s	52.551us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1244	1278	97.34

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	44	80.00
V2S	12	12	11	91.67
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.53	95.85	94.23	98.85	92.52	98.27	98.00	98.03

Failure Buckets

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 17 failures:

Test flash_ctrl_rw_evict has 12 failures.

3.flash_ctrl_rw_evict.93745396620658221820084227245982797027084319881724883900205256478347765433184
Line 292, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 82216.9 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00079420
  UVM_INFO @ 82216.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.flash_ctrl_rw_evict.48162387647389022987772242159677133533639419369465696060108204481646487071004
Line 292, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 58019.2 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00002888
  UVM_INFO @ 58019.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

Test flash_ctrl_rw_evict_all_en has 5 failures.

3.flash_ctrl_rw_evict_all_en.54732307552444564786418759343119593788175882885853239494569075863065711127515
Line 288, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 12164.4 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000ab618
  UVM_INFO @ 12164.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.flash_ctrl_rw_evict_all_en.36124314787586535831435141752937768385886564087534730556871850671442684851594
Line 292, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 94787.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000cd708
  UVM_INFO @ 94787.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Error-[CNST-CIF] Constraints inconsistency failure has 4 failures:
- Test flash_ctrl_config_regwen has 4 failures.
  - 0.flash_ctrl_config_regwen.76450432130724137096094968029974810620655294618826108128549316712078765740700
    Line 328, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_config_regwen/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_flash_ctrl_env_0.1/seq_lib/flash_ctrl_config_regwen_vseq.sv, 46
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 1.flash_ctrl_config_regwen.91945304232361062612914329578115456716926112123006674953081601188408326367921
    Line 328, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_config_regwen/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_flash_ctrl_env_0.1/seq_lib/flash_ctrl_config_regwen_vseq.sv, 46
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 2 more failures.

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 3 failures:

Test flash_ctrl_ro has 1 failures.

4.flash_ctrl_ro.61615880808197821181496012740945584869013783525853826928984872689051982753175
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_ro/latest/run.log

  UVM_ERROR @ 50841.7 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 50841.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_serr_address has 1 failures.

4.flash_ctrl_serr_address.28302116752233862742236166681825084750980473093571656644490934659215683135738
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_serr_address/latest/run.log

  UVM_ERROR @ 95542.9 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 95542.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw has 1 failures.

13.flash_ctrl_rw.27770641760445580022472692367021843667541144126864989753479242169398050371936
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_rw/latest/run.log

  UVM_ERROR @ 433128.6 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 433128.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 2 failures:
- Test flash_ctrl_read_word_sweep_derr has 1 failures.
  - 3.flash_ctrl_read_word_sweep_derr.52981259379998261768130720043279769049645204613247811264910384646897048622133
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_derr/latest/run.log
```
  UVM_ERROR @ 10798.7 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x0001ccc0
  UVM_INFO @ 10798.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_integrity has 1 failures.
  - 4.flash_ctrl_integrity.70908080599488886705078350631487299143348144535071131856362181913187015093432
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 1110168.0 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00000408
  UVM_INFO @ 1110168.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 2 failures:

Test flash_ctrl_rw_serr has 2 failures.

6.flash_ctrl_rw_serr.100103680667592498007010194175500141216313469635226571261328531806276065153833
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 6612954.5 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (647403848469993390180 [0x231888821742c68064] vs 647403883654365479012 [0x231888a21742c68064])
  UVM_INFO @ 6612954.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.flash_ctrl_rw_serr.69789393169617753031962588404944680089569691169126456161738762764428134773284
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 11880334.3 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (1366150354782697095238 [0x4a0f250d8004890046] vs 1366150345986604073030 [0x4a0f25058004890046])
  UVM_INFO @ 11880334.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:362) [flash_ctrl_rw_vseq] Check failed (*) Too many unsuccessful attempts to create a prog_op has 1 failures:
- Test flash_ctrl_integrity has 1 failures.
  - 0.flash_ctrl_integrity.568179477442843638373639451261952778456704955931239402265467786023855670809
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log
```
  UVM_ERROR @ 3173948.6 ns: (flash_ctrl_otf_base_vseq.sv:362) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (0) Too many unsuccessful attempts to create a prog_op
  UVM_INFO @ 3173948.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 1 failures:
- Test flash_ctrl_rw has 1 failures.
  - 1.flash_ctrl_rw.114907655451109942753377139700948466472083318397067838614578802158353648834927
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:61e6a94a-129e-45b7-b2d6-a9d501de6fd2
```
UVM_ERROR (flash_otf_item.sv:247) [rd_scr] ecc error is detected has 1 failures:
- Test flash_ctrl_read_word_sweep_serr has 1 failures.
  - 2.flash_ctrl_read_word_sweep_serr.29327175284483688756501409773168926539084963336351399743233251495778419497741
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_serr/latest/run.log
```
  UVM_ERROR @ 5103.2 ns: (flash_otf_item.sv:247) [rd_scr] ecc error is detected
  UVM_INFO @ 5103.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_rw_derr has 1 failures.
  - 2.flash_ctrl_rw_derr.68769640504183116861850564473606394784372378526283602293831820399471987030121
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 9154961.2 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (26013517948492655494848 [0x58232150ca1090206c0] vs 26013513444893028124352 [0x58232050ca1090206c0])
  UVM_INFO @ 9154961.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp d6ffaa30_4963a78f:ffffffff_4963a78f mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 3.flash_ctrl_intr_rd.58081476858636256867079653479824813794515579386108715993264287362646391961549
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 2589719.2 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    0: obs:exp    d6ffaa30_4963a78f:ffffffff_4963a78f  mismatch!!
  UVM_INFO @ 2589719.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp ab2447d7_9d9d21de:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 23.flash_ctrl_intr_rd.97428282989468423900715590693637339599579657825307269188448715498537033684899
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1504056.4 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    5: obs:exp    ab2447d7_9d9d21de:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 1504056.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```