Unified Coverage Report :: Module :: flash_phy_rd

Module : flash_phy_rd

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.81	100.00	91.25			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd	97.48	100.00	89.93			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd	97.70	100.00	90.81			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.48	100.00	89.93			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.13	97.64	92.74	100.00		98.73	96.55

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.68	100.00	90.57		100.00	97.83	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_rd.gen_bus_words_intg[0].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[0].u_prim_buf_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_prim_buf_intg	100.00	100.00
u_addr_xor_storage	96.53	100.00	86.11			100.00	100.00
u_bus_inv_data_intg	0.00	0.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_prim_buf_data_xor_out	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	93.90	100.00	79.49	100.00		90.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	94.17	92.31	97.69			100.00	86.67

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.70	100.00	90.81			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.20	97.64	93.07	100.00		98.73	96.55

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.55	100.00	84.91		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_rd.gen_bus_words_intg[0].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[0].u_prim_buf_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_prim_buf_intg	100.00	100.00
u_addr_xor_storage	96.53	100.00	86.11			100.00	100.00
u_bus_inv_data_intg	0.00	0.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_prim_buf_data_xor_out	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	93.90	100.00	79.49	100.00		90.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	94.17	92.31	97.69			100.00	86.67

Line Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
ALWAYS	258	4	4	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	327	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
ALWAYS	361	12	12	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	443	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	452	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	506	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	600	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
ALWAYS	603	6	6	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	620	1	1	100.00
CONT_ASSIGN	627	1	1	100.00
CONT_ASSIGN	631	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	662	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
ALWAYS	673	8	8	100.00
CONT_ASSIGN	686	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	727	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	764	1	1	100.00
CONT_ASSIGN	777	1	1	100.00
CONT_ASSIGN	789	1	1	100.00
CONT_ASSIGN	792	1	1	100.00
CONT_ASSIGN	796	1	1	100.00
CONT_ASSIGN	799	1	1	100.00
CONT_ASSIGN	802	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
141	4	4
142	4	4
147	4	4
153	1	1
155	3	3
187	1	1
194	4	4
195	4	4
197	4	4
213	4	4
219	4	4
223	4	4
230	1	1
233	1	1
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
292	1	1
293	1	1
303	1	1
306	1	1
309	1	1
327	1	1
332	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
370	1	1
372	1	1
373	1	1
			MISSING_ELSE
378	1	1
383	1	1
394	1	1
400	1	1
408	1	1
429	1	1
433	1	1
443	1	1
446	1	1
452	1	1
457	1	1
460	1	1
493	1	1
496	1	1
499	1	1
503	1	1
505	1	1
506	1	1
507	1	1
515	1	1
523	1	1
525	1	1
600	1	1
601	1	1
603	1	1
604	1	1
605	1	1
606	1	1
607	1	1
608	1	1
			MISSING_ELSE
613	1	1
617	1	1
620	1	1
627	1	1
631	1	1
639	1	1
657	1	1
662	1	1
667	4	4
673	1	1
674	1	1
675	1	1
676	1	1
677	1	1
678	1	1
679	1	1
680	1	1
			MISSING_ELSE
686	1	1
707	1	1
727	1	1
739	1	1
741	1	1
747	1	1
748	1	1
750	1	1
754	1	1
764	1	1
777	1	1
789	1	1
792	1	1
796	1	1
799	1	1
802	1	1

---

Cond Coverage for Module : flash_phy_rd

	Total	Covered	Percent
Conditions	457	417	91.25
Logical	457	417	91.25
Non-Logical	0	0
Event	0	0

 LINE       141
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       141
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       141
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       141
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       142
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       142
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       142
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       142
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       147
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T15
0	1	Covered	T2,T67,T223
1	0	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T5,T15
1	1	0	Covered	T224
1	1	1	Covered	T2,T67,T223

 LINE       147
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       147
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T15
0	1	Covered	T2,T67,T132
1	0	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T5,T15
1	1	0	Covered	T224
1	1	1	Covered	T2,T67,T132

 LINE       147
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       147
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T15
0	1	Covered	T2,T67,T68
1	0	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T5,T15
1	1	0	Not Covered
1	1	1	Covered	T2,T67,T68

 LINE       147
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       147
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T15
0	1	Covered	T2,T67,T225
1	0	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T5,T15
1	1	0	Not Covered
1	1	1	Covered	T2,T67,T225

 LINE       147
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       155
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T15

 LINE       155
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T15

 LINE       155
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T15

 LINE       168
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------

-1-	Status	Tests
0	Covered	T2,T5,T15
1	Covered	T1,T2,T3

 LINE       168
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T15
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       168
 EXPRESSION (req_o & no_match)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       187
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------

-1-	Status	Tests
0	Covered	T2,T5,T15
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T2,T5,T15
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T15,T17,T26
1	1	1	0	1	1	1	Covered	T2,T5,T15
1	1	1	1	0	1	1	Covered	T2,T67,T108
1	1	1	1	1	0	1	Covered	T67,T226
1	1	1	1	1	1	0	Covered	T42,T67,T194
1	1	1	1	1	1	1	Covered	T2,T5,T15

 LINE       197
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T15
1	0	Covered	T2,T5,T15

 LINE       197
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T2,T5,T15
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T15,T49,T17
1	1	1	0	1	1	1	Covered	T2,T5,T15
1	1	1	1	0	1	1	Covered	T2,T108,T100
1	1	1	1	1	0	1	Covered	T226
1	1	1	1	1	1	0	Covered	T67,T131,T227
1	1	1	1	1	1	1	Covered	T2,T5,T15

 LINE       197
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T15
1	0	Covered	T2,T5,T15

 LINE       197
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T2,T5,T15
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T15,T49,T17
1	1	1	0	1	1	1	Covered	T2,T5,T15
1	1	1	1	0	1	1	Covered	T108,T100,T224
1	1	1	1	1	0	1	Covered	T226
1	1	1	1	1	1	0	Covered	T42,T194,T131
1	1	1	1	1	1	1	Covered	T2,T5,T15

 LINE       197
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T15
1	0	Covered	T2,T5,T15

 LINE       197
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T2,T5,T15
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T15,T49,T17
1	1	1	0	1	1	1	Covered	T2,T5,T15
1	1	1	1	0	1	1	Covered	T2,T67,T108
1	1	1	1	1	0	1	Covered	T226
1	1	1	1	1	1	0	Covered	T42,T67,T194
1	1	1	1	1	1	1	Covered	T2,T5,T15

 LINE       197
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T15
1	0	Covered	T2,T5,T15

 LINE       197
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T42,T67,T194
1	1	1	Covered	T1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T67,T131,T227
1	1	1	Covered	T1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T42,T194,T131
1	1	1	Covered	T1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T42,T67,T194
1	1	1	Covered	T1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T6,T42
1	1	1	Covered	T1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T6,T42
1	1	1	Covered	T1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T42,T67
1	1	1	Covered	T1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T6,T42,T67
1	1	1	Covered	T1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T49,T17
1	0	Covered	T2,T5,T15
1	1	Covered	T15,T49,T17

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T15,T49,T17
0	1	0	Covered	T15,T17,T21
1	0	0	Covered	T41,T77,T39

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T15,T17,T21

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T17
1	1	Covered	T15,T49,T17

 LINE       223
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T49,T17
1	0	Covered	T2,T5,T15
1	1	Covered	T15,T49,T17

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T15,T49,T17
0	1	0	Covered	T15,T17,T21
1	0	0	Covered	T41,T77,T39

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T15,T17,T21

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T17
1	1	Covered	T15,T49,T17

 LINE       223
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T49,T17
1	0	Covered	T2,T5,T15
1	1	Covered	T15,T49,T17

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T15,T49,T17
0	1	0	Covered	T15,T17,T21
1	0	0	Covered	T41,T77,T39

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T15,T17,T21

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T17
1	1	Covered	T15,T49,T17

 LINE       223
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T49,T17
1	0	Covered	T2,T5,T15
1	1	Covered	T15,T49,T17

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T15,T49,T17
0	1	0	Covered	T15,T17,T21
1	0	0	Covered	T41,T77,T39

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T15,T17,T21

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T17
1	1	Covered	T15,T49,T17

 LINE       233
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---

-1-	Status	Tests
0	Covered	T2,T5,T15
1	Covered	T1,T2,T3

 LINE       240
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T42
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T15

 LINE       240
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T42
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T15

 LINE       240
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T42
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T15

 LINE       240
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T42
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T15

 LINE       292
 EXPRESSION (req_o & ack_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T42,T193
1	1	Covered	T1,T2,T3

 LINE       293
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       303
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       306
 EXPRESSION (req_i && rdy_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T3

 LINE       309
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       378
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       383
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       394
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       400
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
             --------------------------------1-------------------------------   -----------2-----------   --------3-------   -----------------4-----------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T2,T5,T6
1	1	1	1	Covered	T1,T2,T3

 LINE       400
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---

-1-	Status	Tests
0	Covered	T2,T5,T15
1	Covered	T1,T2,T3

 LINE       400
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T5,T6
1	1	1	Covered	T1,T2,T3

 LINE       400
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       408
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
             --1--   --------2-------   ----3----   ------4------   ----5---   -----------------6-----------------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Covered	T1,T2,T3
1	0	1	1	1	1	Covered	T170
1	1	0	1	1	1	Covered	T2,T5,T42
1	1	1	0	1	1	Not Covered
1	1	1	1	0	1	Covered	T2,T5,T15
1	1	1	1	1	0	Covered	T5,T6,T42
1	1	1	1	1	1	Covered	T1,T2,T3

 LINE       408
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T49,T40
1	1	Covered	T1,T2,T3

 LINE       433
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T49,T42,T52

 LINE       433
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T15

 LINE       443
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T49,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T67,T223

 LINE       452
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       452
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T67,T223

 LINE       457
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       493
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy & addr_xor_fifo_rdy)
             ------1------   ------2------   --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T2,T5,T6
1	1	1	Covered	T1,T2,T3

 LINE       496
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T15,T6
1	1	0	Covered	T42,T59,T112
1	1	1	Covered	T1,T2,T3

 LINE       499
 EXPRESSION (rd_done & rd_attrs.descramble & data_erased)
             ---1---   ---------2---------   -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T49,T52,T55
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T42,T59,T112

 LINE       503
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T42,T67
1	1	1	Covered	T2,T15,T6

 LINE       505
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T15,T6
1	1	Covered	T1,T2,T3

 LINE       506
 EXPRESSION (fifo_data_valid & dropmsk_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T42,T59,T112

 LINE       507
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T15,T6

 LINE       515
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : (hint_dropmsk ? mask_valid : fifo_data_valid))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       515
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       515
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : fifo_data_valid)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T42,T59,T112

 LINE       523
 EXPRESSION (hint_forward & (hint_dropmsk ? mask_valid : 1'b1))
             ------1-----   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T42,T59,T112
1	1	Covered	T2,T15,T6

 LINE       523
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : 1'b1)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T42,T59,T112

 LINE       525
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       600
 EXPRESSION (req_o & ack_i & descramble_i)
             --1--   --2--   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T42,T193
1	1	0	Covered	T2,T15,T6
1	1	1	Covered	T1,T2,T3

 LINE       601
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T42
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       617
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T6,T42
1	1	0	Covered	T42,T59,T112
1	1	1	Covered	T1,T2,T3

 LINE       627
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T15,T6

 LINE       627
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       631
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T15,T6

 LINE       631
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------

-1-	Status	Tests
0	Covered	T2,T15,T6
1	Covered	T1,T2,T3

 LINE       639
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T15,T6

 LINE       639
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       657
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T15,T6

 LINE       657
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       657
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       662
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       662
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T15
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       662
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T2,T5,T15
1	1	1	0	Covered	T2,T5,T15
1	1	1	1	Covered	T2,T5,T15

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T2,T5,T15
1	1	1	0	Covered	T2,T5,T15
1	1	1	1	Covered	T2,T5,T15

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T2,T5,T15
1	1	1	0	Covered	T2,T5,T15
1	1	1	1	Covered	T2,T5,T15

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T2,T5,T15
1	1	1	0	Covered	T2,T5,T15
1	1	1	1	Covered	T2,T5,T15

 LINE       680
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T15
0	1	Covered	T224
1	0	Not Covered

 LINE       686
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       739
 EXPRESSION (data_err_o ? inv_data_integ : data_out_intg)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       750
 EXPRESSION (((|buf_rsp_match)) ? buf_addr_xor_muxed : fifo_addr_xor_muxed)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       777
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       777
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       789
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T15
1	0	Covered	T1,T2,T3

 LINE       792
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T3,T10

 LINE       792
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T10

 LINE       792
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T224
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T2,T67,T228

 LINE       792
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T15
1	1	Covered	T224

 LINE       796
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T10

---

Branch Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	187	2	2	100.00
TERNARY	233	2	2	100.00
TERNARY	303	2	2	100.00
TERNARY	452	2	2	100.00
TERNARY	515	3	3	100.00
TERNARY	627	3	3	100.00
TERNARY	631	3	3	100.00
TERNARY	657	3	3	100.00
TERNARY	686	2	2	100.00
TERNARY	739	2	2	100.00
TERNARY	750	2	2	100.00
TERNARY	777	2	2	100.00
TERNARY	168	2	2	100.00
IF	258	3	3	100.00
IF	361	4	4	100.00
IF	603	4	4	100.00
IF	677	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	187	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T15

	LineNo.	Expression
-1-:	233	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T15

	LineNo.	Expression
-1-:	303	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	452	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	515	(hint_descram) ? 
-2-:	515	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T42,T59,T112
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	627	(forward) ? 
-2-:	627	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T15,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	631	(forward) ? 
-2-:	631	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T15,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T15,T6

	LineNo.	Expression
-1-:	657	(forward) ? 
-2-:	657	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T15,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	686	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	739	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	750	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	777	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T15

	LineNo.	Expression
-1-:	258	if ((!rst_ni))
-2-:	260	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	361	if ((!rst_ni))
-2-:	365	if (rd_start)
-3-:	372	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	603	if ((!rst_ni))
-2-:	605	if (calc_req_start)
-3-:	607	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	677	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	790668462	1543203	0	0
ExclusiveOps_A	790668462	789077264	0	0
ExclusiveProgHazard_A	790668462	789077264	0	0
ExclusiveState_A	790668462	789077264	0	0
ForwardCheck_A	790668462	3864909	0	0
IdleCheck_A	790668462	99270537	0	0
MaxBufs_A	2060	2060	0	0
OneHotAlloc_A	790668462	789077264	0	0
OneHotMatch_A	790668462	789077264	0	0
OneHotRspMatch_A	790668462	789077264	0	0
OneHotUpdate_A	790668462	789077264	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790668462	1543203	0	0
T2	95464	1267	0	0
T3	7368	0	0	0
T4	3600	0	0	0
T5	674864	3050	0	0
T6	126450	2214	0	0
T10	2988	0	0	0
T14	2706	0	0	0
T15	3436	10	0	0
T16	8526	0	0	0
T17	0	1472	0	0
T25	0	13688	0	0
T26	0	6	0	0
T28	0	4057	0	0
T40	0	3	0	0
T42	0	1407	0	0
T49	325986	1192	0	0
T50	0	154	0	0
T52	0	287	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790668462	789077264	0	0
T1	373470	373302	0	0
T2	95464	95342	0	0
T3	7368	6042	0	0
T4	3600	3308	0	0
T5	674864	674756	0	0
T6	126450	126336	0	0
T10	2988	2576	0	0
T14	2706	2588	0	0
T15	3436	3276	0	0
T16	8526	8368	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790668462	789077264	0	0
T1	373470	373302	0	0
T2	95464	95342	0	0
T3	7368	6042	0	0
T4	3600	3308	0	0
T5	674864	674756	0	0
T6	126450	126336	0	0
T10	2988	2576	0	0
T14	2706	2588	0	0
T15	3436	3276	0	0
T16	8526	8368	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790668462	789077264	0	0
T1	373470	373302	0	0
T2	95464	95342	0	0
T3	7368	6042	0	0
T4	3600	3308	0	0
T5	674864	674756	0	0
T6	126450	126336	0	0
T10	2988	2576	0	0
T14	2706	2588	0	0
T15	3436	3276	0	0
T16	8526	8368	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790668462	3864909	0	0
T2	95464	13044	0	0
T3	7368	0	0	0
T4	3600	0	0	0
T5	674864	0	0	0
T6	126450	480	0	0
T10	2988	0	0	0
T14	2706	0	0	0
T15	3436	10	0	0
T16	8526	0	0	0
T25	0	31945	0	0
T28	0	17381	0	0
T40	0	7	0	0
T42	0	42600	0	0
T49	325986	1192	0	0
T51	0	17050	0	0
T52	0	601	0	0
T59	0	42	0	0
T67	0	9088	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790668462	99270537	0	0
T1	186735	128	0	0
T2	95464	45709	0	0
T3	7368	784	0	0
T4	3600	256	0	0
T5	674864	209145	0	0
T6	126450	71427	0	0
T10	2988	268	0	0
T14	2706	128	0	0
T15	3436	158	0	0
T16	8526	128	0	0
T21	0	524288	0	0
T25	0	921456	0	0
T28	0	16288	0	0
T29	0	30135	0	0
T40	0	10	0	0
T42	0	67676	0	0
T49	162993	1830	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2060	2060	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T10	2	2	0	0
T14	2	2	0	0
T15	2	2	0	0
T16	2	2	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790668462	789077264	0	0
T1	373470	373302	0	0
T2	95464	95342	0	0
T3	7368	6042	0	0
T4	3600	3308	0	0
T5	674864	674756	0	0
T6	126450	126336	0	0
T10	2988	2576	0	0
T14	2706	2588	0	0
T15	3436	3276	0	0
T16	8526	8368	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790668462	789077264	0	0
T1	373470	373302	0	0
T2	95464	95342	0	0
T3	7368	6042	0	0
T4	3600	3308	0	0
T5	674864	674756	0	0
T6	126450	126336	0	0
T10	2988	2576	0	0
T14	2706	2588	0	0
T15	3436	3276	0	0
T16	8526	8368	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790668462	789077264	0	0
T1	373470	373302	0	0
T2	95464	95342	0	0
T3	7368	6042	0	0
T4	3600	3308	0	0
T5	674864	674756	0	0
T6	126450	126336	0	0
T10	2988	2576	0	0
T14	2706	2588	0	0
T15	3436	3276	0	0
T16	8526	8368	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	790668462	789077264	0	0
T1	373470	373302	0	0
T2	95464	95342	0	0
T3	7368	6042	0	0
T4	3600	3308	0	0
T5	674864	674756	0	0
T6	126450	126336	0	0
T10	2988	2576	0	0
T14	2706	2588	0	0
T15	3436	3276	0	0
T16	8526	8368	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
ALWAYS	258	4	4	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	327	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
ALWAYS	361	12	12	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	443	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	452	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	506	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	600	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
ALWAYS	603	6	6	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	620	1	1	100.00
CONT_ASSIGN	627	1	1	100.00
CONT_ASSIGN	631	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	662	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
ALWAYS	673	8	8	100.00
CONT_ASSIGN	686	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	727	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	764	1	1	100.00
CONT_ASSIGN	777	1	1	100.00
CONT_ASSIGN	789	1	1	100.00
CONT_ASSIGN	792	1	1	100.00
CONT_ASSIGN	796	1	1	100.00
CONT_ASSIGN	799	1	1	100.00
CONT_ASSIGN	802	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
141	4	4
142	4	4
147	4	4
153	1	1
155	3	3
187	1	1
194	4	4
195	4	4
197	4	4
213	4	4
219	4	4
223	4	4
230	1	1
233	1	1
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
292	1	1
293	1	1
303	1	1
306	1	1
309	1	1
327	1	1
332	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
370	1	1
372	1	1
373	1	1
			MISSING_ELSE
378	1	1
383	1	1
394	1	1
400	1	1
408	1	1
429	1	1
433	1	1
443	1	1
446	1	1
452	1	1
457	1	1
460	1	1
493	1	1
496	1	1
499	1	1
503	1	1
505	1	1
506	1	1
507	1	1
515	1	1
523	1	1
525	1	1
600	1	1
601	1	1
603	1	1
604	1	1
605	1	1
606	1	1
607	1	1
608	1	1
			MISSING_ELSE
613	1	1
617	1	1
620	1	1
627	1	1
631	1	1
639	1	1
657	1	1
662	1	1
667	4	4
673	1	1
674	1	1
675	1	1
676	1	1
677	1	1
678	1	1
679	1	1
680	1	1
			MISSING_ELSE
686	1	1
707	1	1
727	1	1
739	1	1
741	1	1
747	1	1
748	1	1
750	1	1
754	1	1
764	1	1
777	1	1
789	1	1
792	1	1
796	1	1
799	1	1
802	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Covered	Percent
Conditions	457	411	89.93
Logical	457	411	89.93
Non-Logical	0	0
Event	0	0

 LINE       141
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       141
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       141
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       141
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       142
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       142
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       142
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       142
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       147
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T15
0	1	Covered	T2,T67,T223
1	0	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T5,T15
1	1	0	Not Covered
1	1	1	Covered	T2,T67,T223

 LINE       147
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       147
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T15
0	1	Covered	T2,T67,T132
1	0	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T5,T15
1	1	0	Not Covered
1	1	1	Covered	T2,T67,T132

 LINE       147
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       147
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T15
0	1	Covered	T2,T67,T228
1	0	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T5,T15
1	1	0	Not Covered
1	1	1	Covered	T2,T67,T228

 LINE       147
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       147
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T15
0	1	Covered	T2,T67,T225
1	0	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T5,T15
1	1	0	Not Covered
1	1	1	Covered	T2,T67,T225

 LINE       147
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       155
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T15

 LINE       155
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T15

 LINE       155
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T15

 LINE       168
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------

-1-	Status	Tests
0	Covered	T2,T5,T15
1	Covered	T1,T2,T3

 LINE       168
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T15
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       168
 EXPRESSION (req_o & no_match)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       187
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------

-1-	Status	Tests
0	Covered	T2,T5,T15
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T2,T5,T15
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T15,T17,T26
1	1	1	0	1	1	1	Covered	T2,T5,T15
1	1	1	1	0	1	1	Covered	T67,T108,T229
1	1	1	1	1	0	1	Covered	T67,T226
1	1	1	1	1	1	0	Covered	T42,T194,T230
1	1	1	1	1	1	1	Covered	T2,T5,T15

 LINE       197
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T15
1	0	Covered	T2,T5,T15

 LINE       197
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T2,T5,T15
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T15,T49,T17
1	1	1	0	1	1	1	Covered	T2,T5,T15
1	1	1	1	0	1	1	Covered	T2,T108,T224
1	1	1	1	1	0	1	Covered	T226
1	1	1	1	1	1	0	Covered	T67,T131,T227
1	1	1	1	1	1	1	Covered	T2,T5,T15

 LINE       197
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T15
1	0	Covered	T2,T5,T15

 LINE       197
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T2,T5,T15
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T15,T49,T17
1	1	1	0	1	1	1	Covered	T2,T5,T15
1	1	1	1	0	1	1	Covered	T108,T100,T224
1	1	1	1	1	0	1	Covered	T226
1	1	1	1	1	1	0	Covered	T194,T131,T227
1	1	1	1	1	1	1	Covered	T2,T5,T15

 LINE       197
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T15
1	0	Covered	T2,T5,T15

 LINE       197
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T2,T5,T15
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T15,T49,T17
1	1	1	0	1	1	1	Covered	T2,T5,T15
1	1	1	1	0	1	1	Covered	T2,T67,T108
1	1	1	1	1	0	1	Covered	T226
1	1	1	1	1	1	0	Covered	T42,T194,T196
1	1	1	1	1	1	1	Covered	T2,T5,T15

 LINE       197
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T15
1	0	Covered	T2,T5,T15

 LINE       197
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T42,T194,T230
1	1	1	Covered	T1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T67,T131,T227
1	1	1	Covered	T1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T194,T131,T227
1	1	1	Covered	T1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T42,T194,T196
1	1	1	Covered	T1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T6,T42,T67
1	1	1	Covered	T1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T6,T42,T67
1	1	1	Covered	T1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T42,T67,T41
1	1	1	Covered	T1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T6,T42,T67
1	1	1	Covered	T1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T49,T17
1	0	Covered	T2,T5,T15
1	1	Covered	T15,T49,T17

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T15,T49,T17
0	1	0	Covered	T15,T17,T21
1	0	0	Covered	T41,T39,T78

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T15
1	1	Covered	T15,T17,T21

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T17
1	1	Covered	T15,T49,T17

 LINE       223
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T49,T17
1	0	Covered	T2,T5,T15
1	1	Covered	T15,T49,T17

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T15,T49,T17
0	1	0	Covered	T15,T17,T21
1	0	0	Covered	T41,T39,T78

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T15
1	1	Covered	T15,T17,T21

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T17
1	1	Covered	T15,T49,T17

 LINE       223
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T49,T17
1	0	Covered	T2,T5,T15
1	1	Covered	T15,T49,T17

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T15,T49,T17
0	1	0	Covered	T15,T17,T21
1	0	0	Covered	T41,T39,T78

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T15
1	1	Covered	T15,T17,T21

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T17
1	1	Covered	T15,T49,T17

 LINE       223
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T49,T17
1	0	Covered	T2,T5,T15
1	1	Covered	T15,T49,T17

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T15,T49,T17
0	1	0	Covered	T15,T17,T21
1	0	0	Covered	T41,T39,T78

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T15
1	1	Covered	T15,T17,T21

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T17
1	1	Covered	T15,T49,T17

 LINE       233
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---

-1-	Status	Tests
0	Covered	T2,T5,T15
1	Covered	T1,T2,T3

 LINE       240
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T42
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T15

 LINE       240
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T42
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T15

 LINE       240
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T42
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T15

 LINE       240
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T42
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T15

 LINE       292
 EXPRESSION (req_o & ack_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T42,T193
1	1	Covered	T1,T2,T3

 LINE       293
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       303
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       306
 EXPRESSION (req_i && rdy_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T3

 LINE       309
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       378
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       383
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       394
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       400
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
             --------------------------------1-------------------------------   -----------2-----------   --------3-------   -----------------4-----------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T2,T5,T6
1	1	1	1	Covered	T1,T2,T3

 LINE       400
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---

-1-	Status	Tests
0	Covered	T2,T5,T15
1	Covered	T1,T2,T3

 LINE       400
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T5,T6
1	1	1	Covered	T1,T2,T3

 LINE       400
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       408
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
             --1--   --------2-------   ----3----   ------4------   ----5---   -----------------6-----------------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Covered	T1,T2,T3
1	0	1	1	1	1	Not Covered
1	1	0	1	1	1	Covered	T2,T5,T42
1	1	1	0	1	1	Not Covered
1	1	1	1	0	1	Covered	T2,T5,T15
1	1	1	1	1	0	Covered	T5,T6,T42
1	1	1	1	1	1	Covered	T1,T2,T3

 LINE       408
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       429
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T49,T40
1	1	Covered	T1,T2,T3

 LINE       433
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T49,T42,T52

 LINE       433
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T15

 LINE       443
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T49,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T67,T223

 LINE       452
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       452
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T67,T223

 LINE       457
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       493
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy & addr_xor_fifo_rdy)
             ------1------   ------2------   --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T2,T5,T6
1	1	1	Covered	T1,T2,T3

 LINE       496
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T15,T6
1	1	0	Covered	T42,T59,T112
1	1	1	Covered	T1,T2,T3

 LINE       499
 EXPRESSION (rd_done & rd_attrs.descramble & data_erased)
             ---1---   ---------2---------   -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T49,T52,T231
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T42,T59,T112

 LINE       503
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T42,T67
1	1	1	Covered	T2,T15,T6

 LINE       505
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T15,T6
1	1	Covered	T1,T2,T3

 LINE       506
 EXPRESSION (fifo_data_valid & dropmsk_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T42,T59,T112

 LINE       507
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T15,T6

 LINE       515
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : (hint_dropmsk ? mask_valid : fifo_data_valid))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       515
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       515
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : fifo_data_valid)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T42,T59,T112

 LINE       523
 EXPRESSION (hint_forward & (hint_dropmsk ? mask_valid : 1'b1))
             ------1-----   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T42,T59,T112
1	1	Covered	T2,T15,T6

 LINE       523
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : 1'b1)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T42,T59,T112

 LINE       525
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       600
 EXPRESSION (req_o & ack_i & descramble_i)
             --1--   --2--   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T42,T193
1	1	0	Covered	T2,T15,T6
1	1	1	Covered	T1,T2,T3

 LINE       601
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T42
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       617
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T6,T42
1	1	0	Covered	T42,T59,T112
1	1	1	Covered	T1,T2,T3

 LINE       627
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T15,T6

 LINE       627
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       631
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T15,T6

 LINE       631
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------

-1-	Status	Tests
0	Covered	T2,T15,T6
1	Covered	T1,T2,T3

 LINE       639
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T15,T6

 LINE       639
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       657
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T15,T6

 LINE       657
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       657
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       662
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       662
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T15
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       662
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T2,T5,T15
1	1	1	0	Covered	T2,T5,T15
1	1	1	1	Covered	T2,T5,T15

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T2,T5,T15
1	1	1	0	Covered	T2,T5,T15
1	1	1	1	Covered	T2,T5,T15

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T2,T5,T15
1	1	1	0	Covered	T2,T5,T15
1	1	1	1	Covered	T2,T5,T15

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T2,T5,T15
1	1	1	0	Covered	T2,T5,T15
1	1	1	1	Covered	T2,T5,T15

 LINE       680
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T15
0	1	Not Covered
1	0	Not Covered

 LINE       686
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       739
 EXPRESSION (data_err_o ? inv_data_integ : data_out_intg)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       750
 EXPRESSION (((|buf_rsp_match)) ? buf_addr_xor_muxed : fifo_addr_xor_muxed)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T15

 LINE       777
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       777
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       789
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T15
1	0	Covered	T1,T2,T3

 LINE       792
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T3,T10

 LINE       792
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T10

 LINE       792
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T2,T67,T228

 LINE       792
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T15
1	1	Not Covered

 LINE       796
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T10

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	187	2	2	100.00
TERNARY	233	2	2	100.00
TERNARY	303	2	2	100.00
TERNARY	452	2	2	100.00
TERNARY	515	3	3	100.00
TERNARY	627	3	3	100.00
TERNARY	631	3	3	100.00
TERNARY	657	3	3	100.00
TERNARY	686	2	2	100.00
TERNARY	739	2	2	100.00
TERNARY	750	2	2	100.00
TERNARY	777	2	2	100.00
TERNARY	168	2	2	100.00
IF	258	3	3	100.00
IF	361	4	4	100.00
IF	603	4	4	100.00
IF	677	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	187	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T15

	LineNo.	Expression
-1-:	233	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T15

	LineNo.	Expression
-1-:	303	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	452	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	515	(hint_descram) ? 
-2-:	515	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T42,T59,T112
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	627	(forward) ? 
-2-:	627	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T15,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	631	(forward) ? 
-2-:	631	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T15,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T15,T6

	LineNo.	Expression
-1-:	657	(forward) ? 
-2-:	657	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T15,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	686	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	739	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	750	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	777	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T15

	LineNo.	Expression
-1-:	258	if ((!rst_ni))
-2-:	260	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	361	if ((!rst_ni))
-2-:	365	if (rd_start)
-3-:	372	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	603	if ((!rst_ni))
-2-:	605	if (calc_req_start)
-3-:	607	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	677	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	395334231	791974	0	0
ExclusiveOps_A	395334231	394538632	0	0
ExclusiveProgHazard_A	395334231	394538632	0	0
ExclusiveState_A	395334231	394538632	0	0
ForwardCheck_A	395334231	2054875	0	0
IdleCheck_A	395334231	50956725	0	0
MaxBufs_A	1030	1030	0	0
OneHotAlloc_A	395334231	394538632	0	0
OneHotMatch_A	395334231	394538632	0	0
OneHotRspMatch_A	395334231	394538632	0	0
OneHotUpdate_A	395334231	394538632	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	791974	0	0
T2	47732	454	0	0
T3	3684	0	0	0
T4	1800	0	0	0
T5	337432	1711	0	0
T6	63225	1361	0	0
T10	1494	0	0	0
T14	1353	0	0	0
T15	1718	10	0	0
T16	4263	0	0	0
T17	0	1472	0	0
T25	0	5438	0	0
T28	0	4057	0	0
T40	0	1	0	0
T42	0	695	0	0
T49	162993	582	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	2054875	0	0
T2	47732	3626	0	0
T3	3684	0	0	0
T4	1800	0	0	0
T5	337432	0	0	0
T6	63225	480	0	0
T10	1494	0	0	0
T14	1353	0	0	0
T15	1718	10	0	0
T16	4263	0	0	0
T25	0	14039	0	0
T28	0	9237	0	0
T40	0	3	0	0
T42	0	21387	0	0
T49	162993	582	0	0
T51	0	8647	0	0
T52	0	265	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	50956725	0	0
T1	186735	128	0	0
T2	47732	26060	0	0
T3	3684	784	0	0
T4	1800	256	0	0
T5	337432	120642	0	0
T6	63225	37253	0	0
T10	1494	268	0	0
T14	1353	128	0	0
T15	1718	158	0	0
T16	4263	128	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030	1030	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
ALWAYS	258	4	4	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	327	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
ALWAYS	361	12	12	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	429	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	443	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	452	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	506	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	600	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
ALWAYS	603	6	6	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	620	1	1	100.00
CONT_ASSIGN	627	1	1	100.00
CONT_ASSIGN	631	1	1	100.00
CONT_ASSIGN	639	1	1	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	662	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
ALWAYS	673	8	8	100.00
CONT_ASSIGN	686	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	727	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	764	1	1	100.00
CONT_ASSIGN	777	1	1	100.00
CONT_ASSIGN	789	1	1	100.00
CONT_ASSIGN	792	1	1	100.00
CONT_ASSIGN	796	1	1	100.00
CONT_ASSIGN	799	1	1	100.00
CONT_ASSIGN	802	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
141	4	4
142	4	4
147	4	4
153	1	1
155	3	3
187	1	1
194	4	4
195	4	4
197	4	4
213	4	4
219	4	4
223	4	4
230	1	1
233	1	1
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
292	1	1
293	1	1
303	1	1
306	1	1
309	1	1
327	1	1
332	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
370	1	1
372	1	1
373	1	1
			MISSING_ELSE
378	1	1
383	1	1
394	1	1
400	1	1
408	1	1
429	1	1
433	1	1
443	1	1
446	1	1
452	1	1
457	1	1
460	1	1
493	1	1
496	1	1
499	1	1
503	1	1
505	1	1
506	1	1
507	1	1
515	1	1
523	1	1
525	1	1
600	1	1
601	1	1
603	1	1
604	1	1
605	1	1
606	1	1
607	1	1
608	1	1
			MISSING_ELSE
613	1	1
617	1	1
620	1	1
627	1	1
631	1	1
639	1	1
657	1	1
662	1	1
667	4	4
673	1	1
674	1	1
675	1	1
676	1	1
677	1	1
678	1	1
679	1	1
680	1	1
			MISSING_ELSE
686	1	1
707	1	1
727	1	1
739	1	1
741	1	1
747	1	1
748	1	1
750	1	1
754	1	1
764	1	1
777	1	1
789	1	1
792	1	1
796	1	1
799	1	1
802	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Covered	Percent
Conditions	457	415	90.81
Logical	457	415	90.81
Non-Logical	0	0
Event	0	0

 LINE       141
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       141
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       141
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       141
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       142
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       142
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       142
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       142
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       147
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T67,T108
1	0	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T5,T6
1	1	0	Covered	T224
1	1	1	Covered	T2,T67,T108

 LINE       147
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       147
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T67,T108
1	0	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T5,T6
1	1	0	Covered	T224
1	1	1	Covered	T2,T67,T108

 LINE       147
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       147
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T67,T68
1	0	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T2,T67,T68

 LINE       147
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       147
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T67,T108
1	0	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T2,T67,T108

 LINE       147
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       155
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       155
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       155
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       168
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T3

 LINE       168
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       168
 EXPRESSION (req_o & no_match)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T5,T6

 LINE       187
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T2,T5,T6
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T56,T232,T233
1	1	1	0	1	1	1	Covered	T2,T5,T6
1	1	1	1	0	1	1	Covered	T2,T108,T100
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T67,T96,T234
1	1	1	1	1	1	1	Covered	T2,T5,T6

 LINE       197
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6

 LINE       197
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T2,T5,T6
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T49,T55,T117
1	1	1	0	1	1	1	Covered	T2,T5,T6
1	1	1	1	0	1	1	Covered	T108,T100,T235
1	1	1	1	1	0	1	Not Covered
1	1	1	1	1	1	0	Covered	T67,T131,T227
1	1	1	1	1	1	1	Covered	T2,T5,T6

 LINE       197
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6

 LINE       197
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T2,T5,T6
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T49,T55,T115
1	1	1	0	1	1	1	Covered	T2,T5,T6
1	1	1	1	0	1	1	Covered	T108,T100,T224
1	1	1	1	1	0	1	Covered	T226
1	1	1	1	1	1	0	Covered	T42,T110,T236
1	1	1	1	1	1	1	Covered	T2,T5,T6

 LINE       197
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6

 LINE       197
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	1	1	1	1	1	1	Covered	T2,T5,T6
1	0	1	1	1	1	1	Not Covered
1	1	0	1	1	1	1	Covered	T49,T55,T115
1	1	1	0	1	1	1	Covered	T2,T5,T6
1	1	1	1	0	1	1	Covered	T108,T100,T237
1	1	1	1	1	0	1	Covered	T226
1	1	1	1	1	1	0	Covered	T42,T67,T63
1	1	1	1	1	1	1	Covered	T2,T5,T6

 LINE       197
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6

 LINE       197
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T67,T96,T238
1	1	1	Covered	T1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T67,T131,T227
1	1	1	Covered	T1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T42,T110,T238
1	1	1	Covered	T1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T42,T67,T63
1	1	1	Covered	T1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T6,T67
1	1	1	Covered	T1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T6,T67
1	1	1	Covered	T1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T42,T41
1	1	1	Covered	T1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T6,T42,T67
1	1	1	Covered	T1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T49,T21,T77
1	0	Covered	T2,T5,T6
1	1	Covered	T49,T39,T55

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T49,T21,T55
0	1	0	Covered	T21,T55,T22
1	0	0	Covered	T77,T39,T55

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T21,T55,T22

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T41,T39
1	1	Covered	T49,T21,T55

 LINE       223
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T49,T21,T77
1	0	Covered	T2,T5,T6
1	1	Covered	T49,T39,T55

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T49,T21,T55
0	1	0	Covered	T21,T55,T22
1	0	0	Covered	T77,T39,T55

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T21,T55,T22

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T41,T39
1	1	Covered	T49,T21,T55

 LINE       223
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T49,T21,T77
1	0	Covered	T2,T5,T6
1	1	Covered	T49,T39,T55

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T49,T21,T55
0	1	0	Covered	T21,T55,T22
1	0	0	Covered	T77,T39,T55

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T21,T55,T22

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T41,T39
1	1	Covered	T49,T21,T55

 LINE       223
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T49,T21,T77
1	0	Covered	T2,T5,T6
1	1	Covered	T49,T39,T55

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T49,T21,T55
0	1	0	Covered	T21,T55,T22
1	0	0	Covered	T77,T39,T55

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T21,T55,T22

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T41,T39
1	1	Covered	T49,T21,T55

 LINE       233
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T3

 LINE       240
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T42
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       240
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T42
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       240
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T42
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       240
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T42
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       292
 EXPRESSION (req_o & ack_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T42,T193
1	1	Covered	T2,T5,T6

 LINE       293
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T49
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       303
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       306
 EXPRESSION (req_i && rdy_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       309
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       378
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3

 LINE       383
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       394
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       400
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
             --------------------------------1-------------------------------   -----------2-----------   --------3-------   -----------------4-----------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Covered	T5,T6,T42
1	1	1	1	Covered	T1,T2,T3

 LINE       400
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T3

 LINE       400
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T5,T6
1	1	0	Covered	T2,T5,T6
1	1	1	Covered	T1,T2,T3

 LINE       400
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T42

 LINE       408
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
             --1--   --------2-------   ----3----   ------4------   ----5---   -----------------6-----------------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Covered	T1,T2,T3
1	0	1	1	1	1	Covered	T170
1	1	0	1	1	1	Covered	T2,T5,T42
1	1	1	0	1	1	Not Covered
1	1	1	1	0	1	Covered	T2,T5,T6
1	1	1	1	1	0	Covered	T5,T6,T42
1	1	1	1	1	1	Covered	T2,T5,T6

 LINE       408
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T42

 LINE       429
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T49,T40,T25
1	1	Covered	T2,T5,T6

 LINE       433
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T49
1	0	Covered	T2,T5,T6
1	1	Covered	T49,T42,T52

 LINE       433
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T49

 LINE       443
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T49,T25
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T67,T68

 LINE       452
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       452
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T67,T68

 LINE       457
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       493
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy & addr_xor_fifo_rdy)
             ------1------   ------2------   --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T2,T5,T6
1	1	1	Covered	T1,T2,T3

 LINE       496
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T42
1	0	1	Covered	T2,T49,T40
1	1	0	Covered	T42,T59,T112
1	1	1	Covered	T5,T6,T29

 LINE       499
 EXPRESSION (rd_done & rd_attrs.descramble & data_erased)
             ---1---   ---------2---------   -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T49,T52,T55
1	1	0	Covered	T5,T6,T29
1	1	1	Covered	T42,T59,T112

 LINE       503
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T29
1	1	0	Covered	T194,T239,T240
1	1	1	Covered	T2,T49,T42

 LINE       505
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T49,T42
1	1	Covered	T5,T6,T29

 LINE       506
 EXPRESSION (fifo_data_valid & dropmsk_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T6
1	1	Covered	T42,T59,T112

 LINE       507
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T29
1	1	Covered	T2,T49,T42

 LINE       515
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : (hint_dropmsk ? mask_valid : fifo_data_valid))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T29

 LINE       515
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T29
1	1	Covered	T5,T6,T29

 LINE       515
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : fifo_data_valid)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T42,T59,T112

 LINE       523
 EXPRESSION (hint_forward & (hint_dropmsk ? mask_valid : 1'b1))
             ------1-----   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T42,T59,T112
1	1	Covered	T2,T49,T42

 LINE       523
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : 1'b1)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T42,T59,T112

 LINE       525
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T5,T6,T29

 LINE       600
 EXPRESSION (req_o & ack_i & descramble_i)
             --1--   --2--   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T42,T193
1	1	0	Covered	T2,T49,T40
1	1	1	Covered	T5,T6,T42

 LINE       601
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T42
1	0	Covered	T5,T6,T42
1	1	Covered	T5,T6,T42

 LINE       617
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T6,T29
1	1	0	Covered	T42,T59,T112
1	1	1	Covered	T5,T6,T29

 LINE       627
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T49,T42

 LINE       627
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T29

 LINE       631
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T49,T42

 LINE       631
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------

-1-	Status	Tests
0	Covered	T2,T49,T42
1	Covered	T1,T2,T3

 LINE       639
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T29
1	0	Covered	T2,T49,T42

 LINE       639
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T49,T42
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T29

 LINE       657
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T49,T42

 LINE       657
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T29

 LINE       657
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T49,T42
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T29

 LINE       662
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T21,T22,T23
1	1	0	Not Covered
1	1	1	Covered	T2,T5,T6

 LINE       662
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       662
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T2,T5,T6
1	1	1	0	Covered	T2,T5,T6
1	1	1	1	Covered	T2,T5,T6

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T2,T5,T6
1	1	1	0	Covered	T2,T5,T6
1	1	1	1	Covered	T2,T5,T6

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T2,T5,T6
1	1	1	0	Covered	T2,T5,T6
1	1	1	1	Covered	T2,T5,T6

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T2,T5,T6
1	1	1	0	Covered	T2,T5,T6
1	1	1	1	Covered	T2,T5,T6

 LINE       680
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T224
1	0	Not Covered

 LINE       686
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       739
 EXPRESSION (data_err_o ? inv_data_integ : data_out_intg)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T67,T68

 LINE       750
 EXPRESSION (((|buf_rsp_match)) ? buf_addr_xor_muxed : fifo_addr_xor_muxed)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       777
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       777
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T2,T5,T6

 LINE       789
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6

 LINE       792
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T67,T68

 LINE       792
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T67,T68

 LINE       792
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T224
0	1	0	Covered	T2,T5,T6
1	0	0	Covered	T2,T67,T108

 LINE       792
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T6
1	1	Covered	T224

 LINE       796
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T67,T68

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	187	2	2	100.00
TERNARY	233	2	2	100.00
TERNARY	303	2	2	100.00
TERNARY	452	2	2	100.00
TERNARY	515	3	3	100.00
TERNARY	627	3	3	100.00
TERNARY	631	3	3	100.00
TERNARY	657	3	3	100.00
TERNARY	686	2	2	100.00
TERNARY	739	2	2	100.00
TERNARY	750	2	2	100.00
TERNARY	777	2	2	100.00
TERNARY	168	2	2	100.00
IF	258	3	3	100.00
IF	361	4	4	100.00
IF	603	4	4	100.00
IF	677	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	187	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	233	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	303	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	452	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	515	(hint_descram) ? 
-2-:	515	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T29
0	1	Covered	T42,T59,T112
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	627	(forward) ? 
-2-:	627	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T49,T42
0	1	Covered	T5,T6,T29
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	631	(forward) ? 
-2-:	631	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T49,T42
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T49,T42

	LineNo.	Expression
-1-:	657	(forward) ? 
-2-:	657	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T49,T42
0	1	Covered	T5,T6,T29
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	686	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	739	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T67,T68
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	750	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	777	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	168	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	258	if ((!rst_ni))
-2-:	260	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	361	if ((!rst_ni))
-2-:	365	if (rd_start)
-3-:	372	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	603	if ((!rst_ni))
-2-:	605	if (calc_req_start)
-3-:	607	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T42
0	0	1	Covered	T5,T6,T42
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	677	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	395334231	751229	0	0
ExclusiveOps_A	395334231	394538632	0	0
ExclusiveProgHazard_A	395334231	394538632	0	0
ExclusiveState_A	395334231	394538632	0	0
ForwardCheck_A	395334231	1810034	0	0
IdleCheck_A	395334231	48313812	0	0
MaxBufs_A	1030	1030	0	0
OneHotAlloc_A	395334231	394538632	0	0
OneHotMatch_A	395334231	394538632	0	0
OneHotRspMatch_A	395334231	394538632	0	0
OneHotUpdate_A	395334231	394538632	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	751229	0	0
T2	47732	813	0	0
T3	3684	0	0	0
T4	1800	0	0	0
T5	337432	1339	0	0
T6	63225	853	0	0
T10	1494	0	0	0
T14	1353	0	0	0
T15	1718	0	0	0
T16	4263	0	0	0
T25	0	8250	0	0
T26	0	6	0	0
T40	0	2	0	0
T42	0	712	0	0
T49	162993	610	0	0
T50	0	154	0	0
T52	0	287	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	1810034	0	0
T2	47732	9418	0	0
T3	3684	0	0	0
T4	1800	0	0	0
T5	337432	0	0	0
T6	63225	0	0	0
T10	1494	0	0	0
T14	1353	0	0	0
T15	1718	0	0	0
T16	4263	0	0	0
T25	0	17906	0	0
T28	0	8144	0	0
T40	0	4	0	0
T42	0	21213	0	0
T49	162993	610	0	0
T51	0	8403	0	0
T52	0	336	0	0
T59	0	42	0	0
T67	0	9088	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	48313812	0	0
T2	47732	19649	0	0
T3	3684	0	0	0
T4	1800	0	0	0
T5	337432	88503	0	0
T6	63225	34174	0	0
T10	1494	0	0	0
T14	1353	0	0	0
T15	1718	0	0	0
T16	4263	0	0	0
T21	0	524288	0	0
T25	0	921456	0	0
T28	0	16288	0	0
T29	0	30135	0	0
T40	0	10	0	0
T42	0	67676	0	0
T49	162993	1830	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030	1030	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395334231	394538632	0	0
T1	186735	186651	0	0
T2	47732	47671	0	0
T3	3684	3021	0	0
T4	1800	1654	0	0
T5	337432	337378	0	0
T6	63225	63168	0	0
T10	1494	1288	0	0
T14	1353	1294	0	0
T15	1718	1638	0	0
T16	4263	4184	0	0