Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.37 100.00 89.50 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.10 97.64 92.58 100.00 98.73 96.55


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.57 96.63 84.91 100.00 91.30 100.00 gen_flash_cores[1].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_bufs[0].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_bufs[1].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_bufs[2].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_bufs[3].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_rd.gen_bus_words_intg[0].u_bus_intg 100.00 100.00
gen_rd.gen_bus_words_intg[0].u_prim_buf_intg 100.00 100.00
gen_rd.gen_bus_words_intg[1].u_bus_intg 100.00 100.00
gen_rd.gen_bus_words_intg[1].u_prim_buf_intg 100.00 100.00
u_addr_xor_storage 96.53 100.00 86.11 100.00 100.00
u_bus_inv_data_intg 0.00 0.00
u_dec 100.00 100.00 100.00
u_intg_buf 100.00 100.00
u_mask_storage 93.75 100.00 80.56 94.44 100.00
u_plain_enc 100.00 100.00
u_prim_buf_data_xor_out 100.00 100.00
u_rd_buf_dep 96.59 100.00 86.36 100.00 100.00
u_rd_storage 93.90 100.00 79.49 100.00 90.00 100.00
u_rsp_order_fifo 97.44 100.00 87.18 100.00 100.00 100.00
u_valid_random 94.17 92.31 97.69 100.00 86.67



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.43 100.00 89.72 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.12 97.64 92.66 100.00 98.73 96.55


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.40 98.88 95.28 100.00 97.83 100.00 gen_flash_cores[0].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_bufs[0].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_bufs[1].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_bufs[2].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_bufs[3].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_rd.gen_bus_words_intg[0].u_bus_intg 100.00 100.00
gen_rd.gen_bus_words_intg[0].u_prim_buf_intg 100.00 100.00
gen_rd.gen_bus_words_intg[1].u_bus_intg 100.00 100.00
gen_rd.gen_bus_words_intg[1].u_prim_buf_intg 100.00 100.00
u_addr_xor_storage 96.53 100.00 86.11 100.00 100.00
u_bus_inv_data_intg 0.00 0.00
u_dec 100.00 100.00 100.00
u_intg_buf 100.00 100.00
u_mask_storage 93.75 100.00 80.56 94.44 100.00
u_plain_enc 100.00 100.00
u_prim_buf_data_xor_out 100.00 100.00
u_rd_buf_dep 96.59 100.00 86.36 100.00 100.00
u_rd_storage 93.90 100.00 79.49 100.00 90.00 100.00
u_rsp_order_fifo 97.44 100.00 87.18 100.00 100.00 100.00
u_valid_random 94.17 92.31 97.69 100.00 86.67

Line Coverage for Module : flash_phy_rd
Line No.TotalCoveredPercent
TOTAL133133100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN21911100.00
CONT_ASSIGN21911100.00
CONT_ASSIGN21911100.00
CONT_ASSIGN21911100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN23011100.00
CONT_ASSIGN23311100.00
ALWAYS25844100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN30311100.00
CONT_ASSIGN30611100.00
CONT_ASSIGN30911100.00
CONT_ASSIGN32711100.00
CONT_ASSIGN33211100.00
ALWAYS3611212100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN38311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN40011100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN42911100.00
CONT_ASSIGN43311100.00
CONT_ASSIGN44311100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN45211100.00
CONT_ASSIGN45711100.00
CONT_ASSIGN46011100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49911100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50511100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN51511100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN52511100.00
CONT_ASSIGN60011100.00
CONT_ASSIGN60111100.00
ALWAYS60366100.00
CONT_ASSIGN61311100.00
CONT_ASSIGN61711100.00
CONT_ASSIGN62011100.00
CONT_ASSIGN62711100.00
CONT_ASSIGN63111100.00
CONT_ASSIGN63911100.00
CONT_ASSIGN65711100.00
CONT_ASSIGN66211100.00
CONT_ASSIGN66711100.00
CONT_ASSIGN66711100.00
CONT_ASSIGN66711100.00
CONT_ASSIGN66711100.00
ALWAYS67388100.00
CONT_ASSIGN68611100.00
CONT_ASSIGN70711100.00
CONT_ASSIGN72711100.00
CONT_ASSIGN73911100.00
CONT_ASSIGN74111100.00
CONT_ASSIGN74711100.00
CONT_ASSIGN74811100.00
CONT_ASSIGN75011100.00
CONT_ASSIGN75411100.00
CONT_ASSIGN76411100.00
CONT_ASSIGN77711100.00
CONT_ASSIGN78911100.00
CONT_ASSIGN79211100.00
CONT_ASSIGN79611100.00
CONT_ASSIGN79911100.00
CONT_ASSIGN80211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
138 1 1
141 4 4
142 4 4
147 4 4
153 1 1
155 3 3
187 1 1
194 4 4
195 4 4
197 4 4
213 4 4
219 4 4
223 4 4
230 1 1
233 1 1
258 1 1
259 1 1
260 1 1
261 1 1
MISSING_ELSE
292 1 1
293 1 1
303 1 1
306 1 1
309 1 1
327 1 1
332 1 1
361 1 1
362 1 1
363 1 1
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
369 1 1
370 1 1
372 1 1
373 1 1
MISSING_ELSE
378 1 1
383 1 1
394 1 1
400 1 1
408 1 1
429 1 1
433 1 1
443 1 1
446 1 1
452 1 1
457 1 1
460 1 1
493 1 1
496 1 1
499 1 1
503 1 1
505 1 1
506 1 1
507 1 1
515 1 1
523 1 1
525 1 1
600 1 1
601 1 1
603 1 1
604 1 1
605 1 1
606 1 1
607 1 1
608 1 1
MISSING_ELSE
613 1 1
617 1 1
620 1 1
627 1 1
631 1 1
639 1 1
657 1 1
662 1 1
667 4 4
673 1 1
674 1 1
675 1 1
676 1 1
677 1 1
678 1 1
679 1 1
680 1 1
MISSING_ELSE
686 1 1
707 1 1
727 1 1
739 1 1
741 1 1
747 1 1
748 1 1
750 1 1
754 1 1
764 1 1
777 1 1
789 1 1
792 1 1
796 1 1
799 1 1
802 1 1


Cond Coverage for Module : flash_phy_rd
TotalCoveredPercent
Conditions45741290.15
Logical45741290.15
Non-Logical00
Event00

 LINE       141
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       141
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       141
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       141
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       142
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       142
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       142
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       142
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       147
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT2,T18,T4
01CoveredT129,T185,T142
10CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T18,T4
110Not Covered
111CoveredT129,T185,T142

 LINE       147
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       147
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT2,T18,T4
01CoveredT31,T42,T185
10CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T18,T4
110Not Covered
111CoveredT31,T42,T185

 LINE       147
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       147
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT2,T18,T4
01CoveredT185,T142,T186
10CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T18,T4
110Not Covered
111CoveredT185,T142,T186

 LINE       147
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       147
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT2,T18,T4
01CoveredT33,T58,T187
10CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T18,T4
110Not Covered
111CoveredT33,T58,T187

 LINE       147
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       155
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------
-1--2-StatusTests
01CoveredT2,T18,T4
10CoveredT1,T2,T3
11CoveredT2,T18,T4

 LINE       155
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------
-1--2-StatusTests
01CoveredT2,T18,T4
10CoveredT1,T2,T3
11CoveredT2,T18,T4

 LINE       155
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------
-1--2-StatusTests
01CoveredT2,T18,T4
10CoveredT1,T2,T3
11CoveredT2,T18,T4

 LINE       168
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------
-1-StatusTests
0CoveredT2,T18,T4
1CoveredT1,T2,T3

 LINE       168
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------
-1--2-StatusTests
00CoveredT2,T18,T4
01Not Covered
10CoveredT1,T2,T3

 LINE       168
 EXPRESSION (req_o & no_match)
             --1--   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       187
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------
-1-StatusTests
0CoveredT2,T18,T4
1CoveredT1,T2,T3

 LINE       194
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       194
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       194
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       194
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       195
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       195
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       195
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       195
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT2,T18,T4
1011111CoveredT27
1101111CoveredT5,T150,T129
1110111CoveredT2,T18,T4
1111011CoveredT185,T186,T188
1111101CoveredT189
1111110CoveredT29,T7,T86
1111111CoveredT2,T18,T4

 LINE       197
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T18,T4
10CoveredT2,T18,T4

 LINE       197
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT2,T18,T4
1011111Not Covered
1101111CoveredT5,T31,T33
1110111CoveredT2,T18,T4
1111011CoveredT186,T188,T190
1111101Not Covered
1111110CoveredT87,T191,T192
1111111CoveredT2,T18,T4

 LINE       197
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T18,T4
10CoveredT2,T18,T4

 LINE       197
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT2,T18,T4
1011111Not Covered
1101111CoveredT5,T68,T150
1110111CoveredT2,T18,T4
1111011CoveredT185,T186,T188
1111101Not Covered
1111110CoveredT7,T87,T191
1111111CoveredT2,T18,T4

 LINE       197
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T18,T4
10CoveredT2,T18,T4

 LINE       197
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT2,T18,T4
1011111CoveredT193
1101111CoveredT5,T68,T33
1110111CoveredT2,T18,T4
1111011CoveredT185,T186,T188
1111101CoveredT189
1111110CoveredT191,T192,T194
1111111CoveredT2,T18,T4

 LINE       197
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T18,T4
10CoveredT2,T18,T4

 LINE       197
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T12
101CoveredT1,T2,T3
110CoveredT29,T7,T27
111CoveredT1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T12
101CoveredT1,T2,T3
110CoveredT87,T191,T195
111CoveredT1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T12
101CoveredT1,T2,T3
110CoveredT32,T7,T87
111CoveredT1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T12
101CoveredT1,T2,T3
110CoveredT27,T191,T195
111CoveredT1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T18
101CoveredT1,T2,T3
110CoveredT29,T32,T7
111CoveredT1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T18
101CoveredT1,T2,T3
110CoveredT32,T7,T30
111CoveredT1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T18
101CoveredT1,T2,T3
110CoveredT32,T7,T30
111CoveredT1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T18
101CoveredT1,T2,T3
110CoveredT32,T30,T27
111CoveredT1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       223
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT2,T5,T6
10CoveredT2,T18,T4
11CoveredT2,T5,T6

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT5,T26,T27
010CoveredT5,T27,T68
100CoveredT2,T6,T30

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T5
11CoveredT5,T27,T68

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T17,T18
11CoveredT5,T26,T27

 LINE       223
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT2,T5,T6
10CoveredT2,T18,T4
11CoveredT2,T5,T6

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT5,T26,T27
010CoveredT5,T31,T27
100CoveredT2,T6,T30

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T5
11CoveredT5,T31,T27

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T17,T18
11CoveredT5,T26,T27

 LINE       223
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT2,T5,T6
10CoveredT2,T18,T4
11CoveredT2,T5,T6

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT5,T26,T27
010CoveredT5,T31,T27
100CoveredT2,T6,T30

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T5
11CoveredT5,T31,T27

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T17,T18
11CoveredT5,T26,T27

 LINE       223
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT2,T5,T6
10CoveredT2,T18,T4
11CoveredT2,T5,T6

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT5,T26,T27
010CoveredT5,T31,T27
100CoveredT2,T6,T30

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T5
11CoveredT5,T31,T27

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T17,T18
11CoveredT5,T26,T27

 LINE       233
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---
-1-StatusTests
0CoveredT2,T18,T4
1CoveredT1,T2,T3

 LINE       240
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---
-1--2-StatusTests
01CoveredT128,T196,T42
10CoveredT1,T2,T3
11CoveredT2,T18,T4

 LINE       240
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---
-1--2-StatusTests
01CoveredT7,T22,T68
10CoveredT1,T2,T3
11CoveredT2,T18,T4

 LINE       240
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---
-1--2-StatusTests
01CoveredT22,T128,T196
10CoveredT1,T2,T3
11CoveredT2,T18,T4

 LINE       240
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---
-1--2-StatusTests
01CoveredT7,T22,T128
10CoveredT1,T2,T3
11CoveredT2,T18,T4

 LINE       292
 EXPRESSION (req_o & ack_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT128,T196,T42
11CoveredT1,T2,T3

 LINE       293
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--
-1--2-StatusTests
01CoveredT1,T2,T18
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       303
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       306
 EXPRESSION (req_i && rdy_o)
             --1--    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T13,T14
11CoveredT1,T2,T3

 LINE       309
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       378
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       383
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

 LINE       394
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       400
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
             --------------------------------1-------------------------------   -----------2-----------   --------3-------   -----------------4-----------------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Not Covered
1101CoveredT1,T2,T3
1110CoveredT4,T13,T14
1111CoveredT1,T2,T3

 LINE       400
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---
-1-StatusTests
0CoveredT2,T18,T4
1CoveredT1,T2,T3

 LINE       400
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT4,T37,T8
111CoveredT1,T2,T3

 LINE       400
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       408
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
             --1--   --------2-------   ----3----   ------4------   ----5---   -----------------6-----------------
-1--2--3--4--5--6-StatusTests
011111CoveredT1,T2,T3
101111Not Covered
110111CoveredT8,T22,T68
111011Not Covered
111101CoveredT2,T18,T4
111110CoveredT4,T7,T37
111111CoveredT1,T2,T3

 LINE       408
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       429
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T18,T6
11CoveredT1,T2,T3

 LINE       433
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T3
11CoveredT7,T26,T28

 LINE       433
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5

 LINE       443
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------
-1--2-StatusTests
01CoveredT31,T8,T22
10CoveredT1,T2,T3
11CoveredT31,T33,T42

 LINE       452
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT29,T31,T33

 LINE       452
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT29,T42,T43
10CoveredT31,T33,T42

 LINE       457
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------
-1--2-StatusTests
01CoveredT29,T8,T22
10CoveredT1,T2,T3
11CoveredT29,T42,T43

 LINE       493
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy & addr_xor_fifo_rdy)
             ------1------   ------2------   --------3--------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT4,T37,T8
111CoveredT1,T2,T3

 LINE       496
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T18,T6
110CoveredT7,T26,T28
111CoveredT1,T2,T3

 LINE       499
 EXPRESSION (rd_done & rd_attrs.descramble & data_erased)
             ---1---   ---------2---------   -----3-----
-1--2--3-StatusTests
011Not Covered
101CoveredT128,T196,T38
110CoveredT1,T2,T3
111CoveredT7,T26,T28

 LINE       503
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT8,T72,T42
111CoveredT2,T18,T6

 LINE       505
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT2,T18,T6
11CoveredT1,T2,T3

 LINE       506
 EXPRESSION (fifo_data_valid & dropmsk_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT7,T26,T28

 LINE       507
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T18,T6

 LINE       515
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : (hint_dropmsk ? mask_valid : fifo_data_valid))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       515
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       515
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : fifo_data_valid)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T26,T28

 LINE       523
 EXPRESSION (hint_forward & (hint_dropmsk ? mask_valid : 1'b1))
             ------1-----   -----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T91,T87
11CoveredT2,T18,T6

 LINE       523
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : 1'b1)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T26,T28

 LINE       525
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       600
 EXPRESSION (req_o & ack_i & descramble_i)
             --1--   --2--   ------3-----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT42,T87,T185
110CoveredT2,T18,T6
111CoveredT1,T2,T3

 LINE       601
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----
-1--2-StatusTests
01CoveredT5,T29,T31
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       617
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T7,T37
110CoveredT7,T26,T28
111CoveredT1,T2,T3

 LINE       627
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T6

 LINE       627
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       631
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T6

 LINE       631
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------
-1-StatusTests
0CoveredT2,T18,T6
1CoveredT1,T2,T3

 LINE       639
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T18,T6

 LINE       639
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------
-1--2-StatusTests
01CoveredT2,T18,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       657
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T6

 LINE       657
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       657
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------
-1--2-StatusTests
01CoveredT2,T18,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       662
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       662
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------
-1--2-StatusTests
00CoveredT2,T18,T4
01CoveredT1,T2,T3
10Not Covered

 LINE       662
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT2,T18,T4
1110CoveredT2,T18,T4
1111CoveredT2,T18,T4

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT2,T18,T4
1110CoveredT2,T18,T4
1111CoveredT2,T18,T4

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT2,T18,T4
1110CoveredT2,T18,T4
1111CoveredT2,T18,T4

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT2,T18,T4
1110CoveredT2,T18,T4
1111CoveredT2,T18,T4

 LINE       680
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------
-1--2-StatusTests
00CoveredT2,T18,T4
01Not Covered
10Not Covered

 LINE       686
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       739
 EXPRESSION (data_err_o ? inv_data_integ : data_out_intg)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T29,T31

 LINE       750
 EXPRESSION (((|buf_rsp_match)) ? buf_addr_xor_muxed : fifo_addr_xor_muxed)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       777
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       777
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       789
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T18,T4
10CoveredT1,T2,T3

 LINE       792
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT197
10CoveredT12,T29,T31

 LINE       792
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT12,T29,T31

 LINE       792
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT1,T2,T3
100CoveredT58,T187,T154

 LINE       792
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----
-1--2-StatusTests
01Not Covered
10CoveredT2,T18,T4
11Not Covered

 LINE       796
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT12,T29,T31

Branch Coverage for Module : flash_phy_rd
Line No.TotalCoveredPercent
Branches 43 43 100.00
TERNARY 187 2 2 100.00
TERNARY 233 2 2 100.00
TERNARY 303 2 2 100.00
TERNARY 452 2 2 100.00
TERNARY 515 3 3 100.00
TERNARY 627 3 3 100.00
TERNARY 631 3 3 100.00
TERNARY 657 3 3 100.00
TERNARY 686 2 2 100.00
TERNARY 739 2 2 100.00
TERNARY 750 2 2 100.00
TERNARY 777 2 2 100.00
TERNARY 168 2 2 100.00
IF 258 3 3 100.00
IF 361 4 4 100.00
IF 603 4 4 100.00
IF 677 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 187 ((|buf_invalid_alloc)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T18,T4


LineNo. Expression -1-: 233 (no_match) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T18,T4


LineNo. Expression -1-: 303 ((|alloc)) ?

Branches:
-1-StatusTests
1 Covered T2,T18,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 452 ((data_err | ecc_single_err_o)) ?

Branches:
-1-StatusTests
1 Covered T29,T31,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 515 (hint_descram) ? -2-: 515 (hint_dropmsk) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T7,T26,T28
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 627 (forward) ? -2-: 627 (hint_descram) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T18,T6
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 631 (forward) ? -2-: 631 ((~hint_forward)) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T18,T6
0 1 Covered T1,T2,T3
0 0 Covered T2,T18,T6


LineNo. Expression -1-: 657 (forward) ? -2-: 657 (((~hint_forward) & fifo_data_ready)) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T18,T6
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 686 ((|buf_rsp_match)) ?

Branches:
-1-StatusTests
1 Covered T2,T18,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 739 (data_err_o) ?

Branches:
-1-StatusTests
1 Covered T12,T29,T31
0 Covered T1,T2,T3


LineNo. Expression -1-: 750 ((|buf_rsp_match)) ?

Branches:
-1-StatusTests
1 Covered T2,T18,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 777 (rsp_fifo_rdata.intg_ecc_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 168 (((|buf_invalid_alloc) | all_buf_dependency)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T18,T4


LineNo. Expression -1-: 258 if ((!rst_ni)) -2-: 260 if (idle_o)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 361 if ((!rst_ni)) -2-: 365 if (rd_start) -3-: 372 if (rd_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 603 if ((!rst_ni)) -2-: 605 if (calc_req_start) -3-: 607 if (calc_req_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 677 if (buf_rsp_match[i])

Branches:
-1-StatusTests
1 Covered T2,T18,T4
0 Covered T1,T2,T3


Assert Coverage for Module : flash_phy_rd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 11 11 100.00 11 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 11 11 100.00 11 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferMatchEcc_A 770050552 1613886 0 0
ExclusiveOps_A 770050552 768445004 0 0
ExclusiveProgHazard_A 770050552 768445004 0 0
ExclusiveState_A 770050552 768445004 0 0
ForwardCheck_A 770050552 4482013 0 0
IdleCheck_A 770050552 102556701 0 0
MaxBufs_A 2072 2072 0 0
OneHotAlloc_A 770050552 768445004 0 0
OneHotMatch_A 770050552 768445004 0 0
OneHotRspMatch_A 770050552 768445004 0 0
OneHotUpdate_A 770050552 768445004 0 0


BufferMatchEcc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 770050552 1613886 0 0
T2 677442 393 0 0
T3 6270 0 0 0
T4 300864 11962 0 0
T5 229244 864 0 0
T6 0 464 0 0
T7 0 1736 0 0
T12 2124 0 0 0
T13 1218 8 0 0
T14 1420 15 0 0
T17 7272 0 0 0
T18 5372 9 0 0
T19 6168 0 0 0
T29 0 17 0 0
T30 0 84 0 0
T31 0 34 0 0
T32 0 153 0 0
T37 0 2724 0 0
T47 0 5 0 0

ExclusiveOps_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 770050552 768445004 0 0
T1 3116 2940 0 0
T2 677442 677260 0 0
T3 6270 6126 0 0
T4 300864 300594 0 0
T5 229244 218564 0 0
T12 2124 1676 0 0
T13 1218 1096 0 0
T17 7272 5804 0 0
T18 5372 5234 0 0
T19 6168 6020 0 0

ExclusiveProgHazard_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 770050552 768445004 0 0
T1 3116 2940 0 0
T2 677442 677260 0 0
T3 6270 6126 0 0
T4 300864 300594 0 0
T5 229244 218564 0 0
T12 2124 1676 0 0
T13 1218 1096 0 0
T17 7272 5804 0 0
T18 5372 5234 0 0
T19 6168 6020 0 0

ExclusiveState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 770050552 768445004 0 0
T1 3116 2940 0 0
T2 677442 677260 0 0
T3 6270 6126 0 0
T4 300864 300594 0 0
T5 229244 218564 0 0
T12 2124 1676 0 0
T13 1218 1096 0 0
T17 7272 5804 0 0
T18 5372 5234 0 0
T19 6168 6020 0 0

ForwardCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 770050552 4482013 0 0
T2 677442 461 0 0
T3 6270 0 0 0
T4 300864 0 0 0
T5 229244 0 0 0
T6 0 543 0 0
T7 0 18913 0 0
T8 0 17227 0 0
T12 2124 0 0 0
T13 1218 0 0 0
T14 1420 0 0 0
T17 7272 0 0 0
T18 5372 12 0 0
T19 6168 0 0 0
T22 0 17519 0 0
T26 0 41844 0 0
T27 0 84 0 0
T29 0 3 0 0
T30 0 168 0 0
T47 0 12 0 0
T68 0 31 0 0

IdleCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 770050552 102556701 0 0
T1 1558 128 0 0
T2 677442 1443 0 0
T3 6270 128 0 0
T4 300864 124814 0 0
T5 229244 13024 0 0
T6 0 667 0 0
T7 0 18967 0 0
T12 2124 268 0 0
T13 1218 176 0 0
T14 710 83 0 0
T17 7272 512 0 0
T18 5372 161 0 0
T19 6168 128 0 0
T29 0 40 0 0
T31 0 48 0 0
T32 0 174 0 0
T37 0 32281 0 0

MaxBufs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2072 2072 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T12 2 2 0 0
T13 2 2 0 0
T17 2 2 0 0
T18 2 2 0 0
T19 2 2 0 0

OneHotAlloc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 770050552 768445004 0 0
T1 3116 2940 0 0
T2 677442 677260 0 0
T3 6270 6126 0 0
T4 300864 300594 0 0
T5 229244 218564 0 0
T12 2124 1676 0 0
T13 1218 1096 0 0
T17 7272 5804 0 0
T18 5372 5234 0 0
T19 6168 6020 0 0

OneHotMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 770050552 768445004 0 0
T1 3116 2940 0 0
T2 677442 677260 0 0
T3 6270 6126 0 0
T4 300864 300594 0 0
T5 229244 218564 0 0
T12 2124 1676 0 0
T13 1218 1096 0 0
T17 7272 5804 0 0
T18 5372 5234 0 0
T19 6168 6020 0 0

OneHotRspMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 770050552 768445004 0 0
T1 3116 2940 0 0
T2 677442 677260 0 0
T3 6270 6126 0 0
T4 300864 300594 0 0
T5 229244 218564 0 0
T12 2124 1676 0 0
T13 1218 1096 0 0
T17 7272 5804 0 0
T18 5372 5234 0 0
T19 6168 6020 0 0

OneHotUpdate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 770050552 768445004 0 0
T1 3116 2940 0 0
T2 677442 677260 0 0
T3 6270 6126 0 0
T4 300864 300594 0 0
T5 229244 218564 0 0
T12 2124 1676 0 0
T13 1218 1096 0 0
T17 7272 5804 0 0
T18 5372 5234 0 0
T19 6168 6020 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
Line No.TotalCoveredPercent
TOTAL133133100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN21911100.00
CONT_ASSIGN21911100.00
CONT_ASSIGN21911100.00
CONT_ASSIGN21911100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN23011100.00
CONT_ASSIGN23311100.00
ALWAYS25844100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN30311100.00
CONT_ASSIGN30611100.00
CONT_ASSIGN30911100.00
CONT_ASSIGN32711100.00
CONT_ASSIGN33211100.00
ALWAYS3611212100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN38311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN40011100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN42911100.00
CONT_ASSIGN43311100.00
CONT_ASSIGN44311100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN45211100.00
CONT_ASSIGN45711100.00
CONT_ASSIGN46011100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49911100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50511100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN51511100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN52511100.00
CONT_ASSIGN60011100.00
CONT_ASSIGN60111100.00
ALWAYS60366100.00
CONT_ASSIGN61311100.00
CONT_ASSIGN61711100.00
CONT_ASSIGN62011100.00
CONT_ASSIGN62711100.00
CONT_ASSIGN63111100.00
CONT_ASSIGN63911100.00
CONT_ASSIGN65711100.00
CONT_ASSIGN66211100.00
CONT_ASSIGN66711100.00
CONT_ASSIGN66711100.00
CONT_ASSIGN66711100.00
CONT_ASSIGN66711100.00
ALWAYS67388100.00
CONT_ASSIGN68611100.00
CONT_ASSIGN70711100.00
CONT_ASSIGN72711100.00
CONT_ASSIGN73911100.00
CONT_ASSIGN74111100.00
CONT_ASSIGN74711100.00
CONT_ASSIGN74811100.00
CONT_ASSIGN75011100.00
CONT_ASSIGN75411100.00
CONT_ASSIGN76411100.00
CONT_ASSIGN77711100.00
CONT_ASSIGN78911100.00
CONT_ASSIGN79211100.00
CONT_ASSIGN79611100.00
CONT_ASSIGN79911100.00
CONT_ASSIGN80211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
138 1 1
141 4 4
142 4 4
147 4 4
153 1 1
155 3 3
187 1 1
194 4 4
195 4 4
197 4 4
213 4 4
219 4 4
223 4 4
230 1 1
233 1 1
258 1 1
259 1 1
260 1 1
261 1 1
MISSING_ELSE
292 1 1
293 1 1
303 1 1
306 1 1
309 1 1
327 1 1
332 1 1
361 1 1
362 1 1
363 1 1
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
369 1 1
370 1 1
372 1 1
373 1 1
MISSING_ELSE
378 1 1
383 1 1
394 1 1
400 1 1
408 1 1
429 1 1
433 1 1
443 1 1
446 1 1
452 1 1
457 1 1
460 1 1
493 1 1
496 1 1
499 1 1
503 1 1
505 1 1
506 1 1
507 1 1
515 1 1
523 1 1
525 1 1
600 1 1
601 1 1
603 1 1
604 1 1
605 1 1
606 1 1
607 1 1
608 1 1
MISSING_ELSE
613 1 1
617 1 1
620 1 1
627 1 1
631 1 1
639 1 1
657 1 1
662 1 1
667 4 4
673 1 1
674 1 1
675 1 1
676 1 1
677 1 1
678 1 1
679 1 1
680 1 1
MISSING_ELSE
686 1 1
707 1 1
727 1 1
739 1 1
741 1 1
747 1 1
748 1 1
750 1 1
754 1 1
764 1 1
777 1 1
789 1 1
792 1 1
796 1 1
799 1 1
802 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
TotalCoveredPercent
Conditions45740989.50
Logical45740989.50
Non-Logical00
Event00

 LINE       141
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       141
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       141
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       141
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       142
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       142
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       142
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       142
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       147
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT2,T18,T4
01CoveredT129,T185,T142
10CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T18,T4
110Not Covered
111CoveredT129,T185,T142

 LINE       147
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       147
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT2,T18,T4
01CoveredT42,T185,T186
10CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T18,T4
110Not Covered
111CoveredT42,T185,T186

 LINE       147
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       147
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT2,T18,T4
01CoveredT185,T142,T186
10CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T18,T4
110Not Covered
111CoveredT185,T142,T186

 LINE       147
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       147
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT2,T18,T4
01CoveredT185,T186,T188
10CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T18,T4
110Not Covered
111CoveredT185,T186,T188

 LINE       147
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       155
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------
-1--2-StatusTests
01CoveredT2,T18,T4
10CoveredT1,T2,T3
11CoveredT2,T18,T4

 LINE       155
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------
-1--2-StatusTests
01CoveredT2,T18,T4
10CoveredT1,T2,T3
11CoveredT2,T18,T4

 LINE       155
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------
-1--2-StatusTests
01CoveredT2,T18,T4
10CoveredT1,T2,T3
11CoveredT2,T18,T4

 LINE       168
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------
-1-StatusTests
0CoveredT2,T18,T4
1CoveredT1,T2,T3

 LINE       168
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------
-1--2-StatusTests
00CoveredT2,T18,T4
01Not Covered
10CoveredT1,T2,T3

 LINE       168
 EXPRESSION (req_o & no_match)
             --1--   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T18,T4

 LINE       187
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------
-1-StatusTests
0CoveredT2,T18,T4
1CoveredT1,T2,T3

 LINE       194
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       194
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       194
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       194
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       195
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       195
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       195
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       195
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT2,T18,T4
1011111CoveredT27
1101111CoveredT135,T198
1110111CoveredT2,T18,T4
1111011CoveredT185,T186,T188
1111101Not Covered
1111110CoveredT29,T191,T194
1111111CoveredT2,T18,T4

 LINE       197
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T18,T4
10CoveredT2,T18,T4

 LINE       197
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT2,T18,T4
1011111Not Covered
1101111CoveredT122,T199,T95
1110111CoveredT2,T18,T4
1111011CoveredT188,T200,T201
1111101Not Covered
1111110CoveredT192,T202,T203
1111111CoveredT2,T18,T4

 LINE       197
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T18,T4
10CoveredT2,T18,T4

 LINE       197
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT2,T18,T4
1011111Not Covered
1101111CoveredT68,T122,T199
1110111CoveredT2,T18,T4
1111011CoveredT185,T186,T190
1111101Not Covered
1111110CoveredT87,T191,T204
1111111CoveredT2,T18,T4

 LINE       197
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T18,T4
10CoveredT2,T18,T4

 LINE       197
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT2,T18,T4
1011111CoveredT193
1101111CoveredT68,T122,T199
1110111CoveredT2,T18,T4
1111011CoveredT185,T186,T201
1111101Not Covered
1111110CoveredT205,T206,T207
1111111CoveredT2,T18,T4

 LINE       197
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T18,T4
10CoveredT2,T18,T4

 LINE       197
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T12
101CoveredT1,T2,T3
110CoveredT29,T27,T191
111CoveredT1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T12
101CoveredT1,T2,T3
110CoveredT195,T192,T202
111CoveredT1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T12
101CoveredT1,T2,T3
110CoveredT32,T87,T191
111CoveredT1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T12
101CoveredT1,T2,T3
110CoveredT27,T195,T208
111CoveredT1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T18
101CoveredT1,T2,T3
110CoveredT29,T32,T7
111CoveredT1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T18
101CoveredT1,T2,T3
110CoveredT32,T30,T87
111CoveredT1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T18
101CoveredT1,T2,T3
110CoveredT32,T30,T87
111CoveredT1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T18
101CoveredT1,T2,T3
110CoveredT32,T30,T27
111CoveredT1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       223
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT2,T6,T27
10CoveredT2,T18,T4
11CoveredT2,T6,T27

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT156,T122,T157
010CoveredT68,T156,T38
100CoveredT2,T6,T27

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T6
11CoveredT68,T156,T38

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T30
11CoveredT156,T122,T157

 LINE       223
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT2,T6,T27
10CoveredT2,T18,T4
11CoveredT2,T6,T27

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT27,T156,T122
010CoveredT27,T68,T156
100CoveredT2,T6,T27

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T6
11CoveredT27,T68,T156

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T30
11CoveredT27,T156,T122

 LINE       223
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT2,T6,T27
10CoveredT2,T18,T4
11CoveredT2,T6,T27

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT27,T156,T122
010CoveredT27,T68,T156
100CoveredT2,T6,T27

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T6
11CoveredT27,T68,T156

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T30
11CoveredT27,T156,T122

 LINE       223
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT2,T6,T27
10CoveredT2,T18,T4
11CoveredT2,T6,T27

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT156,T122,T157
010CoveredT68,T156,T38
100CoveredT2,T6,T27

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T6
11CoveredT68,T156,T38

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T30
11CoveredT156,T122,T157

 LINE       233
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---
-1-StatusTests
0CoveredT2,T18,T4
1CoveredT1,T2,T3

 LINE       240
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---
-1--2-StatusTests
01CoveredT87,T185,T209
10CoveredT1,T2,T3
11CoveredT2,T18,T4

 LINE       240
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---
-1--2-StatusTests
01CoveredT210,T42,T24
10CoveredT1,T2,T3
11CoveredT2,T18,T4

 LINE       240
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---
-1--2-StatusTests
01CoveredT210,T87,T45
10CoveredT1,T2,T3
11CoveredT2,T18,T4

 LINE       240
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---
-1--2-StatusTests
01CoveredT7,T22,T87
10CoveredT1,T2,T3
11CoveredT2,T18,T4

 LINE       292
 EXPRESSION (req_o & ack_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT87,T185,T209
11CoveredT2,T18,T4

 LINE       293
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--
-1--2-StatusTests
01CoveredT1,T2,T6
10CoveredT2,T18,T4
11CoveredT2,T18,T4

 LINE       303
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       306
 EXPRESSION (req_i && rdy_o)
             --1--    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T14,T29
11CoveredT2,T18,T4

 LINE       309
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT2,T18,T4
11CoveredT2,T18,T4

 LINE       378
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---
-1--2-StatusTests
00CoveredT2,T18,T4
01CoveredT2,T18,T4
10CoveredT1,T2,T3

 LINE       383
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

 LINE       394
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       400
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
             --------------------------------1-------------------------------   -----------2-----------   --------3-------   -----------------4-----------------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Not Covered
1101CoveredT1,T2,T3
1110CoveredT4,T14,T29
1111CoveredT1,T2,T3

 LINE       400
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---
-1-StatusTests
0CoveredT2,T18,T4
1CoveredT1,T2,T3

 LINE       400
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T18,T4
110CoveredT4,T37,T68
111CoveredT1,T2,T3

 LINE       400
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T14,T29

 LINE       408
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
             --1--   --------2-------   ----3----   ------4------   ----5---   -----------------6-----------------
-1--2--3--4--5--6-StatusTests
011111CoveredT1,T2,T3
101111Not Covered
110111CoveredT8,T22,T72
111011Not Covered
111101CoveredT2,T18,T4
111110CoveredT4,T7,T37
111111CoveredT2,T18,T4

 LINE       408
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T14,T29

 LINE       429
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----
-1--2-StatusTests
01CoveredT4,T14,T29
10CoveredT2,T18,T6
11CoveredT4,T14,T29

 LINE       433
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------
-1--2-StatusTests
01CoveredT1,T2,T6
10CoveredT2,T18,T4
11CoveredT7,T38,T91

 LINE       433
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T6

 LINE       443
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------
-1--2-StatusTests
01CoveredT22,T68,T33
10CoveredT4,T14,T29
11CoveredT42,T129,T185

 LINE       452
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT42,T43,T44

 LINE       452
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT42,T43,T44
10CoveredT42,T129,T185

 LINE       457
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------
-1--2-StatusTests
01CoveredT22,T68,T33
10CoveredT4,T14,T29
11CoveredT42,T43,T44

 LINE       493
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy & addr_xor_fifo_rdy)
             ------1------   ------2------   --------3--------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT4,T37,T68
111CoveredT1,T2,T3

 LINE       496
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------
-1--2--3-StatusTests
011CoveredT4,T14,T29
101CoveredT2,T18,T6
110CoveredT7,T91,T87
111CoveredT4,T14,T29

 LINE       499
 EXPRESSION (rd_done & rd_attrs.descramble & data_erased)
             ---1---   ---------2---------   -----3-----
-1--2--3-StatusTests
011Not Covered
101CoveredT38,T87,T122
110CoveredT4,T14,T29
111CoveredT7,T91,T87

 LINE       503
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T14,T29
110CoveredT72,T42,T185
111CoveredT2,T18,T6

 LINE       505
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT2,T18,T6
11CoveredT4,T14,T29

 LINE       506
 EXPRESSION (fifo_data_valid & dropmsk_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT2,T18,T4
11CoveredT7,T91,T87

 LINE       507
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT4,T14,T29
11CoveredT2,T18,T6

 LINE       515
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : (hint_dropmsk ? mask_valid : fifo_data_valid))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T14,T29

 LINE       515
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------
-1--2-StatusTests
01Not Covered
10CoveredT4,T14,T29
11CoveredT4,T14,T29

 LINE       515
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : fifo_data_valid)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T91,T87

 LINE       523
 EXPRESSION (hint_forward & (hint_dropmsk ? mask_valid : 1'b1))
             ------1-----   -----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T91,T87
11CoveredT2,T18,T6

 LINE       523
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : 1'b1)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T91,T87

 LINE       525
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT4,T14,T29

 LINE       600
 EXPRESSION (req_o & ack_i & descramble_i)
             --1--   --2--   ------3-----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT87,T185,T211
110CoveredT2,T18,T6
111CoveredT4,T14,T29

 LINE       601
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----
-1--2-StatusTests
01CoveredT27,T156,T42
10CoveredT4,T14,T29
11CoveredT4,T14,T29

 LINE       617
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T37,T42
110CoveredT7,T91,T87
111CoveredT4,T14,T29

 LINE       627
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T6

 LINE       627
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T14,T29

 LINE       631
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T6

 LINE       631
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------
-1-StatusTests
0CoveredT2,T18,T6
1CoveredT1,T2,T3

 LINE       639
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T14,T29
10CoveredT2,T18,T6

 LINE       639
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------
-1--2-StatusTests
01CoveredT2,T18,T6
10CoveredT1,T2,T3
11CoveredT4,T14,T29

 LINE       657
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T6

 LINE       657
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T14,T29

 LINE       657
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------
-1--2-StatusTests
01CoveredT2,T18,T6
10CoveredT1,T2,T3
11CoveredT4,T14,T29

 LINE       662
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------
-1--2--3-StatusTests
011Not Covered
101CoveredT27,T156,T157
110Not Covered
111CoveredT2,T18,T4

 LINE       662
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------
-1--2-StatusTests
00CoveredT2,T18,T4
01CoveredT1,T2,T3
10Not Covered

 LINE       662
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT2,T18,T4
1110CoveredT2,T18,T4
1111CoveredT2,T18,T4

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT2,T18,T4
1110CoveredT2,T18,T4
1111CoveredT2,T18,T4

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT2,T18,T4
1110CoveredT2,T18,T4
1111CoveredT2,T18,T4

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT2,T18,T4
1110CoveredT2,T18,T4
1111CoveredT2,T18,T4

 LINE       680
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------
-1--2-StatusTests
00CoveredT2,T18,T4
01Not Covered
10Not Covered

 LINE       686
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       739
 EXPRESSION (data_err_o ? inv_data_integ : data_out_intg)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT42,T43,T129

 LINE       750
 EXPRESSION (((|buf_rsp_match)) ? buf_addr_xor_muxed : fifo_addr_xor_muxed)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T4

 LINE       777
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T14,T29

 LINE       777
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------
-1-StatusTests
0CoveredT4,T14,T29
1CoveredT4,T14,T29

 LINE       789
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T18,T4
10CoveredT2,T18,T4

 LINE       792
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT42,T43,T129

 LINE       792
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT4,T14,T29
10CoveredT2,T18,T4
11CoveredT42,T43,T129

 LINE       792
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT4,T14,T29
100CoveredT185,T186,T212

 LINE       792
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----
-1--2-StatusTests
01Not Covered
10CoveredT2,T18,T4
11Not Covered

 LINE       796
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---
-1--2-StatusTests
01CoveredT4,T14,T29
10CoveredT2,T18,T4
11CoveredT42,T43,T129

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
Line No.TotalCoveredPercent
Branches 43 43 100.00
TERNARY 187 2 2 100.00
TERNARY 233 2 2 100.00
TERNARY 303 2 2 100.00
TERNARY 452 2 2 100.00
TERNARY 515 3 3 100.00
TERNARY 627 3 3 100.00
TERNARY 631 3 3 100.00
TERNARY 657 3 3 100.00
TERNARY 686 2 2 100.00
TERNARY 739 2 2 100.00
TERNARY 750 2 2 100.00
TERNARY 777 2 2 100.00
TERNARY 168 2 2 100.00
IF 258 3 3 100.00
IF 361 4 4 100.00
IF 603 4 4 100.00
IF 677 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 187 ((|buf_invalid_alloc)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T18,T4


LineNo. Expression -1-: 233 (no_match) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T18,T4


LineNo. Expression -1-: 303 ((|alloc)) ?

Branches:
-1-StatusTests
1 Covered T2,T18,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 452 ((data_err | ecc_single_err_o)) ?

Branches:
-1-StatusTests
1 Covered T42,T43,T44
0 Covered T1,T2,T3


LineNo. Expression -1-: 515 (hint_descram) ? -2-: 515 (hint_dropmsk) ?

Branches:
-1--2-StatusTests
1 - Covered T4,T14,T29
0 1 Covered T7,T91,T87
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 627 (forward) ? -2-: 627 (hint_descram) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T18,T6
0 1 Covered T4,T14,T29
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 631 (forward) ? -2-: 631 ((~hint_forward)) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T18,T6
0 1 Covered T1,T2,T3
0 0 Covered T2,T18,T6


LineNo. Expression -1-: 657 (forward) ? -2-: 657 (((~hint_forward) & fifo_data_ready)) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T18,T6
0 1 Covered T4,T14,T29
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 686 ((|buf_rsp_match)) ?

Branches:
-1-StatusTests
1 Covered T2,T18,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 739 (data_err_o) ?

Branches:
-1-StatusTests
1 Covered T42,T43,T129
0 Covered T1,T2,T3


LineNo. Expression -1-: 750 ((|buf_rsp_match)) ?

Branches:
-1-StatusTests
1 Covered T2,T18,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 777 (rsp_fifo_rdata.intg_ecc_en) ?

Branches:
-1-StatusTests
1 Covered T4,T14,T29
0 Covered T1,T2,T3


LineNo. Expression -1-: 168 (((|buf_invalid_alloc) | all_buf_dependency)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T18,T4


LineNo. Expression -1-: 258 if ((!rst_ni)) -2-: 260 if (idle_o)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T2,T18,T4


LineNo. Expression -1-: 361 if ((!rst_ni)) -2-: 365 if (rd_start) -3-: 372 if (rd_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T18,T4
0 0 1 Covered T2,T18,T4
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 603 if ((!rst_ni)) -2-: 605 if (calc_req_start) -3-: 607 if (calc_req_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T4,T14,T29
0 0 1 Covered T4,T14,T29
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 677 if (buf_rsp_match[i])

Branches:
-1-StatusTests
1 Covered T2,T18,T4
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 11 11 100.00 11 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 11 11 100.00 11 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferMatchEcc_A 385025276 642395 0 0
ExclusiveOps_A 385025276 384222502 0 0
ExclusiveProgHazard_A 385025276 384222502 0 0
ExclusiveState_A 385025276 384222502 0 0
ForwardCheck_A 385025276 1845572 0 0
IdleCheck_A 385025276 49039658 0 0
MaxBufs_A 1036 1036 0 0
OneHotAlloc_A 385025276 384222502 0 0
OneHotMatch_A 385025276 384222502 0 0
OneHotRspMatch_A 385025276 384222502 0 0
OneHotUpdate_A 385025276 384222502 0 0


BufferMatchEcc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385025276 642395 0 0
T2 338721 230 0 0
T3 3135 0 0 0
T4 150432 5232 0 0
T5 114622 0 0 0
T6 0 199 0 0
T7 0 729 0 0
T12 1062 0 0 0
T13 609 0 0 0
T14 710 15 0 0
T17 3636 0 0 0
T18 2686 9 0 0
T19 3084 0 0 0
T30 0 84 0 0
T31 0 8 0 0
T32 0 38 0 0
T47 0 5 0 0

ExclusiveOps_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385025276 384222502 0 0
T1 1558 1470 0 0
T2 338721 338630 0 0
T3 3135 3063 0 0
T4 150432 150297 0 0
T5 114622 109282 0 0
T12 1062 838 0 0
T13 609 548 0 0
T17 3636 2902 0 0
T18 2686 2617 0 0
T19 3084 3010 0 0

ExclusiveProgHazard_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385025276 384222502 0 0
T1 1558 1470 0 0
T2 338721 338630 0 0
T3 3135 3063 0 0
T4 150432 150297 0 0
T5 114622 109282 0 0
T12 1062 838 0 0
T13 609 548 0 0
T17 3636 2902 0 0
T18 2686 2617 0 0
T19 3084 3010 0 0

ExclusiveState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385025276 384222502 0 0
T1 1558 1470 0 0
T2 338721 338630 0 0
T3 3135 3063 0 0
T4 150432 150297 0 0
T5 114622 109282 0 0
T12 1062 838 0 0
T13 609 548 0 0
T17 3636 2902 0 0
T18 2686 2617 0 0
T19 3084 3010 0 0

ForwardCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385025276 1845572 0 0
T2 338721 273 0 0
T3 3135 0 0 0
T4 150432 0 0 0
T5 114622 0 0 0
T6 0 234 0 0
T7 0 9119 0 0
T8 0 8184 0 0
T12 1062 0 0 0
T13 609 0 0 0
T14 710 0 0 0
T17 3636 0 0 0
T18 2686 12 0 0
T19 3084 0 0 0
T22 0 8415 0 0
T27 0 40 0 0
T30 0 102 0 0
T47 0 8 0 0
T68 0 31 0 0

IdleCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385025276 49039658 0 0
T2 338721 776 0 0
T3 3135 0 0 0
T4 150432 59890 0 0
T5 114622 0 0 0
T6 0 667 0 0
T7 0 18967 0 0
T12 1062 0 0 0
T13 609 0 0 0
T14 710 83 0 0
T17 3636 0 0 0
T18 2686 33 0 0
T19 3084 0 0 0
T29 0 40 0 0
T31 0 48 0 0
T32 0 174 0 0
T37 0 32281 0 0

MaxBufs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1036 1036 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

OneHotAlloc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385025276 384222502 0 0
T1 1558 1470 0 0
T2 338721 338630 0 0
T3 3135 3063 0 0
T4 150432 150297 0 0
T5 114622 109282 0 0
T12 1062 838 0 0
T13 609 548 0 0
T17 3636 2902 0 0
T18 2686 2617 0 0
T19 3084 3010 0 0

OneHotMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385025276 384222502 0 0
T1 1558 1470 0 0
T2 338721 338630 0 0
T3 3135 3063 0 0
T4 150432 150297 0 0
T5 114622 109282 0 0
T12 1062 838 0 0
T13 609 548 0 0
T17 3636 2902 0 0
T18 2686 2617 0 0
T19 3084 3010 0 0

OneHotRspMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385025276 384222502 0 0
T1 1558 1470 0 0
T2 338721 338630 0 0
T3 3135 3063 0 0
T4 150432 150297 0 0
T5 114622 109282 0 0
T12 1062 838 0 0
T13 609 548 0 0
T17 3636 2902 0 0
T18 2686 2617 0 0
T19 3084 3010 0 0

OneHotUpdate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385025276 384222502 0 0
T1 1558 1470 0 0
T2 338721 338630 0 0
T3 3135 3063 0 0
T4 150432 150297 0 0
T5 114622 109282 0 0
T12 1062 838 0 0
T13 609 548 0 0
T17 3636 2902 0 0
T18 2686 2617 0 0
T19 3084 3010 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
Line No.TotalCoveredPercent
TOTAL133133100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN21911100.00
CONT_ASSIGN21911100.00
CONT_ASSIGN21911100.00
CONT_ASSIGN21911100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN23011100.00
CONT_ASSIGN23311100.00
ALWAYS25844100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN30311100.00
CONT_ASSIGN30611100.00
CONT_ASSIGN30911100.00
CONT_ASSIGN32711100.00
CONT_ASSIGN33211100.00
ALWAYS3611212100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN38311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN40011100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN42911100.00
CONT_ASSIGN43311100.00
CONT_ASSIGN44311100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN45211100.00
CONT_ASSIGN45711100.00
CONT_ASSIGN46011100.00
CONT_ASSIGN49311100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49911100.00
CONT_ASSIGN50311100.00
CONT_ASSIGN50511100.00
CONT_ASSIGN50611100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN51511100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN52511100.00
CONT_ASSIGN60011100.00
CONT_ASSIGN60111100.00
ALWAYS60366100.00
CONT_ASSIGN61311100.00
CONT_ASSIGN61711100.00
CONT_ASSIGN62011100.00
CONT_ASSIGN62711100.00
CONT_ASSIGN63111100.00
CONT_ASSIGN63911100.00
CONT_ASSIGN65711100.00
CONT_ASSIGN66211100.00
CONT_ASSIGN66711100.00
CONT_ASSIGN66711100.00
CONT_ASSIGN66711100.00
CONT_ASSIGN66711100.00
ALWAYS67388100.00
CONT_ASSIGN68611100.00
CONT_ASSIGN70711100.00
CONT_ASSIGN72711100.00
CONT_ASSIGN73911100.00
CONT_ASSIGN74111100.00
CONT_ASSIGN74711100.00
CONT_ASSIGN74811100.00
CONT_ASSIGN75011100.00
CONT_ASSIGN75411100.00
CONT_ASSIGN76411100.00
CONT_ASSIGN77711100.00
CONT_ASSIGN78911100.00
CONT_ASSIGN79211100.00
CONT_ASSIGN79611100.00
CONT_ASSIGN79911100.00
CONT_ASSIGN80211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
138 1 1
141 4 4
142 4 4
147 4 4
153 1 1
155 3 3
187 1 1
194 4 4
195 4 4
197 4 4
213 4 4
219 4 4
223 4 4
230 1 1
233 1 1
258 1 1
259 1 1
260 1 1
261 1 1
MISSING_ELSE
292 1 1
293 1 1
303 1 1
306 1 1
309 1 1
327 1 1
332 1 1
361 1 1
362 1 1
363 1 1
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
369 1 1
370 1 1
372 1 1
373 1 1
MISSING_ELSE
378 1 1
383 1 1
394 1 1
400 1 1
408 1 1
429 1 1
433 1 1
443 1 1
446 1 1
452 1 1
457 1 1
460 1 1
493 1 1
496 1 1
499 1 1
503 1 1
505 1 1
506 1 1
507 1 1
515 1 1
523 1 1
525 1 1
600 1 1
601 1 1
603 1 1
604 1 1
605 1 1
606 1 1
607 1 1
608 1 1
MISSING_ELSE
613 1 1
617 1 1
620 1 1
627 1 1
631 1 1
639 1 1
657 1 1
662 1 1
667 4 4
673 1 1
674 1 1
675 1 1
676 1 1
677 1 1
678 1 1
679 1 1
680 1 1
MISSING_ELSE
686 1 1
707 1 1
727 1 1
739 1 1
741 1 1
747 1 1
748 1 1
750 1 1
754 1 1
764 1 1
777 1 1
789 1 1
792 1 1
796 1 1
799 1 1
802 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
TotalCoveredPercent
Conditions45741089.72
Logical45741089.72
Non-Logical00
Event00

 LINE       141
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T5

 LINE       141
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T5

 LINE       141
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T5

 LINE       141
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T5

 LINE       142
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T5

 LINE       142
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T5

 LINE       142
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T5

 LINE       142
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T5

 LINE       147
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT2,T4,T5
01CoveredT185,T186,T213
10CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T4,T5
110Not Covered
111CoveredT185,T186,T213

 LINE       147
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T5

 LINE       147
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT2,T4,T5
01CoveredT31,T185,T214
10CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T4,T5
110Not Covered
111CoveredT31,T185,T214

 LINE       147
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T5

 LINE       147
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT2,T4,T5
01CoveredT185,T186,T188
10CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T4,T5
110Not Covered
111CoveredT185,T186,T188

 LINE       147
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T5

 LINE       147
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT2,T4,T5
01CoveredT33,T58,T187
10CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       147
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T4,T5
110Not Covered
111CoveredT33,T58,T187

 LINE       147
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T5

 LINE       155
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------
-1--2-StatusTests
01CoveredT2,T4,T5
10CoveredT1,T2,T3
11CoveredT2,T4,T5

 LINE       155
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------
-1--2-StatusTests
01CoveredT2,T4,T5
10CoveredT1,T2,T3
11CoveredT2,T4,T5

 LINE       155
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------
-1--2-StatusTests
01CoveredT2,T4,T5
10CoveredT1,T2,T3
11CoveredT2,T4,T5

 LINE       168
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------
-1-StatusTests
0CoveredT2,T4,T5
1CoveredT1,T2,T3

 LINE       168
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------
-1--2-StatusTests
00CoveredT2,T4,T5
01Not Covered
10CoveredT1,T2,T3

 LINE       168
 EXPRESSION (req_o & no_match)
             --1--   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       187
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------
-1-StatusTests
0CoveredT2,T4,T5
1CoveredT1,T2,T3

 LINE       194
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       194
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       194
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       194
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       195
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       195
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       195
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       195
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT2,T4,T5
1011111Not Covered
1101111CoveredT5,T150,T129
1110111CoveredT2,T4,T5
1111011CoveredT185,T190,T200
1111101CoveredT189
1111110CoveredT7,T86,T204
1111111CoveredT2,T4,T5

 LINE       197
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T5
10CoveredT2,T4,T5

 LINE       197
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT2,T4,T5
1011111Not Covered
1101111CoveredT5,T31,T33
1110111CoveredT2,T4,T5
1111011CoveredT186,T188,T190
1111101Not Covered
1111110CoveredT87,T191,T194
1111111CoveredT2,T4,T5

 LINE       197
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T5
10CoveredT2,T4,T5

 LINE       197
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT2,T4,T5
1011111Not Covered
1101111CoveredT5,T150,T129
1110111CoveredT2,T4,T5
1111011CoveredT185,T188,T200
1111101Not Covered
1111110CoveredT7,T202,T203
1111111CoveredT2,T4,T5

 LINE       197
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T5
10CoveredT2,T4,T5

 LINE       197
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       197
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT2,T4,T5
1011111Not Covered
1101111CoveredT5,T68,T33
1110111CoveredT2,T4,T5
1111011CoveredT185,T186,T188
1111101CoveredT189
1111110CoveredT191,T192,T194
1111111CoveredT2,T4,T5

 LINE       197
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T5
10CoveredT2,T4,T5

 LINE       197
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T12
101CoveredT1,T2,T3
110CoveredT7,T86,T195
111CoveredT1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T12
101CoveredT1,T2,T3
110CoveredT87,T191,T195
111CoveredT1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T12
101CoveredT1,T2,T3
110CoveredT7,T195,T202
111CoveredT1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       213
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T12
101CoveredT1,T2,T3
110CoveredT191,T195,T192
111CoveredT1,T2,T3

 LINE       213
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T18
101CoveredT1,T2,T3
110CoveredT32,T7,T30
111CoveredT1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T18
101CoveredT1,T2,T3
110CoveredT32,T7,T30
111CoveredT1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T18
101CoveredT1,T2,T3
110CoveredT32,T7,T30
111CoveredT1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       219
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T18
101CoveredT1,T2,T3
110CoveredT32,T30,T22
111CoveredT1,T2,T3

 LINE       219
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       223
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT2,T5,T6
10CoveredT2,T4,T5
11CoveredT2,T5,T6

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT5,T26,T27
010CoveredT5,T27,T68
100CoveredT2,T6,T30

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T5,T6
11CoveredT5,T27,T68

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T17,T18
11CoveredT5,T26,T27

 LINE       223
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT2,T5,T6
10CoveredT2,T4,T5
11CoveredT2,T5,T6

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT5,T26,T27
010CoveredT5,T31,T27
100CoveredT2,T6,T30

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T5,T6
11CoveredT5,T31,T27

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T17,T18
11CoveredT5,T26,T27

 LINE       223
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT2,T5,T6
10CoveredT2,T4,T5
11CoveredT2,T5,T6

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT5,T26,T27
010CoveredT5,T31,T27
100CoveredT2,T6,T30

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T5,T6
11CoveredT5,T31,T27

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T17,T18
11CoveredT5,T26,T27

 LINE       223
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT2,T5,T6
10CoveredT2,T4,T5
11CoveredT2,T5,T6

 LINE       223
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT5,T26,T27
010CoveredT5,T31,T27
100CoveredT2,T6,T30

 LINE       223
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T5,T6
11CoveredT5,T31,T27

 LINE       223
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T17,T18
11CoveredT5,T26,T27

 LINE       233
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---
-1-StatusTests
0CoveredT2,T4,T5
1CoveredT1,T2,T3

 LINE       240
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---
-1--2-StatusTests
01CoveredT128,T196,T42
10CoveredT1,T2,T3
11CoveredT2,T4,T5

 LINE       240
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---
-1--2-StatusTests
01CoveredT7,T22,T68
10CoveredT1,T2,T3
11CoveredT2,T4,T5

 LINE       240
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---
-1--2-StatusTests
01CoveredT22,T128,T196
10CoveredT1,T2,T3
11CoveredT2,T4,T5

 LINE       240
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---
-1--2-StatusTests
01CoveredT7,T128,T196
10CoveredT1,T2,T3
11CoveredT2,T4,T5

 LINE       292
 EXPRESSION (req_o & ack_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT128,T196,T42
11CoveredT1,T2,T3

 LINE       293
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--
-1--2-StatusTests
01CoveredT2,T18,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       303
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T5

 LINE       306
 EXPRESSION (req_i && rdy_o)
             --1--    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T13,T29
11CoveredT1,T2,T3

 LINE       309
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       378
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       383
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

 LINE       394
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       400
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
             --------------------------------1-------------------------------   -----------2-----------   --------3-------   -----------------4-----------------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Not Covered
1101CoveredT1,T2,T3
1110CoveredT4,T13,T29
1111CoveredT1,T2,T3

 LINE       400
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---
-1-StatusTests
0CoveredT2,T4,T5
1CoveredT1,T2,T3

 LINE       400
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT4,T37,T8
111CoveredT1,T2,T3

 LINE       400
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       408
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
             --1--   --------2-------   ----3----   ------4------   ----5---   -----------------6-----------------
-1--2--3--4--5--6-StatusTests
011111CoveredT1,T2,T3
101111Not Covered
110111CoveredT8,T22,T68
111011Not Covered
111101CoveredT2,T4,T5
111110CoveredT4,T7,T91
111111CoveredT1,T2,T3

 LINE       408
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       429
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T6,T47
11CoveredT1,T2,T3

 LINE       433
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------
-1--2-StatusTests
01CoveredT2,T5,T6
10CoveredT1,T2,T3
11CoveredT7,T26,T28

 LINE       433
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T5,T6

 LINE       443
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------
-1--2-StatusTests
01CoveredT31,T8,T22
10CoveredT1,T2,T3
11CoveredT31,T33,T58

 LINE       452
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT29,T31,T33

 LINE       452
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT29,T42,T44
10CoveredT31,T33,T58

 LINE       457
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------
-1--2-StatusTests
01CoveredT29,T8,T22
10CoveredT1,T2,T3
11CoveredT29,T42,T44

 LINE       493
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy & addr_xor_fifo_rdy)
             ------1------   ------2------   --------3--------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT4,T37,T8
111CoveredT1,T2,T3

 LINE       496
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T6,T29
110CoveredT7,T26,T28
111CoveredT1,T2,T3

 LINE       499
 EXPRESSION (rd_done & rd_attrs.descramble & data_erased)
             ---1---   ---------2---------   -----3-----
-1--2--3-StatusTests
011Not Covered
101CoveredT128,T196,T87
110CoveredT1,T2,T3
111CoveredT7,T26,T28

 LINE       503
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT8,T24,T185
111CoveredT2,T6,T29

 LINE       505
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT2,T6,T29
11CoveredT1,T2,T3

 LINE       506
 EXPRESSION (fifo_data_valid & dropmsk_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT7,T26,T28

 LINE       507
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T6,T29

 LINE       515
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : (hint_dropmsk ? mask_valid : fifo_data_valid))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       515
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       515
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : fifo_data_valid)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T26,T28

 LINE       523
 EXPRESSION (hint_forward & (hint_dropmsk ? mask_valid : 1'b1))
             ------1-----   -----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T91,T87
11CoveredT2,T6,T29

 LINE       523
 SUB-EXPRESSION (hint_dropmsk ? mask_valid : 1'b1)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T26,T28

 LINE       525
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       600
 EXPRESSION (req_o & ack_i & descramble_i)
             --1--   --2--   ------3-----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT42,T185,T211
110CoveredT2,T6,T29
111CoveredT1,T2,T3

 LINE       601
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----
-1--2-StatusTests
01CoveredT5,T29,T31
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       617
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T7,T37
110CoveredT7,T26,T28
111CoveredT1,T2,T3

 LINE       627
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T6,T29

 LINE       627
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       631
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T6,T29

 LINE       631
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------
-1-StatusTests
0CoveredT2,T6,T29
1CoveredT1,T2,T3

 LINE       639
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T6,T29

 LINE       639
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------
-1--2-StatusTests
01CoveredT2,T6,T29
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       657
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T6,T29

 LINE       657
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       657
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------
-1--2-StatusTests
01CoveredT2,T6,T29
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       662
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       662
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------
-1--2-StatusTests
00CoveredT2,T4,T5
01CoveredT1,T2,T3
10Not Covered

 LINE       662
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT2,T4,T5
1110CoveredT2,T4,T5
1111CoveredT2,T4,T5

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT2,T4,T5
1110CoveredT2,T4,T5
1111CoveredT2,T4,T5

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT2,T4,T5
1110CoveredT2,T4,T5
1111CoveredT2,T4,T5

 LINE       667
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT2,T4,T5
1110CoveredT2,T4,T5
1111CoveredT2,T4,T5

 LINE       680
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------
-1--2-StatusTests
00CoveredT2,T4,T5
01Not Covered
10Not Covered

 LINE       686
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T5

 LINE       739
 EXPRESSION (data_err_o ? inv_data_integ : data_out_intg)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T29,T31

 LINE       750
 EXPRESSION (((|buf_rsp_match)) ? buf_addr_xor_muxed : fifo_addr_xor_muxed)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T5

 LINE       777
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       777
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       789
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T5
10CoveredT1,T2,T3

 LINE       792
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT197
10CoveredT12,T29,T31

 LINE       792
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT12,T29,T31

 LINE       792
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT1,T2,T3
100CoveredT58,T187,T154

 LINE       792
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----
-1--2-StatusTests
01Not Covered
10CoveredT2,T4,T5
11Not Covered

 LINE       796
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT12,T29,T31

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
Line No.TotalCoveredPercent
Branches 43 43 100.00
TERNARY 187 2 2 100.00
TERNARY 233 2 2 100.00
TERNARY 303 2 2 100.00
TERNARY 452 2 2 100.00
TERNARY 515 3 3 100.00
TERNARY 627 3 3 100.00
TERNARY 631 3 3 100.00
TERNARY 657 3 3 100.00
TERNARY 686 2 2 100.00
TERNARY 739 2 2 100.00
TERNARY 750 2 2 100.00
TERNARY 777 2 2 100.00
TERNARY 168 2 2 100.00
IF 258 3 3 100.00
IF 361 4 4 100.00
IF 603 4 4 100.00
IF 677 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 187 ((|buf_invalid_alloc)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T4,T5


LineNo. Expression -1-: 233 (no_match) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T4,T5


LineNo. Expression -1-: 303 ((|alloc)) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 452 ((data_err | ecc_single_err_o)) ?

Branches:
-1-StatusTests
1 Covered T29,T31,T33
0 Covered T1,T2,T3


LineNo. Expression -1-: 515 (hint_descram) ? -2-: 515 (hint_dropmsk) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T7,T26,T28
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 627 (forward) ? -2-: 627 (hint_descram) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T6,T29
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 631 (forward) ? -2-: 631 ((~hint_forward)) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T6,T29
0 1 Covered T1,T2,T3
0 0 Covered T2,T6,T29


LineNo. Expression -1-: 657 (forward) ? -2-: 657 (((~hint_forward) & fifo_data_ready)) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T6,T29
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 686 ((|buf_rsp_match)) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 739 (data_err_o) ?

Branches:
-1-StatusTests
1 Covered T12,T29,T31
0 Covered T1,T2,T3


LineNo. Expression -1-: 750 ((|buf_rsp_match)) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 777 (rsp_fifo_rdata.intg_ecc_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 168 (((|buf_invalid_alloc) | all_buf_dependency)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T4,T5


LineNo. Expression -1-: 258 if ((!rst_ni)) -2-: 260 if (idle_o)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 361 if ((!rst_ni)) -2-: 365 if (rd_start) -3-: 372 if (rd_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 603 if ((!rst_ni)) -2-: 605 if (calc_req_start) -3-: 607 if (calc_req_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 677 if (buf_rsp_match[i])

Branches:
-1-StatusTests
1 Covered T2,T4,T5
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 11 11 100.00 11 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 11 11 100.00 11 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferMatchEcc_A 385025276 971491 0 0
ExclusiveOps_A 385025276 384222502 0 0
ExclusiveProgHazard_A 385025276 384222502 0 0
ExclusiveState_A 385025276 384222502 0 0
ForwardCheck_A 385025276 2636441 0 0
IdleCheck_A 385025276 53517043 0 0
MaxBufs_A 1036 1036 0 0
OneHotAlloc_A 385025276 384222502 0 0
OneHotMatch_A 385025276 384222502 0 0
OneHotRspMatch_A 385025276 384222502 0 0
OneHotUpdate_A 385025276 384222502 0 0


BufferMatchEcc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385025276 971491 0 0
T2 338721 163 0 0
T3 3135 0 0 0
T4 150432 6730 0 0
T5 114622 864 0 0
T6 0 265 0 0
T7 0 1007 0 0
T12 1062 0 0 0
T13 609 8 0 0
T14 710 0 0 0
T17 3636 0 0 0
T18 2686 0 0 0
T19 3084 0 0 0
T29 0 17 0 0
T31 0 26 0 0
T32 0 115 0 0
T37 0 2724 0 0

ExclusiveOps_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385025276 384222502 0 0
T1 1558 1470 0 0
T2 338721 338630 0 0
T3 3135 3063 0 0
T4 150432 150297 0 0
T5 114622 109282 0 0
T12 1062 838 0 0
T13 609 548 0 0
T17 3636 2902 0 0
T18 2686 2617 0 0
T19 3084 3010 0 0

ExclusiveProgHazard_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385025276 384222502 0 0
T1 1558 1470 0 0
T2 338721 338630 0 0
T3 3135 3063 0 0
T4 150432 150297 0 0
T5 114622 109282 0 0
T12 1062 838 0 0
T13 609 548 0 0
T17 3636 2902 0 0
T18 2686 2617 0 0
T19 3084 3010 0 0

ExclusiveState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385025276 384222502 0 0
T1 1558 1470 0 0
T2 338721 338630 0 0
T3 3135 3063 0 0
T4 150432 150297 0 0
T5 114622 109282 0 0
T12 1062 838 0 0
T13 609 548 0 0
T17 3636 2902 0 0
T18 2686 2617 0 0
T19 3084 3010 0 0

ForwardCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385025276 2636441 0 0
T2 338721 188 0 0
T3 3135 0 0 0
T4 150432 0 0 0
T5 114622 0 0 0
T6 0 309 0 0
T7 0 9794 0 0
T8 0 9043 0 0
T12 1062 0 0 0
T13 609 0 0 0
T14 710 0 0 0
T17 3636 0 0 0
T18 2686 0 0 0
T19 3084 0 0 0
T22 0 9104 0 0
T26 0 41844 0 0
T27 0 44 0 0
T29 0 3 0 0
T30 0 66 0 0
T47 0 4 0 0

IdleCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385025276 53517043 0 0
T1 1558 128 0 0
T2 338721 667 0 0
T3 3135 128 0 0
T4 150432 64924 0 0
T5 114622 13024 0 0
T12 1062 268 0 0
T13 609 176 0 0
T17 3636 512 0 0
T18 2686 128 0 0
T19 3084 128 0 0

MaxBufs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1036 1036 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

OneHotAlloc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385025276 384222502 0 0
T1 1558 1470 0 0
T2 338721 338630 0 0
T3 3135 3063 0 0
T4 150432 150297 0 0
T5 114622 109282 0 0
T12 1062 838 0 0
T13 609 548 0 0
T17 3636 2902 0 0
T18 2686 2617 0 0
T19 3084 3010 0 0

OneHotMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385025276 384222502 0 0
T1 1558 1470 0 0
T2 338721 338630 0 0
T3 3135 3063 0 0
T4 150432 150297 0 0
T5 114622 109282 0 0
T12 1062 838 0 0
T13 609 548 0 0
T17 3636 2902 0 0
T18 2686 2617 0 0
T19 3084 3010 0 0

OneHotRspMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385025276 384222502 0 0
T1 1558 1470 0 0
T2 338721 338630 0 0
T3 3135 3063 0 0
T4 150432 150297 0 0
T5 114622 109282 0 0
T12 1062 838 0 0
T13 609 548 0 0
T17 3636 2902 0 0
T18 2686 2617 0 0
T19 3084 3010 0 0

OneHotUpdate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385025276 384222502 0 0
T1 1558 1470 0 0
T2 338721 338630 0 0
T3 3135 3063 0 0
T4 150432 150297 0 0
T5 114622 109282 0 0
T12 1062 838 0 0
T13 609 548 0 0
T17 3636 2902 0 0
T18 2686 2617 0 0
T19 3084 3010 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%