Module Definition
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Module Instance : tb.dut.u_reg_core.u_chk.u_tlul_data_integ_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_chk 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_data_intg_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.33 100.00 90.62 92.11 98.94 100.00 u_flash_hw_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_chk 100.00 100.00



Module Instance : tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_cmd_intg_check.u_cmd_intg_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_chk 100.00 100.00



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.u_tlul_data_integ_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_chk 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_data_intg_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.38 100.00 96.92 100.00 100.00 100.00 gen_prog_data.u_prog


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_chk 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_data_intg_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.50 100.00 95.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.38 100.00 96.92 100.00 100.00 100.00 gen_prog_data.u_prog


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_chk 95.00 95.00

Line Coverage for Module : tlul_data_integ_dec
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN2511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_chk.u_tlul_data_integ_dec
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN2511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_data_intg_chk
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN2511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN2511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.u_tlul_data_integ_dec
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN2511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_data_intg_chk
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN2511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_data_intg_chk
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN2511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1

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