Unified Coverage Report :: Module :: flash_phy_prog

Module : flash_phy_prog

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog	99.38	100.00	96.92		100.00	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog	99.38	100.00	96.92		100.00	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.49	100.00	96.92	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.87	100.00	91.51		100.00	97.83	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	100.00	100.00		100.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.65	100.00	96.92	95.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.74	100.00	85.85		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	97.50	100.00		95.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Module : flash_phy_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T5,T6

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T5,T6

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T142,T199
1	0	Covered	T11,T142,T199

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T16
1	1	Covered	T11,T142,T199

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T142,T199
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T5,T6

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T11,T5,T6
1	Covered	T7,T200,T36

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T11,T5,T6
1	0	Covered	T11,T5,T6
1	1	Covered	T11,T5,T6

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T5,T6

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T5,T6
1	1	Covered	T7,T200,T36

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T10
1	Covered	T7,T200,T36

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T11,T5,T6
1	0	Covered	T11,T5,T6
1	1	Covered	T11,T5,T6

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T11,T5,T6
1	Covered	T11,T5,T6

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T16
1	0	Covered	T11,T5,T6
1	1	Covered	T7,T200,T36

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T8,T10
1	Covered	T7,T200,T36

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T11,T6,T7
1	Covered	T5,T6,T16

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T6,T16,T39
1	Covered	T5,T6,T16

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T6,T16,T39
1	Covered	T11,T6,T16

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T16,T39
1	1	Covered	T5,T6,T16

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T16
1	1	Covered	T5,T6,T16

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T16
1	1	Covered	T5,T6,T16

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T6,T16
1	1	0	Covered	T11,T5,T6
1	1	1	Covered	T5,T6,T16

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T16

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : flash_phy_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T5,T6,T16
StCalcMask	237	Covered	T5,T6,T16
StCalcPlainEcc	215	Covered	T11,T5,T6
StDisabled	193	Covered	T2,T11,T12
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T11,T5,T6
StPostPack	218	Covered	T7,T200,T36
StPrePack	195	Covered	T7,T200,T36
StReqFlash	237	Covered	T11,T5,T6
StScrambleData	244	Covered	T5,T6,T16
StWaitFlash	270	Covered	T5,T6,T16

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T5,T6,T16
StCalcMask->StScrambleData	244	Covered	T5,T6,T16
StCalcPlainEcc->StCalcMask	237	Covered	T5,T6,T16
StCalcPlainEcc->StReqFlash	237	Covered	T11,T6,T7
StIdle->StDisabled	193	Covered	T2,T11,T12
StIdle->StPackData	197	Covered	T11,T5,T6
StIdle->StPrePack	195	Covered	T7,T200,T36
StPackData->StCalcPlainEcc	215	Covered	T11,T5,T6
StPackData->StPostPack	218	Covered	T7,T200,T36
StPostPack->StCalcPlainEcc	231	Covered	T7,T200,T36
StPrePack->StPackData	205	Covered	T7,T200,T36
StReqFlash->StIdle	273	Covered	T11,T6,T16
StReqFlash->StWaitFlash	270	Covered	T5,T6,T16
StScrambleData->StCalcEcc	252	Covered	T5,T6,T16
StWaitFlash->StIdle	280	Covered	T5,T6,T16

---

Branch Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T16
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T11,T5,T6
0	0	1	Covered	T11,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T12
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T200,T36
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T5,T6
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T200,T36
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T10
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T11,T5,T6
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T7,T200,T36
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T11,T5,T6
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T11,T5,T6
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T7,T200,T36
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T8,T10
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T6,T16
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T11,T6,T7
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T5,T6,T16
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T5,T6,T16
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T6,T16
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T5,T6,T16
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T16
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T5,T6,T16
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T6,T16,T39
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T11,T6,T16
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T6,T16,T39
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T5,T6,T16
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T5,T6,T16
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T13,T10

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T5,T6,T16
0	0	1	-	-	Covered	T5,T6,T16
0	0	0	1	-	Covered	T5,T6,T16
0	0	0	0	1	Covered	T11,T5,T6
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T11,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	750920344	2436842	0	0
PostPackRule_A	750920344	1833	0	0
PrePackRule_A	750920344	1325	0	0
WidthCheck_A	2084	2084	0	0
u_state_regs_A	750920344	749264580	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750920344	2436842	0	0
T5	1873	1	0	0
T6	574032	1264	0	0
T7	4480	2	0	0
T12	0	66080	0	0
T14	27452	0	0	0
T15	2002	0	0	0
T16	54870	15	0	0
T17	0	100	0	0
T21	11320	0	0	0
T22	170630	1408	0	0
T23	0	1	0	0
T27	125128	64	0	0
T34	0	24	0	0
T39	260118	493	0	0
T51	0	1562	0	0
T52	2792	0	0	0
T55	0	2	0	0
T76	0	61	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750920344	1833	0	0
T7	2240	2	0	0
T17	164606	0	0	0
T18	1534	0	0	0
T21	5660	0	0	0
T22	170630	0	0	0
T24	2035	0	0	0
T27	62564	0	0	0
T34	7693	0	0	0
T36	140711	7	0	0
T40	103413	0	0	0
T43	84189	0	0	0
T44	420362	0	0	0
T51	374326	0	0	0
T55	1323	0	0	0
T66	70249	2	0	0
T67	634054	49	0	0
T80	0	61	0	0
T86	0	36	0	0
T89	3927	0	0	0
T108	1074	0	0	0
T126	0	6	0	0
T136	0	5	0	0
T139	0	14	0	0
T200	31694	34	0	0
T218	0	39	0	0
T219	1599	0	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750920344	1325	0	0
T7	2240	1	0	0
T17	164606	0	0	0
T18	1534	0	0	0
T21	5660	0	0	0
T22	170630	0	0	0
T24	2035	0	0	0
T27	62564	0	0	0
T34	7693	0	0	0
T36	140711	6	0	0
T40	103413	0	0	0
T43	84189	0	0	0
T44	420362	0	0	0
T51	374326	0	0	0
T55	1323	0	0	0
T66	70249	2	0	0
T67	634054	24	0	0
T80	0	53	0	0
T86	0	29	0	0
T89	3927	0	0	0
T108	1074	0	0	0
T126	0	5	0	0
T136	0	9	0	0
T139	0	7	0	0
T200	31694	19	0	0
T218	0	31	0	0
T219	1599	0	0	0
T220	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2084	2084	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T11	2	2	0	0
T14	2	2	0	0
T15	2	2	0	0
T16	2	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750920344	749264580	0	0
T1	2854	2676	0	0
T2	2466	2350	0	0
T3	124182	123984	0	0
T4	117256	117150	0	0
T5	3746	3500	0	0
T6	574032	573850	0	0
T11	482404	482134	0	0
T14	27452	27324	0	0
T15	2002	1842	0	0
T16	54870	54530	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T5,T6

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T5,T6

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T142,T199
1	0	Covered	T11,T142,T199

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T16
1	1	Covered	T11,T142,T199

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T142,T199
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T5,T6

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T11,T5,T6
1	Covered	T200,T36,T66

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T11,T5,T6
1	0	Covered	T11,T5,T6
1	1	Covered	T11,T5,T6

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T5,T6

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T5,T6
1	1	Covered	T200,T36,T66

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T10
1	Covered	T200,T36,T66

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T11,T5,T6
1	0	Covered	T11,T5,T6
1	1	Covered	T11,T5,T6

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T11,T5,T6
1	Covered	T11,T5,T6

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T16
1	0	Covered	T11,T5,T6
1	1	Covered	T200,T36,T66

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T8,T10
1	Covered	T200,T36,T66

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T11,T6,T27
1	Covered	T5,T6,T16

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T6,T16,T39
1	Covered	T5,T6,T16

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T6,T16,T39
1	Covered	T11,T6,T16

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T16,T39
1	1	Covered	T5,T6,T16

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T16
1	1	Covered	T5,T6,T16

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T16
1	1	Covered	T5,T6,T16

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T6,T16
1	1	0	Covered	T11,T5,T6
1	1	1	Covered	T5,T6,T16

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T16

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T5,T6,T16
StCalcMask	237	Covered	T5,T6,T16
StCalcPlainEcc	215	Covered	T11,T5,T6
StDisabled	193	Covered	T2,T11,T12
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T11,T5,T6
StPostPack	218	Covered	T200,T36,T66
StPrePack	195	Covered	T200,T36,T66
StReqFlash	237	Covered	T11,T5,T6
StScrambleData	244	Covered	T5,T6,T16
StWaitFlash	270	Covered	T5,T6,T16

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T5,T6,T16
StCalcMask->StScrambleData	244	Covered	T5,T6,T16
StCalcPlainEcc->StCalcMask	237	Covered	T5,T6,T16
StCalcPlainEcc->StReqFlash	237	Covered	T11,T6,T27
StIdle->StDisabled	193	Covered	T2,T11,T12
StIdle->StPackData	197	Covered	T11,T5,T6
StIdle->StPrePack	195	Covered	T200,T36,T66
StPackData->StCalcPlainEcc	215	Covered	T11,T5,T6
StPackData->StPostPack	218	Covered	T200,T36,T66
StPostPack->StCalcPlainEcc	231	Covered	T200,T36,T66
StPrePack->StPackData	205	Covered	T200,T36,T66
StReqFlash->StIdle	273	Covered	T11,T6,T16
StReqFlash->StWaitFlash	270	Covered	T5,T6,T16
StScrambleData->StCalcEcc	252	Covered	T5,T6,T16
StWaitFlash->StIdle	280	Covered	T5,T6,T16

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T16
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T11,T5,T6
0	0	1	Covered	T11,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T12
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T200,T36,T66
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T5,T6
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T200,T36,T66
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T10
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T11,T5,T6
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T200,T36,T66
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T11,T5,T6
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T11,T5,T6
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T200,T36,T66
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T8,T10
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T6,T16
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T11,T6,T27
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T5,T6,T16
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T5,T6,T16
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T6,T16
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T5,T6,T16
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T16
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T5,T6,T16
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T6,T16,T39
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T11,T6,T16
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T6,T16,T39
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T5,T6,T16
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T5,T6,T16
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T13,T10

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T5,T6,T16
0	0	1	-	-	Covered	T5,T6,T16
0	0	0	1	-	Covered	T5,T6,T16
0	0	0	0	1	Covered	T11,T5,T6
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T11,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	375460172	1238560	0	0
PostPackRule_A	375460172	953	0	0
PrePackRule_A	375460172	697	0	0
WidthCheck_A	1042	1042	0	0
u_state_regs_A	375460172	374632290	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	1238560	0	0
T5	1873	1	0	0
T6	287016	722	0	0
T7	2240	0	0	0
T12	0	33280	0	0
T14	13726	0	0	0
T15	1001	0	0	0
T16	27435	15	0	0
T17	0	59	0	0
T21	5660	0	0	0
T22	0	771	0	0
T27	62564	64	0	0
T34	0	24	0	0
T39	130059	245	0	0
T51	0	880	0	0
T52	1396	0	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	953	0	0
T24	2035	0	0	0
T36	140711	2	0	0
T40	103413	0	0	0
T43	84189	0	0	0
T44	420362	0	0	0
T66	70249	2	0	0
T67	634054	27	0	0
T80	0	28	0	0
T86	0	20	0	0
T89	3927	0	0	0
T126	0	2	0	0
T136	0	1	0	0
T139	0	5	0	0
T200	31694	15	0	0
T218	0	20	0	0
T219	1599	0	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	697	0	0
T24	2035	0	0	0
T36	140711	2	0	0
T40	103413	0	0	0
T43	84189	0	0	0
T44	420362	0	0	0
T66	70249	2	0	0
T67	634054	15	0	0
T80	0	26	0	0
T86	0	15	0	0
T89	3927	0	0	0
T126	0	3	0	0
T136	0	2	0	0
T200	31694	8	0	0
T218	0	19	0	0
T219	1599	0	0	0
T220	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	374632290	0	0
T1	1427	1338	0	0
T2	1233	1175	0	0
T3	62091	61992	0	0
T4	58628	58575	0	0
T5	1873	1750	0	0
T6	287016	286925	0	0
T11	241202	241067	0	0
T14	13726	13662	0	0
T15	1001	921	0	0
T16	27435	27265	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T39,T7

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T39,T7

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T221,T222
1	0	Covered	T221,T222

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T39,T7
1	1	Covered	T221,T222

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T221,T222
1	0	Covered	T3,T4,T5

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T39,T7

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T6,T39,T7
1	Covered	T7,T200,T36

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T6,T39,T7
1	0	Covered	T6,T39,T7
1	1	Covered	T6,T39,T7

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T39,T7

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T39,T7
1	1	Covered	T7,T200,T36

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T10
1	Covered	T7,T200,T36

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T6,T39,T7
1	0	Covered	T6,T39,T7
1	1	Covered	T6,T39,T7

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T6,T39,T7
1	Covered	T6,T39,T7

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T6,T39,T22
1	0	Covered	T6,T39,T7
1	1	Covered	T7,T200,T36

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T8,T10
1	Covered	T7,T200,T36

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T6,T7,T22
1	Covered	T39,T51,T55

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T6,T39,T7
1	Covered	T6,T39,T7

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T6,T39,T7
1	Covered	T6,T39,T7

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T39,T7
1	1	Covered	T6,T39,T7

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T39,T51,T55
1	1	Covered	T39,T51,T55

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T39
1	0	Covered	T39,T51,T55
1	1	Covered	T39,T51,T55

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T6,T39,T7
1	1	0	Covered	T6,T39,T7
1	1	1	Covered	T6,T39,T7

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T39,T7

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T39,T51,T55
StCalcMask	237	Covered	T39,T51,T55
StCalcPlainEcc	215	Covered	T6,T39,T7
StDisabled	193	Covered	T2,T11,T12
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T6,T39,T7
StPostPack	218	Covered	T7,T200,T36
StPrePack	195	Covered	T7,T200,T36
StReqFlash	237	Covered	T6,T39,T7
StScrambleData	244	Covered	T39,T51,T55
StWaitFlash	270	Covered	T6,T39,T7

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T39,T51,T55
StCalcMask->StScrambleData	244	Covered	T39,T51,T55
StCalcPlainEcc->StCalcMask	237	Covered	T39,T51,T55
StCalcPlainEcc->StReqFlash	237	Covered	T6,T7,T22
StIdle->StDisabled	193	Covered	T2,T11,T12
StIdle->StPackData	197	Covered	T6,T39,T7
StIdle->StPrePack	195	Covered	T7,T200,T36
StPackData->StCalcPlainEcc	215	Covered	T6,T39,T7
StPackData->StPostPack	218	Covered	T7,T200,T36
StPostPack->StCalcPlainEcc	231	Covered	T7,T200,T36
StPrePack->StPackData	205	Covered	T7,T200,T36
StReqFlash->StIdle	273	Covered	T6,T39,T7
StReqFlash->StWaitFlash	270	Covered	T6,T39,T7
StScrambleData->StCalcEcc	252	Covered	T39,T51,T55
StWaitFlash->StIdle	280	Covered	T6,T39,T7

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T39,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T39,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T39,T7
0	1	Covered	T3,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T39,T7
0	0	1	Covered	T6,T39,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T12
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T200,T36
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T39,T7
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T200,T36
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T10
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T39,T7
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T7,T200,T36
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T6,T39,T7
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T6,T39,T7
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T7,T200,T36
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T8,T10
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T39,T51,T55
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T6,T7,T22
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T39,T51,T55
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T39,T51,T55
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T39,T51,T55
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T39,T51,T55
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T39,T51,T55
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T6,T39,T7
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T6,T39,T7
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T6,T39,T7
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T6,T39,T7
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T39,T7
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T6,T39,T7
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T13,T10

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T6,T39,T7
0	0	1	-	-	Covered	T39,T51,T55
0	0	0	1	-	Covered	T39,T51,T55
0	0	0	0	1	Covered	T6,T39,T7
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T6,T39,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	375460172	1198282	0	0
PostPackRule_A	375460172	880	0	0
PrePackRule_A	375460172	628	0	0
WidthCheck_A	1042	1042	0	0
u_state_regs_A	375460172	374632290	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	1198282	0	0
T6	287016	542	0	0
T7	2240	2	0	0
T12	0	32800	0	0
T14	13726	0	0	0
T15	1001	0	0	0
T16	27435	0	0	0
T17	0	41	0	0
T21	5660	0	0	0
T22	170630	637	0	0
T23	0	1	0	0
T27	62564	0	0	0
T39	130059	248	0	0
T51	0	682	0	0
T52	1396	0	0	0
T55	0	2	0	0
T76	0	61	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	880	0	0
T7	2240	2	0	0
T17	164606	0	0	0
T18	1534	0	0	0
T21	5660	0	0	0
T22	170630	0	0	0
T27	62564	0	0	0
T34	7693	0	0	0
T36	0	5	0	0
T51	374326	0	0	0
T55	1323	0	0	0
T67	0	22	0	0
T80	0	33	0	0
T86	0	16	0	0
T108	1074	0	0	0
T126	0	4	0	0
T136	0	4	0	0
T139	0	9	0	0
T200	0	19	0	0
T218	0	19	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	628	0	0
T7	2240	1	0	0
T17	164606	0	0	0
T18	1534	0	0	0
T21	5660	0	0	0
T22	170630	0	0	0
T27	62564	0	0	0
T34	7693	0	0	0
T36	0	4	0	0
T51	374326	0	0	0
T55	1323	0	0	0
T67	0	9	0	0
T80	0	27	0	0
T86	0	14	0	0
T108	1074	0	0	0
T126	0	2	0	0
T136	0	7	0	0
T139	0	7	0	0
T200	0	11	0	0
T218	0	12	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375460172	374632290	0	0
T1	1427	1338	0	0
T2	1233	1175	0	0
T3	62091	61992	0	0
T4	58628	58575	0	0
T5	1873	1750	0	0
T6	287016	286925	0	0
T11	241202	241067	0	0
T14	13726	13662	0	0
T15	1001	921	0	0
T16	27435	27265	0	0