Line Coverage for Module :
flash_phy_rd_buf_dep
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 48 | 7 | 7 | 100.00 |
CONT_ASSIGN | 61 | 1 | 1 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
ALWAYS | 76 | 6 | 6 | 100.00 |
ALWAYS | 90 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
ALWAYS | 116 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
|
|
|
MISSING_ELSE |
54 |
1 |
1 |
55 |
1 |
1 |
|
|
|
MISSING_ELSE |
61 |
1 |
1 |
62 |
1 |
1 |
65 |
1 |
1 |
66 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
|
|
|
MISSING_ELSE |
82 |
1 |
1 |
83 |
1 |
1 |
|
|
|
MISSING_ELSE |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
116 |
|
unreachable |
117 |
|
unreachable |
118 |
|
unreachable |
Cond Coverage for Module :
flash_phy_rd_buf_dep
| Total | Covered | Percent |
Conditions | 22 | 19 | 86.36 |
Logical | 22 | 19 | 86.36 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
--1- ----2---- -----------------------3----------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 66
EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
--1- ----2---- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 71
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
----1--- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T32,T54 |
1 | 1 | Covered | T1,T2,T3 |
LINE 72
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T32,T54 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
flash_phy_rd_buf_dep
| Line No. | Total | Covered | Percent |
Branches |
|
13 |
13 |
100.00 |
TERNARY |
71 |
2 |
2 |
100.00 |
TERNARY |
72 |
2 |
2 |
100.00 |
IF |
51 |
2 |
2 |
100.00 |
IF |
54 |
2 |
2 |
100.00 |
IF |
76 |
5 |
5 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 72 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 51 if (wr_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 54 if (rd_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 76 if ((!rst_ni))
-2-: 79 if (fin_cnt_incr)
-3-: 82 if (fin_cnt_decr)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
flash_phy_rd_buf_dep
Assertion Details
BufferDecrUnderRun_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
751557086 |
6629191 |
0 |
0 |
T1 |
2491 |
20 |
0 |
0 |
T2 |
376740 |
252 |
0 |
0 |
T3 |
2172 |
22 |
0 |
0 |
T4 |
839422 |
5424 |
0 |
0 |
T5 |
273450 |
3785 |
0 |
0 |
T6 |
0 |
44878 |
0 |
0 |
T7 |
0 |
21158 |
0 |
0 |
T8 |
0 |
9721 |
0 |
0 |
T12 |
6718 |
0 |
0 |
0 |
T13 |
8194 |
0 |
0 |
0 |
T17 |
2604 |
0 |
0 |
0 |
T18 |
6970 |
0 |
0 |
0 |
T19 |
9066 |
0 |
0 |
0 |
T21 |
0 |
60 |
0 |
0 |
T32 |
0 |
166 |
0 |
0 |
T43 |
0 |
5880 |
0 |
0 |
T52 |
0 |
872 |
0 |
0 |
T53 |
0 |
8088 |
0 |
0 |
T54 |
0 |
129 |
0 |
0 |
T55 |
1247 |
0 |
0 |
0 |
BufferDepRsp_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
751557086 |
749899942 |
0 |
0 |
T1 |
4982 |
4806 |
0 |
0 |
T2 |
376740 |
376736 |
0 |
0 |
T3 |
2172 |
2070 |
0 |
0 |
T4 |
839422 |
804928 |
0 |
0 |
T5 |
273450 |
273432 |
0 |
0 |
T12 |
6718 |
5324 |
0 |
0 |
T13 |
8194 |
6788 |
0 |
0 |
T17 |
2604 |
2438 |
0 |
0 |
T18 |
6970 |
6796 |
0 |
0 |
T19 |
9066 |
8894 |
0 |
0 |
BufferIncrOverFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
751557086 |
6629202 |
0 |
0 |
T1 |
2491 |
20 |
0 |
0 |
T2 |
376740 |
252 |
0 |
0 |
T3 |
2172 |
22 |
0 |
0 |
T4 |
839422 |
5424 |
0 |
0 |
T5 |
273450 |
3785 |
0 |
0 |
T6 |
0 |
44878 |
0 |
0 |
T7 |
0 |
21158 |
0 |
0 |
T8 |
0 |
9721 |
0 |
0 |
T12 |
6718 |
0 |
0 |
0 |
T13 |
8194 |
0 |
0 |
0 |
T17 |
2604 |
0 |
0 |
0 |
T18 |
6970 |
0 |
0 |
0 |
T19 |
9066 |
0 |
0 |
0 |
T21 |
0 |
60 |
0 |
0 |
T32 |
0 |
166 |
0 |
0 |
T43 |
0 |
5880 |
0 |
0 |
T52 |
0 |
872 |
0 |
0 |
T53 |
0 |
8088 |
0 |
0 |
T54 |
0 |
129 |
0 |
0 |
T55 |
1247 |
0 |
0 |
0 |
DepBufferRspOrder_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
751557089 |
16133113 |
0 |
0 |
T1 |
2491 |
52 |
0 |
0 |
T2 |
376740 |
263964 |
0 |
0 |
T3 |
2172 |
54 |
0 |
0 |
T4 |
839422 |
12752 |
0 |
0 |
T5 |
273450 |
3817 |
0 |
0 |
T6 |
0 |
24616 |
0 |
0 |
T7 |
0 |
8495 |
0 |
0 |
T8 |
0 |
9721 |
0 |
0 |
T12 |
6718 |
104 |
0 |
0 |
T13 |
8194 |
200 |
0 |
0 |
T17 |
2604 |
32 |
0 |
0 |
T18 |
6970 |
32 |
0 |
0 |
T19 |
9066 |
32 |
0 |
0 |
T21 |
0 |
6 |
0 |
0 |
T32 |
0 |
166 |
0 |
0 |
T52 |
0 |
401 |
0 |
0 |
T53 |
0 |
8088 |
0 |
0 |
T54 |
0 |
129 |
0 |
0 |
T55 |
1247 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 48 | 7 | 7 | 100.00 |
CONT_ASSIGN | 61 | 1 | 1 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
ALWAYS | 76 | 6 | 6 | 100.00 |
ALWAYS | 90 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
ALWAYS | 116 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
|
|
|
MISSING_ELSE |
54 |
1 |
1 |
55 |
1 |
1 |
|
|
|
MISSING_ELSE |
61 |
1 |
1 |
62 |
1 |
1 |
65 |
1 |
1 |
66 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
|
|
|
MISSING_ELSE |
82 |
1 |
1 |
83 |
1 |
1 |
|
|
|
MISSING_ELSE |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
116 |
|
unreachable |
117 |
|
unreachable |
118 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
| Total | Covered | Percent |
Conditions | 22 | 19 | 86.36 |
Logical | 22 | 19 | 86.36 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
--1- ----2---- -----------------------3----------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 66
EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
--1- ----2---- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 71
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
----1--- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T32,T54 |
1 | 1 | Covered | T1,T2,T3 |
LINE 72
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T32,T54 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
| Line No. | Total | Covered | Percent |
Branches |
|
13 |
13 |
100.00 |
TERNARY |
71 |
2 |
2 |
100.00 |
TERNARY |
72 |
2 |
2 |
100.00 |
IF |
51 |
2 |
2 |
100.00 |
IF |
54 |
2 |
2 |
100.00 |
IF |
76 |
5 |
5 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 72 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 51 if (wr_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 54 if (rd_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 76 if ((!rst_ni))
-2-: 79 if (fin_cnt_incr)
-3-: 82 if (fin_cnt_decr)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
0 |
- |
1 |
Covered |
T1,T2,T3 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Assertion Details
BufferDecrUnderRun_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
3628546 |
0 |
0 |
T1 |
2491 |
20 |
0 |
0 |
T2 |
188370 |
166 |
0 |
0 |
T3 |
1086 |
22 |
0 |
0 |
T4 |
419711 |
5424 |
0 |
0 |
T5 |
136725 |
2661 |
0 |
0 |
T6 |
0 |
20262 |
0 |
0 |
T7 |
0 |
12663 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T21 |
0 |
54 |
0 |
0 |
T43 |
0 |
5880 |
0 |
0 |
T52 |
0 |
471 |
0 |
0 |
BufferDepRsp_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
374949971 |
0 |
0 |
T1 |
2491 |
2403 |
0 |
0 |
T2 |
188370 |
188368 |
0 |
0 |
T3 |
1086 |
1035 |
0 |
0 |
T4 |
419711 |
402464 |
0 |
0 |
T5 |
136725 |
136716 |
0 |
0 |
T12 |
3359 |
2662 |
0 |
0 |
T13 |
4097 |
3394 |
0 |
0 |
T17 |
1302 |
1219 |
0 |
0 |
T18 |
3485 |
3398 |
0 |
0 |
T19 |
4533 |
4447 |
0 |
0 |
BufferIncrOverFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
3628554 |
0 |
0 |
T1 |
2491 |
20 |
0 |
0 |
T2 |
188370 |
166 |
0 |
0 |
T3 |
1086 |
22 |
0 |
0 |
T4 |
419711 |
5424 |
0 |
0 |
T5 |
136725 |
2661 |
0 |
0 |
T6 |
0 |
20262 |
0 |
0 |
T7 |
0 |
12663 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T21 |
0 |
54 |
0 |
0 |
T43 |
0 |
5880 |
0 |
0 |
T52 |
0 |
471 |
0 |
0 |
DepBufferRspOrder_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778544 |
8615069 |
0 |
0 |
T1 |
2491 |
52 |
0 |
0 |
T2 |
188370 |
132806 |
0 |
0 |
T3 |
1086 |
54 |
0 |
0 |
T4 |
419711 |
12752 |
0 |
0 |
T5 |
136725 |
2693 |
0 |
0 |
T12 |
3359 |
104 |
0 |
0 |
T13 |
4097 |
200 |
0 |
0 |
T17 |
1302 |
32 |
0 |
0 |
T18 |
3485 |
32 |
0 |
0 |
T19 |
4533 |
32 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 48 | 7 | 7 | 100.00 |
CONT_ASSIGN | 61 | 1 | 1 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 66 | 1 | 1 | 100.00 |
CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
ALWAYS | 76 | 6 | 6 | 100.00 |
ALWAYS | 90 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
ALWAYS | 116 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
|
|
|
MISSING_ELSE |
54 |
1 |
1 |
55 |
1 |
1 |
|
|
|
MISSING_ELSE |
61 |
1 |
1 |
62 |
1 |
1 |
65 |
1 |
1 |
66 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
|
|
|
MISSING_ELSE |
82 |
1 |
1 |
83 |
1 |
1 |
|
|
|
MISSING_ELSE |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
116 |
|
unreachable |
117 |
|
unreachable |
118 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
| Total | Covered | Percent |
Conditions | 22 | 19 | 86.36 |
Logical | 22 | 19 | 86.36 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
--1- ----2---- -----------------------3----------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T29,T73 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T5,T6 |
LINE 66
EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
--1- ----2---- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T5,T6 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T5,T6 |
LINE 71
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T2,T5,T6 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 71
SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
----1--- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T32,T54,T69 |
1 | 1 | Covered | T2,T5,T6 |
LINE 72
EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T2,T5,T6 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 72
SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T32,T54,T69 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T5,T6 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
| Line No. | Total | Covered | Percent |
Branches |
|
13 |
13 |
100.00 |
TERNARY |
71 |
2 |
2 |
100.00 |
TERNARY |
72 |
2 |
2 |
100.00 |
IF |
51 |
2 |
2 |
100.00 |
IF |
54 |
2 |
2 |
100.00 |
IF |
76 |
5 |
5 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T5,T6 |
LineNo. Expression
-1-: 72 ((incr_buf_sel == decr_buf_sel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T5,T6 |
LineNo. Expression
-1-: 51 if (wr_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T5,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 54 if (rd_buf_i[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T5,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 76 if ((!rst_ni))
-2-: 79 if (fin_cnt_incr)
-3-: 82 if (fin_cnt_decr)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T2,T5,T6 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
0 |
- |
1 |
Covered |
T2,T5,T6 |
0 |
- |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Assertion Details
BufferDecrUnderRun_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
3000645 |
0 |
0 |
T2 |
188370 |
86 |
0 |
0 |
T3 |
1086 |
0 |
0 |
0 |
T4 |
419711 |
0 |
0 |
0 |
T5 |
136725 |
1124 |
0 |
0 |
T6 |
0 |
24616 |
0 |
0 |
T7 |
0 |
8495 |
0 |
0 |
T8 |
0 |
9721 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T21 |
0 |
6 |
0 |
0 |
T32 |
0 |
166 |
0 |
0 |
T52 |
0 |
401 |
0 |
0 |
T53 |
0 |
8088 |
0 |
0 |
T54 |
0 |
129 |
0 |
0 |
T55 |
1247 |
0 |
0 |
0 |
BufferDepRsp_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
374949971 |
0 |
0 |
T1 |
2491 |
2403 |
0 |
0 |
T2 |
188370 |
188368 |
0 |
0 |
T3 |
1086 |
1035 |
0 |
0 |
T4 |
419711 |
402464 |
0 |
0 |
T5 |
136725 |
136716 |
0 |
0 |
T12 |
3359 |
2662 |
0 |
0 |
T13 |
4097 |
3394 |
0 |
0 |
T17 |
1302 |
1219 |
0 |
0 |
T18 |
3485 |
3398 |
0 |
0 |
T19 |
4533 |
4447 |
0 |
0 |
BufferIncrOverFlow_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
3000648 |
0 |
0 |
T2 |
188370 |
86 |
0 |
0 |
T3 |
1086 |
0 |
0 |
0 |
T4 |
419711 |
0 |
0 |
0 |
T5 |
136725 |
1124 |
0 |
0 |
T6 |
0 |
24616 |
0 |
0 |
T7 |
0 |
8495 |
0 |
0 |
T8 |
0 |
9721 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T21 |
0 |
6 |
0 |
0 |
T32 |
0 |
166 |
0 |
0 |
T52 |
0 |
401 |
0 |
0 |
T53 |
0 |
8088 |
0 |
0 |
T54 |
0 |
129 |
0 |
0 |
T55 |
1247 |
0 |
0 |
0 |
DepBufferRspOrder_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778545 |
7518044 |
0 |
0 |
T2 |
188370 |
131158 |
0 |
0 |
T3 |
1086 |
0 |
0 |
0 |
T4 |
419711 |
0 |
0 |
0 |
T5 |
136725 |
1124 |
0 |
0 |
T6 |
0 |
24616 |
0 |
0 |
T7 |
0 |
8495 |
0 |
0 |
T8 |
0 |
9721 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T21 |
0 |
6 |
0 |
0 |
T32 |
0 |
166 |
0 |
0 |
T52 |
0 |
401 |
0 |
0 |
T53 |
0 |
8088 |
0 |
0 |
T54 |
0 |
129 |
0 |
0 |
T55 |
1247 |
0 |
0 |
0 |