Line Coverage for Module :
flash_phy_rd
| Line No. | Total | Covered | Percent |
TOTAL | | 133 | 133 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 152 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 186 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 229 | 1 | 1 | 100.00 |
CONT_ASSIGN | 232 | 1 | 1 | 100.00 |
ALWAYS | 257 | 4 | 4 | 100.00 |
CONT_ASSIGN | 291 | 1 | 1 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 302 | 1 | 1 | 100.00 |
CONT_ASSIGN | 305 | 1 | 1 | 100.00 |
CONT_ASSIGN | 308 | 1 | 1 | 100.00 |
CONT_ASSIGN | 326 | 1 | 1 | 100.00 |
CONT_ASSIGN | 331 | 1 | 1 | 100.00 |
ALWAYS | 360 | 12 | 12 | 100.00 |
CONT_ASSIGN | 377 | 1 | 1 | 100.00 |
CONT_ASSIGN | 382 | 1 | 1 | 100.00 |
CONT_ASSIGN | 393 | 1 | 1 | 100.00 |
CONT_ASSIGN | 399 | 1 | 1 | 100.00 |
CONT_ASSIGN | 407 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 442 | 1 | 1 | 100.00 |
CONT_ASSIGN | 445 | 1 | 1 | 100.00 |
CONT_ASSIGN | 451 | 1 | 1 | 100.00 |
CONT_ASSIGN | 456 | 1 | 1 | 100.00 |
CONT_ASSIGN | 459 | 1 | 1 | 100.00 |
CONT_ASSIGN | 491 | 1 | 1 | 100.00 |
CONT_ASSIGN | 494 | 1 | 1 | 100.00 |
CONT_ASSIGN | 497 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 504 | 1 | 1 | 100.00 |
CONT_ASSIGN | 505 | 1 | 1 | 100.00 |
CONT_ASSIGN | 513 | 1 | 1 | 100.00 |
CONT_ASSIGN | 521 | 1 | 1 | 100.00 |
CONT_ASSIGN | 523 | 1 | 1 | 100.00 |
CONT_ASSIGN | 597 | 1 | 1 | 100.00 |
CONT_ASSIGN | 598 | 1 | 1 | 100.00 |
ALWAYS | 600 | 6 | 6 | 100.00 |
CONT_ASSIGN | 610 | 1 | 1 | 100.00 |
CONT_ASSIGN | 614 | 1 | 1 | 100.00 |
CONT_ASSIGN | 617 | 1 | 1 | 100.00 |
CONT_ASSIGN | 624 | 1 | 1 | 100.00 |
CONT_ASSIGN | 628 | 1 | 1 | 100.00 |
CONT_ASSIGN | 636 | 1 | 1 | 100.00 |
CONT_ASSIGN | 654 | 1 | 1 | 100.00 |
CONT_ASSIGN | 659 | 1 | 1 | 100.00 |
CONT_ASSIGN | 664 | 1 | 1 | 100.00 |
CONT_ASSIGN | 664 | 1 | 1 | 100.00 |
CONT_ASSIGN | 664 | 1 | 1 | 100.00 |
CONT_ASSIGN | 664 | 1 | 1 | 100.00 |
ALWAYS | 670 | 8 | 8 | 100.00 |
CONT_ASSIGN | 683 | 1 | 1 | 100.00 |
CONT_ASSIGN | 704 | 1 | 1 | 100.00 |
CONT_ASSIGN | 724 | 1 | 1 | 100.00 |
CONT_ASSIGN | 736 | 1 | 1 | 100.00 |
CONT_ASSIGN | 738 | 1 | 1 | 100.00 |
CONT_ASSIGN | 744 | 1 | 1 | 100.00 |
CONT_ASSIGN | 745 | 1 | 1 | 100.00 |
CONT_ASSIGN | 747 | 1 | 1 | 100.00 |
CONT_ASSIGN | 751 | 1 | 1 | 100.00 |
CONT_ASSIGN | 762 | 1 | 1 | 100.00 |
CONT_ASSIGN | 775 | 1 | 1 | 100.00 |
CONT_ASSIGN | 787 | 1 | 1 | 100.00 |
CONT_ASSIGN | 790 | 1 | 1 | 100.00 |
CONT_ASSIGN | 794 | 1 | 1 | 100.00 |
CONT_ASSIGN | 797 | 1 | 1 | 100.00 |
CONT_ASSIGN | 800 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
137 |
1 |
1 |
140 |
4 |
4 |
141 |
4 |
4 |
146 |
4 |
4 |
152 |
1 |
1 |
154 |
3 |
3 |
186 |
1 |
1 |
193 |
4 |
4 |
194 |
4 |
4 |
196 |
4 |
4 |
212 |
4 |
4 |
218 |
4 |
4 |
222 |
4 |
4 |
229 |
1 |
1 |
232 |
1 |
1 |
257 |
1 |
1 |
258 |
1 |
1 |
259 |
1 |
1 |
260 |
1 |
1 |
|
|
|
MISSING_ELSE |
291 |
1 |
1 |
292 |
1 |
1 |
302 |
1 |
1 |
305 |
1 |
1 |
308 |
1 |
1 |
326 |
1 |
1 |
331 |
1 |
1 |
360 |
1 |
1 |
361 |
1 |
1 |
362 |
1 |
1 |
363 |
1 |
1 |
364 |
1 |
1 |
365 |
1 |
1 |
366 |
1 |
1 |
367 |
1 |
1 |
368 |
1 |
1 |
369 |
1 |
1 |
371 |
1 |
1 |
372 |
1 |
1 |
|
|
|
MISSING_ELSE |
377 |
1 |
1 |
382 |
1 |
1 |
393 |
1 |
1 |
399 |
1 |
1 |
407 |
1 |
1 |
428 |
1 |
1 |
432 |
1 |
1 |
442 |
1 |
1 |
445 |
1 |
1 |
451 |
1 |
1 |
456 |
1 |
1 |
459 |
1 |
1 |
491 |
1 |
1 |
494 |
1 |
1 |
497 |
1 |
1 |
501 |
1 |
1 |
503 |
1 |
1 |
504 |
1 |
1 |
505 |
1 |
1 |
513 |
1 |
1 |
521 |
1 |
1 |
523 |
1 |
1 |
597 |
1 |
1 |
598 |
1 |
1 |
600 |
1 |
1 |
601 |
1 |
1 |
602 |
1 |
1 |
603 |
1 |
1 |
604 |
1 |
1 |
605 |
1 |
1 |
|
|
|
MISSING_ELSE |
610 |
1 |
1 |
614 |
1 |
1 |
617 |
1 |
1 |
624 |
1 |
1 |
628 |
1 |
1 |
636 |
1 |
1 |
654 |
1 |
1 |
659 |
1 |
1 |
664 |
4 |
4 |
670 |
1 |
1 |
671 |
1 |
1 |
672 |
1 |
1 |
673 |
1 |
1 |
674 |
1 |
1 |
675 |
1 |
1 |
676 |
1 |
1 |
677 |
1 |
1 |
|
|
|
MISSING_ELSE |
683 |
1 |
1 |
704 |
1 |
1 |
724 |
1 |
1 |
736 |
1 |
1 |
738 |
1 |
1 |
744 |
1 |
1 |
745 |
1 |
1 |
747 |
1 |
1 |
751 |
1 |
1 |
762 |
1 |
1 |
775 |
1 |
1 |
787 |
1 |
1 |
790 |
1 |
1 |
794 |
1 |
1 |
797 |
1 |
1 |
800 |
1 |
1 |
Cond Coverage for Module :
flash_phy_rd
| Total | Covered | Percent |
Conditions | 458 | 417 | 91.05 |
Logical | 458 | 417 | 91.05 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 140
EXPRESSION (read_buf[0].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 140
EXPRESSION (read_buf[1].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 140
EXPRESSION (read_buf[2].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 140
EXPRESSION (read_buf[3].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
EXPRESSION (read_buf[0].attr == Wip)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
EXPRESSION (read_buf[1].attr == Wip)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
EXPRESSION (read_buf[2].attr == Wip)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
EXPRESSION (read_buf[3].attr == Wip)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
--------------1-------------- ------------------------------------2-----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T21,T34,T48 |
1 | 0 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (read_buf[0].attr == Invalid)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
-------------1------------- -------2------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T184 |
1 | 1 | 1 | Covered | T21,T34,T48 |
LINE 146
SUB-EXPRESSION (read_buf[0].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
--------------1-------------- ------------------------------------2-----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T34,T23,T48 |
1 | 0 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (read_buf[1].attr == Invalid)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
-------------1------------- -------2------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T34,T23,T48 |
LINE 146
SUB-EXPRESSION (read_buf[1].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
--------------1-------------- ------------------------------------2-----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T34,T48,T49 |
1 | 0 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (read_buf[2].attr == Invalid)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
-------------1------------- -------2------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T34,T48,T49 |
LINE 146
SUB-EXPRESSION (read_buf[2].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
--------------1-------------- ------------------------------------2-----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T34,T48,T49 |
1 | 0 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (read_buf[3].attr == Invalid)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
-------------1------------- -------2------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T34,T48,T49 |
LINE 146
SUB-EXPRESSION (read_buf[3].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 154
EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
-------1------ ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 154
EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 154
EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 167
SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
-----------1---------- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (req_o & ack_i & no_match)
--1-- --2-- ----3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T8,T39,T68 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 186
EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 193
EXPRESSION (read_buf[0].part == part_i)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 193
EXPRESSION (read_buf[1].part == part_i)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 193
EXPRESSION (read_buf[2].part == part_i)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 193
EXPRESSION (read_buf[3].part == part_i)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 194
EXPRESSION (read_buf[0].info_sel == info_sel_i)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 194
EXPRESSION (read_buf[1].info_sel == info_sel_i)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 194
EXPRESSION (read_buf[2].info_sel == info_sel_i)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 194
EXPRESSION (read_buf[3].info_sel == info_sel_i)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION
Number Term
1 req_i &
2 buf_en_q &
3 (buf_valid[0] | buf_wip[0]) &
4 (read_buf[0].addr == flash_word_addr) &
5 ((~read_buf[0].err)) &
6 gen_buf_match[0].part_match &
7 gen_buf_match[0].info_sel_match)
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | 1 | 1 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | 1 | 1 | 1 | Covered | T1,T4,T43 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | Covered | T34,T48,T49 |
1 | 1 | 1 | 1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 1 | 1 | 0 | Covered | T7,T68,T126 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
------1----- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION
Number Term
1 req_i &
2 buf_en_q &
3 (buf_valid[1] | buf_wip[1]) &
4 (read_buf[1].addr == flash_word_addr) &
5 ((~read_buf[1].err)) &
6 gen_buf_match[1].part_match &
7 gen_buf_match[1].info_sel_match)
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | 1 | 1 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | 1 | 1 | 1 | Covered | T1,T4,T43 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | Covered | T34,T49,T143 |
1 | 1 | 1 | 1 | 1 | 0 | 1 | Covered | T185 |
1 | 1 | 1 | 1 | 1 | 1 | 0 | Covered | T7,T8,T186 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
------1----- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION
Number Term
1 req_i &
2 buf_en_q &
3 (buf_valid[2] | buf_wip[2]) &
4 (read_buf[2].addr == flash_word_addr) &
5 ((~read_buf[2].err)) &
6 gen_buf_match[2].part_match &
7 gen_buf_match[2].info_sel_match)
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | 1 | 1 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | 1 | 1 | 1 | Covered | T1,T4,T43 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | Covered | T34,T48,T49 |
1 | 1 | 1 | 1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 1 | 1 | 0 | Covered | T126,T187,T188 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
------1----- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION
Number Term
1 req_i &
2 buf_en_q &
3 (buf_valid[3] | buf_wip[3]) &
4 (read_buf[3].addr == flash_word_addr) &
5 ((~read_buf[3].err)) &
6 gen_buf_match[3].part_match &
7 gen_buf_match[3].info_sel_match)
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | 1 | 1 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | 1 | 1 | 1 | Covered | T1,T4,T43 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | Covered | T34,T48,T49 |
1 | 1 | 1 | 1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 1 | 1 | 0 | Covered | T8,T96,T127 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
------1----- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 212
EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
------------------1------------------ -------------2------------- ---------------3---------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T68,T126 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 212
SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 212
EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
------------------1------------------ -------------2------------- ---------------3---------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T8,T189 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 212
SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 212
EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
------------------1------------------ -------------2------------- ---------------3---------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T126,T189,T187 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 212
SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 212
EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
------------------1------------------ -------------2------------- ---------------3---------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T8,T96,T127 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 212
SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 218
EXPRESSION
Number Term
1 (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) &
2 gen_buf_match[0].part_match &
3 gen_buf_match[0].info_sel_match)
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T3,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T8,T33 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 218
SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
-----------------------------------------------------------1-----------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 218
EXPRESSION
Number Term
1 (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) &
2 gen_buf_match[1].part_match &
3 gen_buf_match[1].info_sel_match)
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T3,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T8,T39 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 218
SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
-----------------------------------------------------------1-----------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 218
EXPRESSION
Number Term
1 (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) &
2 gen_buf_match[2].part_match &
3 gen_buf_match[2].info_sel_match)
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T3,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T8,T33 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 218
SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
-----------------------------------------------------------1-----------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 218
EXPRESSION
Number Term
1 (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) &
2 gen_buf_match[3].part_match &
3 gen_buf_match[3].info_sel_match)
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T3,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T8,T39 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 218
SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
-----------------------------------------------------------1-----------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 222
EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
------1----- ------------------------------------------------------2-----------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T4 |
LINE 222
SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
-----1---- ---------------------2--------------------- -----------------------3-----------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T2,T4 |
0 | 1 | 0 | Covered | T1,T2,T4 |
1 | 0 | 0 | Covered | T2,T5,T52 |
LINE 222
SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
---1-- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T4 |
LINE 222
SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
-----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T4,T5 |
1 | 1 | Covered | T1,T2,T4 |
LINE 222
EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
------1----- ------------------------------------------------------2-----------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T4 |
LINE 222
SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
-----1---- ---------------------2--------------------- -----------------------3-----------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T2,T4 |
0 | 1 | 0 | Covered | T1,T2,T4 |
1 | 0 | 0 | Covered | T2,T5,T52 |
LINE 222
SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
---1-- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T4 |
LINE 222
SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
-----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T4,T5 |
1 | 1 | Covered | T1,T2,T4 |
LINE 222
EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
------1----- ------------------------------------------------------2-----------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T4 |
LINE 222
SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
-----1---- ---------------------2--------------------- -----------------------3-----------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T2,T4 |
0 | 1 | 0 | Covered | T1,T2,T4 |
1 | 0 | 0 | Covered | T2,T5,T52 |
LINE 222
SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
---1-- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T4 |
LINE 222
SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
-----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T4,T5 |
1 | 1 | Covered | T1,T2,T4 |
LINE 222
EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
------1----- ------------------------------------------------------2-----------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T4 |
LINE 222
SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
-----1---- ---------------------2--------------------- -----------------------3-----------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T2,T4 |
0 | 1 | 0 | Covered | T1,T2,T4 |
1 | 0 | 0 | Covered | T2,T5,T52 |
LINE 222
SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
---1-- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T4 |
LINE 222
SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
-----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T4,T5 |
1 | 1 | Covered | T1,T2,T4 |
LINE 232
EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 239
EXPRESSION (rdy_o & alloc[0])
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T48,T49,T190 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 239
EXPRESSION (rdy_o & alloc[1])
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T7,T32 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 239
EXPRESSION (rdy_o & alloc[2])
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T32,T33,T69 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 239
EXPRESSION (rdy_o & alloc[3])
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T8,T32 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 291
EXPRESSION (req_o & ack_i)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T39,T68 |
1 | 1 | Covered | T1,T2,T3 |
LINE 292
EXPRESSION (rd_busy & done_i)
---1--- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 302
EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 305
EXPRESSION (req_i && rdy_o)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T7,T21 |
1 | 1 | Covered | T1,T2,T3 |
LINE 308
EXPRESSION (rsp_fifo_vld & data_valid_o)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 377
EXPRESSION (((~rd_busy)) | rd_done)
------1----- ---2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 382
EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T38,T56,T57 |
1 | 0 | Covered | T38,T56,T57 |
1 | 1 | Covered | T1,T2,T3 |
LINE 393
EXPRESSION (buf_en_q == buf_en_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 399
EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
--------------------------------1------------------------------- -----------2----------- --------3------- -----------------4-----------------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 0 | Covered | T7,T21,T8 |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 399
SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 399
SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
--1-- ----2---- ------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T8,T32 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 399
SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 407
EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
--1-- --------2------- ----3---- ------4------ ----5--- -----------------6-----------------
-1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | 1 | 1 | Covered | T191,T161 |
1 | 1 | 0 | 1 | 1 | 1 | Covered | T6,T8,T32 |
1 | 1 | 1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | 1 | 0 | Covered | T7,T30,T33 |
1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 407
SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 428
EXPRESSION (rd_done && rd_attrs.ecc)
---1--- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T3 |
LINE 432
EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
---1--- ------------------------2------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T68,T69 |
LINE 432
SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 442
EXPRESSION (valid_ecc & ecc_multi_err)
----1---- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T6,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T21,T34,T23 |
LINE 451
EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T21,T32,T33 |
LINE 451
SUB-EXPRESSION (data_err | ecc_single_err_o)
----1--- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T32,T33,T34 |
1 | 0 | Covered | T21,T34,T23 |
LINE 456
EXPRESSION (valid_ecc & ecc_single_err)
----1---- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T6,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T32,T33,T34 |
LINE 491
EXPRESSION (data_fifo_rdy & mask_fifo_rdy & addr_xor_fifo_rdy)
------1------ ------2------ --------3--------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T38,T56,T57 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T7,T8,T32 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 494
EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
---1--- ---------2--------- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T68,T69,T96 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 497
EXPRESSION (rd_done & rd_attrs.descramble & data_erased)
---1--- ---------2--------- -----3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T5,T126,T127 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T68,T69,T96 |
LINE 501
EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
---1--- ------2----- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T8,T30,T68 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 503
EXPRESSION (fifo_data_valid & descram_q)
-------1------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 504
EXPRESSION (fifo_data_valid & dropmsk_q)
-------1------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T68,T69,T96 |
LINE 505
EXPRESSION (fifo_data_valid & forward_q)
-------1------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 513
EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : (hint_dropmsk ? mask_valid : fifo_data_valid))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 513
SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 513
SUB-EXPRESSION (hint_dropmsk ? mask_valid : fifo_data_valid)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T68,T69,T96 |
LINE 521
EXPRESSION (hint_forward & (hint_dropmsk ? mask_valid : 1'b1))
------1----- -----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T68,T69,T96 |
1 | 1 | Covered | T1,T2,T3 |
LINE 521
SUB-EXPRESSION (hint_dropmsk ? mask_valid : 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T68,T69,T96 |
LINE 523
EXPRESSION (fifo_data_ready | fifo_forward_pop)
-------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
LINE 597
EXPRESSION (req_o & ack_i & descramble_i)
--1-- --2-- ------3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T8,T39,T68 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 598
EXPRESSION (calc_req_o & calc_ack_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T59 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 614
EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
-------1------- -----2---- ------3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T7,T32,T30 |
1 | 1 | 0 | Covered | T68,T69,T96 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 624
EXPRESSION
Number Term
1 forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 624
SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 628
EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 628
SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 636
EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
---1--- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 636
SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
--------1-------- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 654
EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 654
SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 654
SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
--------1-------- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 659
EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
------1----- -----2---- --------------------------3-------------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T38,T56,T57 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 659
SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
------1------ -----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 659
SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
-----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 664
EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
----1--- ------2----- ------------3------------ ------4-----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 664
EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
----1--- ------2----- ------------3------------ ------4-----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 664
EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
----1--- ------2----- ------------3------------ ------4-----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 664
EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
----1--- ------2----- ------------3------------ ------4-----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 677
EXPRESSION (buf_rsp_err | read_buf[i].err)
-----1----- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T184 |
1 | 0 | Not Covered | |
LINE 683
EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 736
EXPRESSION (data_err_o ? inv_data_integ : data_out_intg)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T21,T104,T146 |
LINE 747
EXPRESSION (((|buf_rsp_match)) ? buf_addr_xor_muxed : fifo_addr_xor_muxed)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 775
EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 775
SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
---------------------------------------------1---------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 787
EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
-------1------- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 790
EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
--------------------------------------1------------------------------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T21,T104,T146 |
LINE 790
SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
------1----- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T21,T104,T146 |
LINE 790
SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
----1---- ----2--- -----------------3----------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Not Covered | |
0 | 1 | 0 | Covered | T1,T2,T3 |
1 | 0 | 0 | Covered | T34,T23,T48 |
LINE 790
SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
---------1-------- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T184 |
LINE 794
EXPRESSION (data_valid_o & intg_err)
------1----- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T21,T104,T146 |
Branch Coverage for Module :
flash_phy_rd
| Line No. | Total | Covered | Percent |
Branches |
|
43 |
43 |
100.00 |
TERNARY |
186 |
2 |
2 |
100.00 |
TERNARY |
232 |
2 |
2 |
100.00 |
TERNARY |
302 |
2 |
2 |
100.00 |
TERNARY |
451 |
2 |
2 |
100.00 |
TERNARY |
513 |
3 |
3 |
100.00 |
TERNARY |
624 |
3 |
3 |
100.00 |
TERNARY |
628 |
3 |
3 |
100.00 |
TERNARY |
654 |
3 |
3 |
100.00 |
TERNARY |
683 |
2 |
2 |
100.00 |
TERNARY |
736 |
2 |
2 |
100.00 |
TERNARY |
747 |
2 |
2 |
100.00 |
TERNARY |
775 |
2 |
2 |
100.00 |
TERNARY |
167 |
2 |
2 |
100.00 |
IF |
257 |
3 |
3 |
100.00 |
IF |
360 |
4 |
4 |
100.00 |
IF |
600 |
4 |
4 |
100.00 |
IF |
674 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 186 ((|buf_invalid_alloc)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 232 (no_match) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 302 ((|alloc)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 451 ((data_err | ecc_single_err_o)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T21,T32,T33 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 513 (hint_descram) ?
-2-: 513 (hint_dropmsk) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T68,T69,T96 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 624 (forward) ?
-2-: 624 (hint_descram) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 628 (forward) ?
-2-: 628 ((~hint_forward)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 654 (forward) ?
-2-: 654 (((~hint_forward) & fifo_data_ready)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 683 ((|buf_rsp_match)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 736 (data_err_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T21,T104,T146 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 747 ((|buf_rsp_match)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 775 (rsp_fifo_rdata.intg_ecc_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (((|buf_invalid_alloc) | all_buf_dependency)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 257 if ((!rst_ni))
-2-: 259 if (idle_o)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 360 if ((!rst_ni))
-2-: 364 if (rd_start)
-3-: 371 if (rd_done)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 600 if ((!rst_ni))
-2-: 602 if (calc_req_start)
-3-: 604 if (calc_req_done)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 674 if (buf_rsp_match[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
flash_phy_rd
Assertion Details
BufferMatchEcc_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
751557086 |
1600959 |
0 |
0 |
T1 |
2491 |
10 |
0 |
0 |
T2 |
376740 |
117 |
0 |
0 |
T3 |
2172 |
11 |
0 |
0 |
T4 |
839422 |
2808 |
0 |
0 |
T5 |
273450 |
1884 |
0 |
0 |
T6 |
0 |
13353 |
0 |
0 |
T7 |
0 |
2042 |
0 |
0 |
T8 |
0 |
376 |
0 |
0 |
T12 |
6718 |
0 |
0 |
0 |
T13 |
8194 |
0 |
0 |
0 |
T17 |
2604 |
0 |
0 |
0 |
T18 |
6970 |
0 |
0 |
0 |
T19 |
9066 |
0 |
0 |
0 |
T21 |
0 |
29 |
0 |
0 |
T32 |
0 |
78 |
0 |
0 |
T43 |
0 |
3088 |
0 |
0 |
T52 |
0 |
406 |
0 |
0 |
T53 |
0 |
1 |
0 |
0 |
T54 |
0 |
62 |
0 |
0 |
T55 |
1247 |
0 |
0 |
0 |
ExclusiveOps_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
751557086 |
749899942 |
0 |
0 |
T1 |
4982 |
4806 |
0 |
0 |
T2 |
376740 |
376736 |
0 |
0 |
T3 |
2172 |
2070 |
0 |
0 |
T4 |
839422 |
804928 |
0 |
0 |
T5 |
273450 |
273432 |
0 |
0 |
T12 |
6718 |
5324 |
0 |
0 |
T13 |
8194 |
6788 |
0 |
0 |
T17 |
2604 |
2438 |
0 |
0 |
T18 |
6970 |
6796 |
0 |
0 |
T19 |
9066 |
8894 |
0 |
0 |
ExclusiveProgHazard_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
751557086 |
749899942 |
0 |
0 |
T1 |
4982 |
4806 |
0 |
0 |
T2 |
376740 |
376736 |
0 |
0 |
T3 |
2172 |
2070 |
0 |
0 |
T4 |
839422 |
804928 |
0 |
0 |
T5 |
273450 |
273432 |
0 |
0 |
T12 |
6718 |
5324 |
0 |
0 |
T13 |
8194 |
6788 |
0 |
0 |
T17 |
2604 |
2438 |
0 |
0 |
T18 |
6970 |
6796 |
0 |
0 |
T19 |
9066 |
8894 |
0 |
0 |
ExclusiveState_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
751557086 |
749899942 |
0 |
0 |
T1 |
4982 |
4806 |
0 |
0 |
T2 |
376740 |
376736 |
0 |
0 |
T3 |
2172 |
2070 |
0 |
0 |
T4 |
839422 |
804928 |
0 |
0 |
T5 |
273450 |
273432 |
0 |
0 |
T12 |
6718 |
5324 |
0 |
0 |
T13 |
8194 |
6788 |
0 |
0 |
T17 |
2604 |
2438 |
0 |
0 |
T18 |
6970 |
6796 |
0 |
0 |
T19 |
9066 |
8894 |
0 |
0 |
ForwardCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
751557086 |
3622368 |
0 |
0 |
T1 |
2491 |
10 |
0 |
0 |
T2 |
376740 |
135 |
0 |
0 |
T3 |
2172 |
11 |
0 |
0 |
T4 |
839422 |
0 |
0 |
0 |
T5 |
273450 |
1901 |
0 |
0 |
T6 |
0 |
31525 |
0 |
0 |
T7 |
0 |
816 |
0 |
0 |
T8 |
0 |
14096 |
0 |
0 |
T12 |
6718 |
0 |
0 |
0 |
T13 |
8194 |
0 |
0 |
0 |
T17 |
2604 |
0 |
0 |
0 |
T18 |
6970 |
0 |
0 |
0 |
T19 |
9066 |
0 |
0 |
0 |
T30 |
0 |
12712 |
0 |
0 |
T31 |
0 |
235 |
0 |
0 |
T32 |
0 |
88 |
0 |
0 |
T52 |
0 |
466 |
0 |
0 |
T53 |
0 |
16118 |
0 |
0 |
T54 |
0 |
67 |
0 |
0 |
T55 |
1247 |
0 |
0 |
0 |
IdleCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
751557086 |
99741235 |
0 |
0 |
T1 |
2491 |
158 |
0 |
0 |
T2 |
376740 |
1055235 |
0 |
0 |
T3 |
2172 |
161 |
0 |
0 |
T4 |
839422 |
42584 |
0 |
0 |
T5 |
273450 |
5814 |
0 |
0 |
T6 |
0 |
879916 |
0 |
0 |
T7 |
0 |
30420 |
0 |
0 |
T8 |
0 |
24577 |
0 |
0 |
T12 |
6718 |
412 |
0 |
0 |
T13 |
8194 |
800 |
0 |
0 |
T17 |
2604 |
128 |
0 |
0 |
T18 |
6970 |
128 |
0 |
0 |
T19 |
9066 |
128 |
0 |
0 |
T21 |
0 |
21 |
0 |
0 |
T32 |
0 |
369 |
0 |
0 |
T52 |
0 |
616 |
0 |
0 |
T53 |
0 |
412438 |
0 |
0 |
T54 |
0 |
196 |
0 |
0 |
T55 |
1247 |
0 |
0 |
0 |
MaxBufs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2076 |
2076 |
0 |
0 |
T1 |
2 |
2 |
0 |
0 |
T2 |
2 |
2 |
0 |
0 |
T3 |
2 |
2 |
0 |
0 |
T4 |
2 |
2 |
0 |
0 |
T5 |
2 |
2 |
0 |
0 |
T12 |
2 |
2 |
0 |
0 |
T13 |
2 |
2 |
0 |
0 |
T17 |
2 |
2 |
0 |
0 |
T18 |
2 |
2 |
0 |
0 |
T19 |
2 |
2 |
0 |
0 |
OneHotAlloc_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
751557086 |
749899942 |
0 |
0 |
T1 |
4982 |
4806 |
0 |
0 |
T2 |
376740 |
376736 |
0 |
0 |
T3 |
2172 |
2070 |
0 |
0 |
T4 |
839422 |
804928 |
0 |
0 |
T5 |
273450 |
273432 |
0 |
0 |
T12 |
6718 |
5324 |
0 |
0 |
T13 |
8194 |
6788 |
0 |
0 |
T17 |
2604 |
2438 |
0 |
0 |
T18 |
6970 |
6796 |
0 |
0 |
T19 |
9066 |
8894 |
0 |
0 |
OneHotMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
751557086 |
749899942 |
0 |
0 |
T1 |
4982 |
4806 |
0 |
0 |
T2 |
376740 |
376736 |
0 |
0 |
T3 |
2172 |
2070 |
0 |
0 |
T4 |
839422 |
804928 |
0 |
0 |
T5 |
273450 |
273432 |
0 |
0 |
T12 |
6718 |
5324 |
0 |
0 |
T13 |
8194 |
6788 |
0 |
0 |
T17 |
2604 |
2438 |
0 |
0 |
T18 |
6970 |
6796 |
0 |
0 |
T19 |
9066 |
8894 |
0 |
0 |
OneHotRspMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
751557086 |
749899942 |
0 |
0 |
T1 |
4982 |
4806 |
0 |
0 |
T2 |
376740 |
376736 |
0 |
0 |
T3 |
2172 |
2070 |
0 |
0 |
T4 |
839422 |
804928 |
0 |
0 |
T5 |
273450 |
273432 |
0 |
0 |
T12 |
6718 |
5324 |
0 |
0 |
T13 |
8194 |
6788 |
0 |
0 |
T17 |
2604 |
2438 |
0 |
0 |
T18 |
6970 |
6796 |
0 |
0 |
T19 |
9066 |
8894 |
0 |
0 |
OneHotUpdate_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
751557086 |
749899942 |
0 |
0 |
T1 |
4982 |
4806 |
0 |
0 |
T2 |
376740 |
376736 |
0 |
0 |
T3 |
2172 |
2070 |
0 |
0 |
T4 |
839422 |
804928 |
0 |
0 |
T5 |
273450 |
273432 |
0 |
0 |
T12 |
6718 |
5324 |
0 |
0 |
T13 |
8194 |
6788 |
0 |
0 |
T17 |
2604 |
2438 |
0 |
0 |
T18 |
6970 |
6796 |
0 |
0 |
T19 |
9066 |
8894 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
| Line No. | Total | Covered | Percent |
TOTAL | | 133 | 133 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 152 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 186 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 229 | 1 | 1 | 100.00 |
CONT_ASSIGN | 232 | 1 | 1 | 100.00 |
ALWAYS | 257 | 4 | 4 | 100.00 |
CONT_ASSIGN | 291 | 1 | 1 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 302 | 1 | 1 | 100.00 |
CONT_ASSIGN | 305 | 1 | 1 | 100.00 |
CONT_ASSIGN | 308 | 1 | 1 | 100.00 |
CONT_ASSIGN | 326 | 1 | 1 | 100.00 |
CONT_ASSIGN | 331 | 1 | 1 | 100.00 |
ALWAYS | 360 | 12 | 12 | 100.00 |
CONT_ASSIGN | 377 | 1 | 1 | 100.00 |
CONT_ASSIGN | 382 | 1 | 1 | 100.00 |
CONT_ASSIGN | 393 | 1 | 1 | 100.00 |
CONT_ASSIGN | 399 | 1 | 1 | 100.00 |
CONT_ASSIGN | 407 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 442 | 1 | 1 | 100.00 |
CONT_ASSIGN | 445 | 1 | 1 | 100.00 |
CONT_ASSIGN | 451 | 1 | 1 | 100.00 |
CONT_ASSIGN | 456 | 1 | 1 | 100.00 |
CONT_ASSIGN | 459 | 1 | 1 | 100.00 |
CONT_ASSIGN | 491 | 1 | 1 | 100.00 |
CONT_ASSIGN | 494 | 1 | 1 | 100.00 |
CONT_ASSIGN | 497 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 504 | 1 | 1 | 100.00 |
CONT_ASSIGN | 505 | 1 | 1 | 100.00 |
CONT_ASSIGN | 513 | 1 | 1 | 100.00 |
CONT_ASSIGN | 521 | 1 | 1 | 100.00 |
CONT_ASSIGN | 523 | 1 | 1 | 100.00 |
CONT_ASSIGN | 597 | 1 | 1 | 100.00 |
CONT_ASSIGN | 598 | 1 | 1 | 100.00 |
ALWAYS | 600 | 6 | 6 | 100.00 |
CONT_ASSIGN | 610 | 1 | 1 | 100.00 |
CONT_ASSIGN | 614 | 1 | 1 | 100.00 |
CONT_ASSIGN | 617 | 1 | 1 | 100.00 |
CONT_ASSIGN | 624 | 1 | 1 | 100.00 |
CONT_ASSIGN | 628 | 1 | 1 | 100.00 |
CONT_ASSIGN | 636 | 1 | 1 | 100.00 |
CONT_ASSIGN | 654 | 1 | 1 | 100.00 |
CONT_ASSIGN | 659 | 1 | 1 | 100.00 |
CONT_ASSIGN | 664 | 1 | 1 | 100.00 |
CONT_ASSIGN | 664 | 1 | 1 | 100.00 |
CONT_ASSIGN | 664 | 1 | 1 | 100.00 |
CONT_ASSIGN | 664 | 1 | 1 | 100.00 |
ALWAYS | 670 | 8 | 8 | 100.00 |
CONT_ASSIGN | 683 | 1 | 1 | 100.00 |
CONT_ASSIGN | 704 | 1 | 1 | 100.00 |
CONT_ASSIGN | 724 | 1 | 1 | 100.00 |
CONT_ASSIGN | 736 | 1 | 1 | 100.00 |
CONT_ASSIGN | 738 | 1 | 1 | 100.00 |
CONT_ASSIGN | 744 | 1 | 1 | 100.00 |
CONT_ASSIGN | 745 | 1 | 1 | 100.00 |
CONT_ASSIGN | 747 | 1 | 1 | 100.00 |
CONT_ASSIGN | 751 | 1 | 1 | 100.00 |
CONT_ASSIGN | 762 | 1 | 1 | 100.00 |
CONT_ASSIGN | 775 | 1 | 1 | 100.00 |
CONT_ASSIGN | 787 | 1 | 1 | 100.00 |
CONT_ASSIGN | 790 | 1 | 1 | 100.00 |
CONT_ASSIGN | 794 | 1 | 1 | 100.00 |
CONT_ASSIGN | 797 | 1 | 1 | 100.00 |
CONT_ASSIGN | 800 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
137 |
1 |
1 |
140 |
4 |
4 |
141 |
4 |
4 |
146 |
4 |
4 |
152 |
1 |
1 |
154 |
3 |
3 |
186 |
1 |
1 |
193 |
4 |
4 |
194 |
4 |
4 |
196 |
4 |
4 |
212 |
4 |
4 |
218 |
4 |
4 |
222 |
4 |
4 |
229 |
1 |
1 |
232 |
1 |
1 |
257 |
1 |
1 |
258 |
1 |
1 |
259 |
1 |
1 |
260 |
1 |
1 |
|
|
|
MISSING_ELSE |
291 |
1 |
1 |
292 |
1 |
1 |
302 |
1 |
1 |
305 |
1 |
1 |
308 |
1 |
1 |
326 |
1 |
1 |
331 |
1 |
1 |
360 |
1 |
1 |
361 |
1 |
1 |
362 |
1 |
1 |
363 |
1 |
1 |
364 |
1 |
1 |
365 |
1 |
1 |
366 |
1 |
1 |
367 |
1 |
1 |
368 |
1 |
1 |
369 |
1 |
1 |
371 |
1 |
1 |
372 |
1 |
1 |
|
|
|
MISSING_ELSE |
377 |
1 |
1 |
382 |
1 |
1 |
393 |
1 |
1 |
399 |
1 |
1 |
407 |
1 |
1 |
428 |
1 |
1 |
432 |
1 |
1 |
442 |
1 |
1 |
445 |
1 |
1 |
451 |
1 |
1 |
456 |
1 |
1 |
459 |
1 |
1 |
491 |
1 |
1 |
494 |
1 |
1 |
497 |
1 |
1 |
501 |
1 |
1 |
503 |
1 |
1 |
504 |
1 |
1 |
505 |
1 |
1 |
513 |
1 |
1 |
521 |
1 |
1 |
523 |
1 |
1 |
597 |
1 |
1 |
598 |
1 |
1 |
600 |
1 |
1 |
601 |
1 |
1 |
602 |
1 |
1 |
603 |
1 |
1 |
604 |
1 |
1 |
605 |
1 |
1 |
|
|
|
MISSING_ELSE |
610 |
1 |
1 |
614 |
1 |
1 |
617 |
1 |
1 |
624 |
1 |
1 |
628 |
1 |
1 |
636 |
1 |
1 |
654 |
1 |
1 |
659 |
1 |
1 |
664 |
4 |
4 |
670 |
1 |
1 |
671 |
1 |
1 |
672 |
1 |
1 |
673 |
1 |
1 |
674 |
1 |
1 |
675 |
1 |
1 |
676 |
1 |
1 |
677 |
1 |
1 |
|
|
|
MISSING_ELSE |
683 |
1 |
1 |
704 |
1 |
1 |
724 |
1 |
1 |
736 |
1 |
1 |
738 |
1 |
1 |
744 |
1 |
1 |
745 |
1 |
1 |
747 |
1 |
1 |
751 |
1 |
1 |
762 |
1 |
1 |
775 |
1 |
1 |
787 |
1 |
1 |
790 |
1 |
1 |
794 |
1 |
1 |
797 |
1 |
1 |
800 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
| Total | Covered | Percent |
Conditions | 458 | 413 | 90.17 |
Logical | 458 | 413 | 90.17 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 140
EXPRESSION (read_buf[0].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 140
EXPRESSION (read_buf[1].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 140
EXPRESSION (read_buf[2].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 140
EXPRESSION (read_buf[3].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
EXPRESSION (read_buf[0].attr == Wip)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
EXPRESSION (read_buf[1].attr == Wip)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
EXPRESSION (read_buf[2].attr == Wip)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
EXPRESSION (read_buf[3].attr == Wip)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
--------------1-------------- ------------------------------------2-----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T34,T48,T49 |
1 | 0 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (read_buf[0].attr == Invalid)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
-------------1------------- -------2------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T34,T48,T49 |
LINE 146
SUB-EXPRESSION (read_buf[0].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
--------------1-------------- ------------------------------------2-----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T34,T23,T48 |
1 | 0 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (read_buf[1].attr == Invalid)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
-------------1------------- -------2------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T34,T23,T48 |
LINE 146
SUB-EXPRESSION (read_buf[1].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
--------------1-------------- ------------------------------------2-----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T34,T48,T49 |
1 | 0 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (read_buf[2].attr == Invalid)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
-------------1------------- -------2------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T34,T48,T49 |
LINE 146
SUB-EXPRESSION (read_buf[2].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
--------------1-------------- ------------------------------------2-----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T34,T48,T49 |
1 | 0 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (read_buf[3].attr == Invalid)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
-------------1------------- -------2------- -----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T34,T48,T49 |
LINE 146
SUB-EXPRESSION (read_buf[3].attr == Valid)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 154
EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
-------1------ ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 154
EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 154
EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
-------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 167
SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
-----------1---------- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
LINE 167
EXPRESSION (req_o & ack_i & no_match)
--1-- --2-- ----3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T8,T39,T68 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 186
EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 193
EXPRESSION (read_buf[0].part == part_i)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 193
EXPRESSION (read_buf[1].part == part_i)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 193
EXPRESSION (read_buf[2].part == part_i)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 193
EXPRESSION (read_buf[3].part == part_i)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 194
EXPRESSION (read_buf[0].info_sel == info_sel_i)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 194
EXPRESSION (read_buf[1].info_sel == info_sel_i)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 194
EXPRESSION (read_buf[2].info_sel == info_sel_i)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 194
EXPRESSION (read_buf[3].info_sel == info_sel_i)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION
Number Term
1 req_i &
2 buf_en_q &
3 (buf_valid[0] | buf_wip[0]) &
4 (read_buf[0].addr == flash_word_addr) &
5 ((~read_buf[0].err)) &
6 gen_buf_match[0].part_match &
7 gen_buf_match[0].info_sel_match)
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | 1 | 1 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | 1 | 1 | 1 | Covered | T1,T4,T43 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | Covered | T34,T48,T143 |
1 | 1 | 1 | 1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 1 | 1 | 0 | Covered | T126,T133,T192 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
------1----- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION
Number Term
1 req_i &
2 buf_en_q &
3 (buf_valid[1] | buf_wip[1]) &
4 (read_buf[1].addr == flash_word_addr) &
5 ((~read_buf[1].err)) &
6 gen_buf_match[1].part_match &
7 gen_buf_match[1].info_sel_match)
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | 1 | 1 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | 1 | 1 | 1 | Covered | T1,T4,T43 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | Covered | T34,T143,T193 |
1 | 1 | 1 | 1 | 1 | 0 | 1 | Covered | T185 |
1 | 1 | 1 | 1 | 1 | 1 | 0 | Covered | T186,T187,T130 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
------1----- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION
Number Term
1 req_i &
2 buf_en_q &
3 (buf_valid[2] | buf_wip[2]) &
4 (read_buf[2].addr == flash_word_addr) &
5 ((~read_buf[2].err)) &
6 gen_buf_match[2].part_match &
7 gen_buf_match[2].info_sel_match)
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | 1 | 1 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | 1 | 1 | 1 | Covered | T1,T4,T43 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | Covered | T34,T143,T193 |
1 | 1 | 1 | 1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 1 | 1 | 0 | Covered | T126,T187,T194 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
------1----- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION
Number Term
1 req_i &
2 buf_en_q &
3 (buf_valid[3] | buf_wip[3]) &
4 (read_buf[3].addr == flash_word_addr) &
5 ((~read_buf[3].err)) &
6 gen_buf_match[3].part_match &
7 gen_buf_match[3].info_sel_match)
-1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | 1 | 1 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | 1 | 1 | 1 | Covered | T1,T4,T43 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | Covered | T34,T143,T193 |
1 | 1 | 1 | 1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 1 | 1 | 0 | Covered | T96,T127,T188 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
------1----- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 212
EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
------------------1------------------ -------------2------------- ---------------3---------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T126,T189 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 212
SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 212
EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
------------------1------------------ -------------2------------- ---------------3---------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T189,T186 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 212
SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 212
EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
------------------1------------------ -------------2------------- ---------------3---------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T126,T189,T187 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 212
SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 212
EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
------------------1------------------ -------------2------------- ---------------3---------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T96,T127,T189 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 212
SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 218
EXPRESSION
Number Term
1 (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) &
2 gen_buf_match[0].part_match &
3 gen_buf_match[0].info_sel_match)
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T3,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T8,T33 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 218
SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
-----------------------------------------------------------1-----------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 218
EXPRESSION
Number Term
1 (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) &
2 gen_buf_match[1].part_match &
3 gen_buf_match[1].info_sel_match)
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T3,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T8,T39 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 218
SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
-----------------------------------------------------------1-----------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 218
EXPRESSION
Number Term
1 (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) &
2 gen_buf_match[2].part_match &
3 gen_buf_match[2].info_sel_match)
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T3,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T8,T33 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 218
SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
-----------------------------------------------------------1-----------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 218
EXPRESSION
Number Term
1 (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) &
2 gen_buf_match[3].part_match &
3 gen_buf_match[3].info_sel_match)
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T3,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T8,T39 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 218
SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
-----------------------------------------------------------1-----------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 222
EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
------1----- ------------------------------------------------------2-----------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T5 |
LINE 222
SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
-----1---- ---------------------2--------------------- -----------------------3-----------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T2,T4 |
0 | 1 | 0 | Covered | T1,T2,T4 |
1 | 0 | 0 | Covered | T5,T52,T31 |
LINE 222
SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
---1-- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T4 |
LINE 222
SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
-----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T4,T5 |
1 | 1 | Covered | T1,T2,T4 |
LINE 222
EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
------1----- ------------------------------------------------------2-----------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T5 |
LINE 222
SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
-----1---- ---------------------2--------------------- -----------------------3-----------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T2,T4 |
0 | 1 | 0 | Covered | T1,T2,T4 |
1 | 0 | 0 | Covered | T5,T52,T31 |
LINE 222
SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
---1-- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T4 |
LINE 222
SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
-----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T4,T5 |
1 | 1 | Covered | T1,T2,T4 |
LINE 222
EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
------1----- ------------------------------------------------------2-----------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T5 |
LINE 222
SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
-----1---- ---------------------2--------------------- -----------------------3-----------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T2,T4 |
0 | 1 | 0 | Covered | T1,T2,T4 |
1 | 0 | 0 | Covered | T5,T52,T31 |
LINE 222
SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
---1-- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T4 |
LINE 222
SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
-----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T4,T5 |
1 | 1 | Covered | T1,T2,T4 |
LINE 222
EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
------1----- ------------------------------------------------------2-----------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T5 |
LINE 222
SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
-----1---- ---------------------2--------------------- -----------------------3-----------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T2,T4 |
0 | 1 | 0 | Covered | T1,T2,T4 |
1 | 0 | 0 | Covered | T5,T52,T31 |
LINE 222
SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
---1-- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T4 |
LINE 222
SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
-----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T4,T5 |
1 | 1 | Covered | T1,T2,T4 |
LINE 232
EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 239
EXPRESSION (rdy_o & alloc[0])
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T48,T49,T190 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 239
EXPRESSION (rdy_o & alloc[1])
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T32,T54 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 239
EXPRESSION (rdy_o & alloc[2])
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T32,T69,T96 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 239
EXPRESSION (rdy_o & alloc[3])
--1-- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T32,T69 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 291
EXPRESSION (req_o & ack_i)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T39,T68 |
1 | 1 | Covered | T1,T2,T3 |
LINE 292
EXPRESSION (rd_busy & done_i)
---1--- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 302
EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 305
EXPRESSION (req_i && rdy_o)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T7,T21 |
1 | 1 | Covered | T1,T2,T3 |
LINE 308
EXPRESSION (rsp_fifo_vld & data_valid_o)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 377
EXPRESSION (((~rd_busy)) | rd_done)
------1----- ---2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 382
EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T38,T56,T57 |
1 | 0 | Covered | T38,T56,T57 |
1 | 1 | Covered | T1,T2,T3 |
LINE 393
EXPRESSION (buf_en_q == buf_en_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 399
EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
--------------------------------1------------------------------- -----------2----------- --------3------- -----------------4-----------------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 0 | Covered | T7,T21,T8 |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 399
SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
----1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 399
SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
--1-- ----2---- ------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T7,T8,T32 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 399
SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 407
EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
--1-- --------2------- ----3---- ------4------ ----5--- -----------------6-----------------
-1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
0 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | 1 | 1 | Covered | T6,T8,T32 |
1 | 1 | 1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 1 | 1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | 1 | 0 | Covered | T33,T39,T67 |
1 | 1 | 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 407
SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 428
EXPRESSION (rd_done && rd_attrs.ecc)
---1--- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T3 |
LINE 432
EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
---1--- ------------------------2------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T68,T69 |
LINE 432
SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 442
EXPRESSION (valid_ecc & ecc_multi_err)
----1---- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T6,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T34,T23,T48 |
LINE 451
EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T32,T33,T34 |
LINE 451
SUB-EXPRESSION (data_err | ecc_single_err_o)
----1--- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T32,T33,T34 |
1 | 0 | Covered | T34,T23,T48 |
LINE 456
EXPRESSION (valid_ecc & ecc_single_err)
----1---- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T6,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T32,T33,T34 |
LINE 491
EXPRESSION (data_fifo_rdy & mask_fifo_rdy & addr_xor_fifo_rdy)
------1------ ------2------ --------3--------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T38,T56,T57 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T7,T8,T32 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 494
EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
---1--- ---------2--------- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T68,T69,T96 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 497
EXPRESSION (rd_done & rd_attrs.descramble & data_erased)
---1--- ---------2--------- -----3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T5,T126,T127 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T68,T69,T96 |
LINE 501
EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
---1--- ------2----- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T8,T68,T126 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 503
EXPRESSION (fifo_data_valid & descram_q)
-------1------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 504
EXPRESSION (fifo_data_valid & dropmsk_q)
-------1------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T68,T69,T96 |
LINE 505
EXPRESSION (fifo_data_valid & forward_q)
-------1------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 513
EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : (hint_dropmsk ? mask_valid : fifo_data_valid))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 513
SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 513
SUB-EXPRESSION (hint_dropmsk ? mask_valid : fifo_data_valid)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T68,T69,T96 |
LINE 521
EXPRESSION (hint_forward & (hint_dropmsk ? mask_valid : 1'b1))
------1----- -----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T68,T69,T96 |
1 | 1 | Covered | T1,T2,T3 |
LINE 521
SUB-EXPRESSION (hint_dropmsk ? mask_valid : 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T68,T69,T96 |
LINE 523
EXPRESSION (fifo_data_ready | fifo_forward_pop)
-------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
LINE 597
EXPRESSION (req_o & ack_i & descramble_i)
--1-- --2-- ------3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T8,T39,T68 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 598
EXPRESSION (calc_req_o & calc_ack_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T4,T59 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 614
EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
-------1------- -----2---- ------3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T7,T32,T30 |
1 | 1 | 0 | Covered | T68,T69,T96 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 624
EXPRESSION
Number Term
1 forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 624
SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 628
EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 628
SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 636
EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
---1--- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 636
SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
--------1-------- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 654
EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 654
SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 654
SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
--------1-------- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 659
EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
------1----- -----2---- --------------------------3-------------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T38,T56,T57 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 659
SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
------1------ -----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 659
SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
-----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 664
EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
----1--- ------2----- ------------3------------ ------4-----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 664
EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
----1--- ------2----- ------------3------------ ------4-----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 664
EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
----1--- ------2----- ------------3------------ ------4-----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 664
EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
----1--- ------2----- ------------3------------ ------4-----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 677
EXPRESSION (buf_rsp_err | read_buf[i].err)
-----1----- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 683
EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 736
EXPRESSION (data_err_o ? inv_data_integ : data_out_intg)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T104,T146,T34 |
LINE 747
EXPRESSION (((|buf_rsp_match)) ? buf_addr_xor_muxed : fifo_addr_xor_muxed)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 775
EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 775
SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
---------------------------------------------1---------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 787
EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
-------1------- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 790
EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
--------------------------------------1------------------------------------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T104,T146,T34 |
LINE 790
SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
------1----- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T104,T146,T34 |
LINE 790
SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
----1---- ----2--- -----------------3----------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Not Covered | |
0 | 1 | 0 | Covered | T1,T2,T3 |
1 | 0 | 0 | Covered | T34,T23,T48 |
LINE 790
SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
---------1-------- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Not Covered | |
LINE 794
EXPRESSION (data_valid_o & intg_err)
------1----- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T104,T146,T34 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
| Line No. | Total | Covered | Percent |
Branches |
|
43 |
43 |
100.00 |
TERNARY |
186 |
2 |
2 |
100.00 |
TERNARY |
232 |
2 |
2 |
100.00 |
TERNARY |
302 |
2 |
2 |
100.00 |
TERNARY |
451 |
2 |
2 |
100.00 |
TERNARY |
513 |
3 |
3 |
100.00 |
TERNARY |
624 |
3 |
3 |
100.00 |
TERNARY |
628 |
3 |
3 |
100.00 |
TERNARY |
654 |
3 |
3 |
100.00 |
TERNARY |
683 |
2 |
2 |
100.00 |
TERNARY |
736 |
2 |
2 |
100.00 |
TERNARY |
747 |
2 |
2 |
100.00 |
TERNARY |
775 |
2 |
2 |
100.00 |
TERNARY |
167 |
2 |
2 |
100.00 |
IF |
257 |
3 |
3 |
100.00 |
IF |
360 |
4 |
4 |
100.00 |
IF |
600 |
4 |
4 |
100.00 |
IF |
674 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 186 ((|buf_invalid_alloc)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 232 (no_match) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 302 ((|alloc)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 451 ((data_err | ecc_single_err_o)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T32,T33,T34 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 513 (hint_descram) ?
-2-: 513 (hint_dropmsk) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T68,T69,T96 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 624 (forward) ?
-2-: 624 (hint_descram) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 628 (forward) ?
-2-: 628 ((~hint_forward)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 654 (forward) ?
-2-: 654 (((~hint_forward) & fifo_data_ready)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 683 ((|buf_rsp_match)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 736 (data_err_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T104,T146,T34 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 747 ((|buf_rsp_match)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 775 (rsp_fifo_rdata.intg_ecc_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (((|buf_invalid_alloc) | all_buf_dependency)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 257 if ((!rst_ni))
-2-: 259 if (idle_o)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 360 if ((!rst_ni))
-2-: 364 if (rd_start)
-3-: 371 if (rd_done)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 600 if ((!rst_ni))
-2-: 602 if (calc_req_start)
-3-: 604 if (calc_req_done)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 674 if (buf_rsp_match[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
Assertion Details
BufferMatchEcc_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
958776 |
0 |
0 |
T1 |
2491 |
10 |
0 |
0 |
T2 |
188370 |
78 |
0 |
0 |
T3 |
1086 |
11 |
0 |
0 |
T4 |
419711 |
2808 |
0 |
0 |
T5 |
136725 |
1325 |
0 |
0 |
T6 |
0 |
5843 |
0 |
0 |
T7 |
0 |
2023 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T21 |
0 |
28 |
0 |
0 |
T43 |
0 |
3088 |
0 |
0 |
T52 |
0 |
220 |
0 |
0 |
ExclusiveOps_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
374949971 |
0 |
0 |
T1 |
2491 |
2403 |
0 |
0 |
T2 |
188370 |
188368 |
0 |
0 |
T3 |
1086 |
1035 |
0 |
0 |
T4 |
419711 |
402464 |
0 |
0 |
T5 |
136725 |
136716 |
0 |
0 |
T12 |
3359 |
2662 |
0 |
0 |
T13 |
4097 |
3394 |
0 |
0 |
T17 |
1302 |
1219 |
0 |
0 |
T18 |
3485 |
3398 |
0 |
0 |
T19 |
4533 |
4447 |
0 |
0 |
ExclusiveProgHazard_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
374949971 |
0 |
0 |
T1 |
2491 |
2403 |
0 |
0 |
T2 |
188370 |
188368 |
0 |
0 |
T3 |
1086 |
1035 |
0 |
0 |
T4 |
419711 |
402464 |
0 |
0 |
T5 |
136725 |
136716 |
0 |
0 |
T12 |
3359 |
2662 |
0 |
0 |
T13 |
4097 |
3394 |
0 |
0 |
T17 |
1302 |
1219 |
0 |
0 |
T18 |
3485 |
3398 |
0 |
0 |
T19 |
4533 |
4447 |
0 |
0 |
ExclusiveState_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
374949971 |
0 |
0 |
T1 |
2491 |
2403 |
0 |
0 |
T2 |
188370 |
188368 |
0 |
0 |
T3 |
1086 |
1035 |
0 |
0 |
T4 |
419711 |
402464 |
0 |
0 |
T5 |
136725 |
136716 |
0 |
0 |
T12 |
3359 |
2662 |
0 |
0 |
T13 |
4097 |
3394 |
0 |
0 |
T17 |
1302 |
1219 |
0 |
0 |
T18 |
3485 |
3398 |
0 |
0 |
T19 |
4533 |
4447 |
0 |
0 |
ForwardCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
1966514 |
0 |
0 |
T1 |
2491 |
10 |
0 |
0 |
T2 |
188370 |
88 |
0 |
0 |
T3 |
1086 |
11 |
0 |
0 |
T4 |
419711 |
0 |
0 |
0 |
T5 |
136725 |
1336 |
0 |
0 |
T6 |
0 |
14419 |
0 |
0 |
T7 |
0 |
816 |
0 |
0 |
T8 |
0 |
4751 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T32 |
0 |
59 |
0 |
0 |
T52 |
0 |
251 |
0 |
0 |
T53 |
0 |
8031 |
0 |
0 |
IdleCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
51310258 |
0 |
0 |
T1 |
2491 |
158 |
0 |
0 |
T2 |
188370 |
530814 |
0 |
0 |
T3 |
1086 |
161 |
0 |
0 |
T4 |
419711 |
42584 |
0 |
0 |
T5 |
136725 |
4125 |
0 |
0 |
T12 |
3359 |
412 |
0 |
0 |
T13 |
4097 |
800 |
0 |
0 |
T17 |
1302 |
128 |
0 |
0 |
T18 |
3485 |
128 |
0 |
0 |
T19 |
4533 |
128 |
0 |
0 |
MaxBufs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1038 |
1038 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OneHotAlloc_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
374949971 |
0 |
0 |
T1 |
2491 |
2403 |
0 |
0 |
T2 |
188370 |
188368 |
0 |
0 |
T3 |
1086 |
1035 |
0 |
0 |
T4 |
419711 |
402464 |
0 |
0 |
T5 |
136725 |
136716 |
0 |
0 |
T12 |
3359 |
2662 |
0 |
0 |
T13 |
4097 |
3394 |
0 |
0 |
T17 |
1302 |
1219 |
0 |
0 |
T18 |
3485 |
3398 |
0 |
0 |
T19 |
4533 |
4447 |
0 |
0 |
OneHotMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
374949971 |
0 |
0 |
T1 |
2491 |
2403 |
0 |
0 |
T2 |
188370 |
188368 |
0 |
0 |
T3 |
1086 |
1035 |
0 |
0 |
T4 |
419711 |
402464 |
0 |
0 |
T5 |
136725 |
136716 |
0 |
0 |
T12 |
3359 |
2662 |
0 |
0 |
T13 |
4097 |
3394 |
0 |
0 |
T17 |
1302 |
1219 |
0 |
0 |
T18 |
3485 |
3398 |
0 |
0 |
T19 |
4533 |
4447 |
0 |
0 |
OneHotRspMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
374949971 |
0 |
0 |
T1 |
2491 |
2403 |
0 |
0 |
T2 |
188370 |
188368 |
0 |
0 |
T3 |
1086 |
1035 |
0 |
0 |
T4 |
419711 |
402464 |
0 |
0 |
T5 |
136725 |
136716 |
0 |
0 |
T12 |
3359 |
2662 |
0 |
0 |
T13 |
4097 |
3394 |
0 |
0 |
T17 |
1302 |
1219 |
0 |
0 |
T18 |
3485 |
3398 |
0 |
0 |
T19 |
4533 |
4447 |
0 |
0 |
OneHotUpdate_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
374949971 |
0 |
0 |
T1 |
2491 |
2403 |
0 |
0 |
T2 |
188370 |
188368 |
0 |
0 |
T3 |
1086 |
1035 |
0 |
0 |
T4 |
419711 |
402464 |
0 |
0 |
T5 |
136725 |
136716 |
0 |
0 |
T12 |
3359 |
2662 |
0 |
0 |
T13 |
4097 |
3394 |
0 |
0 |
T17 |
1302 |
1219 |
0 |
0 |
T18 |
3485 |
3398 |
0 |
0 |
T19 |
4533 |
4447 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
| Line No. | Total | Covered | Percent |
TOTAL | | 133 | 133 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 152 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 186 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 229 | 1 | 1 | 100.00 |
CONT_ASSIGN | 232 | 1 | 1 | 100.00 |
ALWAYS | 257 | 4 | 4 | 100.00 |
CONT_ASSIGN | 291 | 1 | 1 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 302 | 1 | 1 | 100.00 |
CONT_ASSIGN | 305 | 1 | 1 | 100.00 |
CONT_ASSIGN | 308 | 1 | 1 | 100.00 |
CONT_ASSIGN | 326 | 1 | 1 | 100.00 |
CONT_ASSIGN | 331 | 1 | 1 | 100.00 |
ALWAYS | 360 | 12 | 12 | 100.00 |
CONT_ASSIGN | 377 | 1 | 1 | 100.00 |
CONT_ASSIGN | 382 | 1 | 1 | 100.00 |
CONT_ASSIGN | 393 | 1 | 1 | 100.00 |
CONT_ASSIGN | 399 | 1 | 1 | 100.00 |
CONT_ASSIGN | 407 | 1 | 1 | 100.00 |
CONT_ASSIGN | 428 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 442 | 1 | 1 | 100.00 |
CONT_ASSIGN | 445 | 1 | 1 | 100.00 |
CONT_ASSIGN | 451 | 1 | 1 | 100.00 |
CONT_ASSIGN | 456 | 1 | 1 | 100.00 |
CONT_ASSIGN | 459 | 1 | 1 | 100.00 |
CONT_ASSIGN | 491 | 1 | 1 | 100.00 |
CONT_ASSIGN | 494 | 1 | 1 | 100.00 |
CONT_ASSIGN | 497 | 1 | 1 | 100.00 |
CONT_ASSIGN | 501 | 1 | 1 | 100.00 |
CONT_ASSIGN | 503 | 1 | 1 | 100.00 |
CONT_ASSIGN | 504 | 1 | 1 | 100.00 |
CONT_ASSIGN | 505 | 1 | 1 | 100.00 |
CONT_ASSIGN | 513 | 1 | 1 | 100.00 |
CONT_ASSIGN | 521 | 1 | 1 | 100.00 |
CONT_ASSIGN | 523 | 1 | 1 | 100.00 |
CONT_ASSIGN | 597 | 1 | 1 | 100.00 |
CONT_ASSIGN | 598 | 1 | 1 | 100.00 |
ALWAYS | 600 | 6 | 6 | 100.00 |
CONT_ASSIGN | 610 | 1 | 1 | 100.00 |
CONT_ASSIGN | 614 | 1 | 1 | 100.00 |
CONT_ASSIGN | 617 | 1 | 1 | 100.00 |
CONT_ASSIGN | 624 | 1 | 1 | 100.00 |
CONT_ASSIGN | 628 | 1 | 1 | 100.00 |
CONT_ASSIGN | 636 | 1 | 1 | 100.00 |
CONT_ASSIGN | 654 | 1 | 1 | 100.00 |
CONT_ASSIGN | 659 | 1 | 1 | 100.00 |
CONT_ASSIGN | 664 | 1 | 1 | 100.00 |
CONT_ASSIGN | 664 | 1 | 1 | 100.00 |
CONT_ASSIGN | 664 | 1 | 1 | 100.00 |
CONT_ASSIGN | 664 | 1 | 1 | 100.00 |
ALWAYS | 670 | 8 | 8 | 100.00 |
CONT_ASSIGN | 683 | 1 | 1 | 100.00 |
CONT_ASSIGN | 704 | 1 | 1 | 100.00 |
CONT_ASSIGN | 724 | 1 | 1 | 100.00 |
CONT_ASSIGN | 736 | 1 | 1 | 100.00 |
CONT_ASSIGN | 738 | 1 | 1 | 100.00 |
CONT_ASSIGN | 744 | 1 | 1 | 100.00 |
CONT_ASSIGN | 745 | 1 | 1 | 100.00 |
CONT_ASSIGN | 747 | 1 | 1 | 100.00 |
CONT_ASSIGN | 751 | 1 | 1 | 100.00 |
CONT_ASSIGN | 762 | 1 | 1 | 100.00 |
CONT_ASSIGN | 775 | 1 | 1 | 100.00 |
CONT_ASSIGN | 787 | 1 | 1 | 100.00 |
CONT_ASSIGN | 790 | 1 | 1 | 100.00 |
CONT_ASSIGN | 794 | 1 | 1 | 100.00 |
CONT_ASSIGN | 797 | 1 | 1 | 100.00 |
CONT_ASSIGN | 800 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
137 |
1 |
1 |
140 |
4 |
4 |
141 |
4 |
4 |
146 |
4 |
4 |
152 |
1 |
1 |
154 |
3 |
3 |
186 |
1 |
1 |
193 |
4 |
4 |
194 |
4 |
4 |
196 |
4 |
4 |
212 |
4 |
4 |
218 |
4 |
4 |
222 |
4 |
4 |
229 |
1 |
1 |
232 |
1 |
1 |
257 |
1 |
1 |
258 |
1 |
1 |
259 |
1 |
1 |
260 |
1 |
1 |
|
|
|
MISSING_ELSE |
291 |
1 |
1 |
292 |
1 |
1 |
302 |
1 |
1 |
305 |
1 |
1 |
308 |
1 |
1 |
326 |
1 |
1 |
331 |
1 |
1 |
360 |
1 |
1 |
361 |
1 |
1 |
362 |
1 |
1 |
363 |
1 |
1 |
364 |
1 |
1 |
365 |
1 |
1 |
366 |
1 |
1 |
367 |
1 |
1 |
368 |
1 |
1 |
369 |
1 |
1 |
371 |
1 |
1 |
372 |
1 |
1 |
|
|
|
MISSING_ELSE |
377 |
1 |
1 |
382 |
1 |
1 |
393 |
1 |
1 |
399 |
1 |
1 |
407 |
1 |
1 |
428 |
1 |
1 |
432 |
1 |
1 |
442 |
1 |
1 |
445 |
1 |
1 |
451 |
1 |
1 |
456 |
1 |
1 |
459 |
1 |
1 |
491 |
1 |
1 |
494 |
1 |
1 |
497 |
1 |
1 |
501 |
1 |
1 |
503 |
1 |
1 |
504 |
1 |
1 |
505 |
1 |
1 |
513 |
1 |
1 |
521 |
1 |
1 |
523 |
1 |
1 |
597 |
1 |
1 |
598 |
1 |
1 |
600 |
1 |
1 |
601 |
1 |
1 |
602 |
1 |
1 |
603 |
1 |
1 |
604 |
1 |
1 |
605 |
1 |
1 |
|
|
|
MISSING_ELSE |
610 |
1 |
1 |
614 |
1 |
1 |
617 |
1 |
1 |
624 |
1 |
1 |
628 |
1 |
1 |
636 |
1 |
1 |
654 |
1 |
1 |
659 |
1 |
1 |
664 |
4 |
4 |
670 |
1 |
1 |
671 |
1 |
1 |
672 |
1 |
1 |
673 |
1 |
1 |
674 |
1 |
1 |
675 |
1 |
1 |
676 |
1 |
1 |
677 |
1 |
1 |
|
|
|
MISSING_ELSE |
683 |
1 |
1 |
704 |
1 |
1 |
724 |
1 |
1 |
736 |
1 |
1 |
738 |
1 |
1 |
744 |
1 |
1 |
745 |
1 |
1 |
747 |
1 |
1 |
751 |
1 |
1 |
762 |
1 |
1 |
775 |
1 |
1 |
787 |
1 |
1 |
790 |
1 |
1 |
794 |
1 |
1 |
797 |
1 |
1 |
800 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
| Total | Covered | Percent |
Conditions | 458 | 416 | 90.83 |
Logical | 458 | 416 | 90.83 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
| Line No. | Total | Covered | Percent |
Branches |
|
43 |
43 |
100.00 |
TERNARY |
186 |
2 |
2 |
100.00 |
TERNARY |
232 |
2 |
2 |
100.00 |
TERNARY |
302 |
2 |
2 |
100.00 |
TERNARY |
451 |
2 |
2 |
100.00 |
TERNARY |
513 |
3 |
3 |
100.00 |
TERNARY |
624 |
3 |
3 |
100.00 |
TERNARY |
628 |
3 |
3 |
100.00 |
TERNARY |
654 |
3 |
3 |
100.00 |
TERNARY |
683 |
2 |
2 |
100.00 |
TERNARY |
736 |
2 |
2 |
100.00 |
TERNARY |
747 |
2 |
2 |
100.00 |
TERNARY |
775 |
2 |
2 |
100.00 |
TERNARY |
167 |
2 |
2 |
100.00 |
IF |
257 |
3 |
3 |
100.00 |
IF |
360 |
4 |
4 |
100.00 |
IF |
600 |
4 |
4 |
100.00 |
IF |
674 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 186 ((|buf_invalid_alloc)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T5,T6 |
LineNo. Expression
-1-: 232 (no_match) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T5,T6 |
LineNo. Expression
-1-: 302 ((|alloc)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T5,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 451 ((data_err | ecc_single_err_o)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T21,T32,T33 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 513 (hint_descram) ?
-2-: 513 (hint_dropmsk) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T2,T7,T21 |
0 |
1 |
Covered |
T68,T69,T96 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 624 (forward) ?
-2-: 624 (hint_descram) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T2,T5,T6 |
0 |
1 |
Covered |
T2,T7,T21 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 628 (forward) ?
-2-: 628 ((~hint_forward)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T2,T5,T6 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T2,T5,T6 |
LineNo. Expression
-1-: 654 (forward) ?
-2-: 654 (((~hint_forward) & fifo_data_ready)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T2,T5,T6 |
0 |
1 |
Covered |
T2,T7,T21 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 683 ((|buf_rsp_match)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T5,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 736 (data_err_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T21,T34,T24 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 747 ((|buf_rsp_match)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T5,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 775 (rsp_fifo_rdata.intg_ecc_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T7,T21 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 167 (((|buf_invalid_alloc) | all_buf_dependency)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T5,T6 |
LineNo. Expression
-1-: 257 if ((!rst_ni))
-2-: 259 if (idle_o)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T2,T5,T6 |
LineNo. Expression
-1-: 360 if ((!rst_ni))
-2-: 364 if (rd_start)
-3-: 371 if (rd_done)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T2,T5,T6 |
0 |
0 |
1 |
Covered |
T2,T5,T6 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 600 if ((!rst_ni))
-2-: 602 if (calc_req_start)
-3-: 604 if (calc_req_done)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T2,T7,T21 |
0 |
0 |
1 |
Covered |
T2,T7,T21 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 674 if (buf_rsp_match[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T5,T6 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
Assertion Details
BufferMatchEcc_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
642183 |
0 |
0 |
T2 |
188370 |
39 |
0 |
0 |
T3 |
1086 |
0 |
0 |
0 |
T4 |
419711 |
0 |
0 |
0 |
T5 |
136725 |
559 |
0 |
0 |
T6 |
0 |
7510 |
0 |
0 |
T7 |
0 |
19 |
0 |
0 |
T8 |
0 |
376 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T21 |
0 |
1 |
0 |
0 |
T32 |
0 |
78 |
0 |
0 |
T52 |
0 |
186 |
0 |
0 |
T53 |
0 |
1 |
0 |
0 |
T54 |
0 |
62 |
0 |
0 |
T55 |
1247 |
0 |
0 |
0 |
ExclusiveOps_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
374949971 |
0 |
0 |
T1 |
2491 |
2403 |
0 |
0 |
T2 |
188370 |
188368 |
0 |
0 |
T3 |
1086 |
1035 |
0 |
0 |
T4 |
419711 |
402464 |
0 |
0 |
T5 |
136725 |
136716 |
0 |
0 |
T12 |
3359 |
2662 |
0 |
0 |
T13 |
4097 |
3394 |
0 |
0 |
T17 |
1302 |
1219 |
0 |
0 |
T18 |
3485 |
3398 |
0 |
0 |
T19 |
4533 |
4447 |
0 |
0 |
ExclusiveProgHazard_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
374949971 |
0 |
0 |
T1 |
2491 |
2403 |
0 |
0 |
T2 |
188370 |
188368 |
0 |
0 |
T3 |
1086 |
1035 |
0 |
0 |
T4 |
419711 |
402464 |
0 |
0 |
T5 |
136725 |
136716 |
0 |
0 |
T12 |
3359 |
2662 |
0 |
0 |
T13 |
4097 |
3394 |
0 |
0 |
T17 |
1302 |
1219 |
0 |
0 |
T18 |
3485 |
3398 |
0 |
0 |
T19 |
4533 |
4447 |
0 |
0 |
ExclusiveState_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
374949971 |
0 |
0 |
T1 |
2491 |
2403 |
0 |
0 |
T2 |
188370 |
188368 |
0 |
0 |
T3 |
1086 |
1035 |
0 |
0 |
T4 |
419711 |
402464 |
0 |
0 |
T5 |
136725 |
136716 |
0 |
0 |
T12 |
3359 |
2662 |
0 |
0 |
T13 |
4097 |
3394 |
0 |
0 |
T17 |
1302 |
1219 |
0 |
0 |
T18 |
3485 |
3398 |
0 |
0 |
T19 |
4533 |
4447 |
0 |
0 |
ForwardCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
1655854 |
0 |
0 |
T2 |
188370 |
47 |
0 |
0 |
T3 |
1086 |
0 |
0 |
0 |
T4 |
419711 |
0 |
0 |
0 |
T5 |
136725 |
565 |
0 |
0 |
T6 |
0 |
17106 |
0 |
0 |
T8 |
0 |
9345 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T30 |
0 |
12712 |
0 |
0 |
T31 |
0 |
235 |
0 |
0 |
T32 |
0 |
29 |
0 |
0 |
T52 |
0 |
215 |
0 |
0 |
T53 |
0 |
8087 |
0 |
0 |
T54 |
0 |
67 |
0 |
0 |
T55 |
1247 |
0 |
0 |
0 |
IdleCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
48430977 |
0 |
0 |
T2 |
188370 |
524421 |
0 |
0 |
T3 |
1086 |
0 |
0 |
0 |
T4 |
419711 |
0 |
0 |
0 |
T5 |
136725 |
1689 |
0 |
0 |
T6 |
0 |
879916 |
0 |
0 |
T7 |
0 |
30420 |
0 |
0 |
T8 |
0 |
24577 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T21 |
0 |
21 |
0 |
0 |
T32 |
0 |
369 |
0 |
0 |
T52 |
0 |
616 |
0 |
0 |
T53 |
0 |
412438 |
0 |
0 |
T54 |
0 |
196 |
0 |
0 |
T55 |
1247 |
0 |
0 |
0 |
MaxBufs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1038 |
1038 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OneHotAlloc_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
374949971 |
0 |
0 |
T1 |
2491 |
2403 |
0 |
0 |
T2 |
188370 |
188368 |
0 |
0 |
T3 |
1086 |
1035 |
0 |
0 |
T4 |
419711 |
402464 |
0 |
0 |
T5 |
136725 |
136716 |
0 |
0 |
T12 |
3359 |
2662 |
0 |
0 |
T13 |
4097 |
3394 |
0 |
0 |
T17 |
1302 |
1219 |
0 |
0 |
T18 |
3485 |
3398 |
0 |
0 |
T19 |
4533 |
4447 |
0 |
0 |
OneHotMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
374949971 |
0 |
0 |
T1 |
2491 |
2403 |
0 |
0 |
T2 |
188370 |
188368 |
0 |
0 |
T3 |
1086 |
1035 |
0 |
0 |
T4 |
419711 |
402464 |
0 |
0 |
T5 |
136725 |
136716 |
0 |
0 |
T12 |
3359 |
2662 |
0 |
0 |
T13 |
4097 |
3394 |
0 |
0 |
T17 |
1302 |
1219 |
0 |
0 |
T18 |
3485 |
3398 |
0 |
0 |
T19 |
4533 |
4447 |
0 |
0 |
OneHotRspMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
374949971 |
0 |
0 |
T1 |
2491 |
2403 |
0 |
0 |
T2 |
188370 |
188368 |
0 |
0 |
T3 |
1086 |
1035 |
0 |
0 |
T4 |
419711 |
402464 |
0 |
0 |
T5 |
136725 |
136716 |
0 |
0 |
T12 |
3359 |
2662 |
0 |
0 |
T13 |
4097 |
3394 |
0 |
0 |
T17 |
1302 |
1219 |
0 |
0 |
T18 |
3485 |
3398 |
0 |
0 |
T19 |
4533 |
4447 |
0 |
0 |
OneHotUpdate_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
374949971 |
0 |
0 |
T1 |
2491 |
2403 |
0 |
0 |
T2 |
188370 |
188368 |
0 |
0 |
T3 |
1086 |
1035 |
0 |
0 |
T4 |
419711 |
402464 |
0 |
0 |
T5 |
136725 |
136716 |
0 |
0 |
T12 |
3359 |
2662 |
0 |
0 |
T13 |
4097 |
3394 |
0 |
0 |
T17 |
1302 |
1219 |
0 |
0 |
T18 |
3485 |
3398 |
0 |
0 |
T19 |
4533 |
4447 |
0 |
0 |