Line Coverage for Module :
flash_phy_rd_buffers
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Module :
flash_phy_rd_buffers
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T22,T29 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T4 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
flash_phy_rd_buffers
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T2,T22,T29 |
0 |
0 |
1 |
- |
- |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
flash_phy_rd_buffers
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
5028241 |
0 |
0 |
T1 |
9964 |
10 |
0 |
0 |
T2 |
1506960 |
135 |
0 |
0 |
T3 |
8688 |
11 |
0 |
0 |
T4 |
3357688 |
2616 |
0 |
0 |
T5 |
1093800 |
1901 |
0 |
0 |
T6 |
0 |
31525 |
0 |
0 |
T7 |
0 |
19116 |
0 |
0 |
T8 |
0 |
9345 |
0 |
0 |
T12 |
26872 |
0 |
0 |
0 |
T13 |
32776 |
0 |
0 |
0 |
T17 |
10416 |
0 |
0 |
0 |
T18 |
27880 |
0 |
0 |
0 |
T19 |
36264 |
0 |
0 |
0 |
T21 |
0 |
31 |
0 |
0 |
T32 |
0 |
88 |
0 |
0 |
T43 |
0 |
2792 |
0 |
0 |
T52 |
0 |
466 |
0 |
0 |
T53 |
0 |
8087 |
0 |
0 |
T54 |
0 |
67 |
0 |
0 |
T55 |
4988 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
5028232 |
0 |
0 |
T1 |
9964 |
10 |
0 |
0 |
T2 |
1506960 |
135 |
0 |
0 |
T3 |
8688 |
11 |
0 |
0 |
T4 |
3357688 |
2616 |
0 |
0 |
T5 |
1093800 |
1901 |
0 |
0 |
T6 |
0 |
31525 |
0 |
0 |
T7 |
0 |
19116 |
0 |
0 |
T8 |
0 |
9345 |
0 |
0 |
T12 |
26872 |
0 |
0 |
0 |
T13 |
32776 |
0 |
0 |
0 |
T17 |
10416 |
0 |
0 |
0 |
T18 |
27880 |
0 |
0 |
0 |
T19 |
36264 |
0 |
0 |
0 |
T21 |
0 |
31 |
0 |
0 |
T32 |
0 |
88 |
0 |
0 |
T43 |
0 |
2792 |
0 |
0 |
T52 |
0 |
466 |
0 |
0 |
T53 |
0 |
8087 |
0 |
0 |
T54 |
0 |
67 |
0 |
0 |
T55 |
4988 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T22,T29 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T5 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T2,T22,T29 |
0 |
0 |
1 |
- |
- |
Covered |
T1,T4,T5 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
667664 |
0 |
0 |
T1 |
2491 |
3 |
0 |
0 |
T2 |
188370 |
22 |
0 |
0 |
T3 |
1086 |
3 |
0 |
0 |
T4 |
419711 |
654 |
0 |
0 |
T5 |
136725 |
334 |
0 |
0 |
T6 |
0 |
3598 |
0 |
0 |
T7 |
0 |
2654 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T21 |
0 |
7 |
0 |
0 |
T43 |
0 |
698 |
0 |
0 |
T52 |
0 |
63 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
667663 |
0 |
0 |
T1 |
2491 |
3 |
0 |
0 |
T2 |
188370 |
22 |
0 |
0 |
T3 |
1086 |
3 |
0 |
0 |
T4 |
419711 |
654 |
0 |
0 |
T5 |
136725 |
334 |
0 |
0 |
T6 |
0 |
3598 |
0 |
0 |
T7 |
0 |
2654 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T21 |
0 |
7 |
0 |
0 |
T43 |
0 |
698 |
0 |
0 |
T52 |
0 |
63 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T22,T29 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T5 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T2,T22,T29 |
0 |
0 |
1 |
- |
- |
Covered |
T1,T4,T5 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
667613 |
0 |
0 |
T1 |
2491 |
3 |
0 |
0 |
T2 |
188370 |
22 |
0 |
0 |
T3 |
1086 |
3 |
0 |
0 |
T4 |
419711 |
654 |
0 |
0 |
T5 |
136725 |
334 |
0 |
0 |
T6 |
0 |
3607 |
0 |
0 |
T7 |
0 |
2659 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T21 |
0 |
7 |
0 |
0 |
T43 |
0 |
698 |
0 |
0 |
T52 |
0 |
63 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
667612 |
0 |
0 |
T1 |
2491 |
3 |
0 |
0 |
T2 |
188370 |
22 |
0 |
0 |
T3 |
1086 |
3 |
0 |
0 |
T4 |
419711 |
654 |
0 |
0 |
T5 |
136725 |
334 |
0 |
0 |
T6 |
0 |
3607 |
0 |
0 |
T7 |
0 |
2659 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T21 |
0 |
7 |
0 |
0 |
T43 |
0 |
698 |
0 |
0 |
T52 |
0 |
63 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T22,T29 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T5 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T2,T22,T29 |
0 |
0 |
1 |
- |
- |
Covered |
T1,T4,T5 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
667414 |
0 |
0 |
T1 |
2491 |
2 |
0 |
0 |
T2 |
188370 |
22 |
0 |
0 |
T3 |
1086 |
3 |
0 |
0 |
T4 |
419711 |
654 |
0 |
0 |
T5 |
136725 |
334 |
0 |
0 |
T6 |
0 |
3608 |
0 |
0 |
T7 |
0 |
2675 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T21 |
0 |
6 |
0 |
0 |
T43 |
0 |
698 |
0 |
0 |
T52 |
0 |
63 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
667410 |
0 |
0 |
T1 |
2491 |
2 |
0 |
0 |
T2 |
188370 |
22 |
0 |
0 |
T3 |
1086 |
3 |
0 |
0 |
T4 |
419711 |
654 |
0 |
0 |
T5 |
136725 |
334 |
0 |
0 |
T6 |
0 |
3608 |
0 |
0 |
T7 |
0 |
2675 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T21 |
0 |
6 |
0 |
0 |
T43 |
0 |
698 |
0 |
0 |
T52 |
0 |
63 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T22,T29 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T4,T5 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T2,T22,T29 |
0 |
0 |
1 |
- |
- |
Covered |
T1,T4,T5 |
0 |
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
667085 |
0 |
0 |
T1 |
2491 |
2 |
0 |
0 |
T2 |
188370 |
22 |
0 |
0 |
T3 |
1086 |
2 |
0 |
0 |
T4 |
419711 |
654 |
0 |
0 |
T5 |
136725 |
334 |
0 |
0 |
T6 |
0 |
3606 |
0 |
0 |
T7 |
0 |
2652 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T21 |
0 |
6 |
0 |
0 |
T43 |
0 |
698 |
0 |
0 |
T52 |
0 |
62 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
667085 |
0 |
0 |
T1 |
2491 |
2 |
0 |
0 |
T2 |
188370 |
22 |
0 |
0 |
T3 |
1086 |
2 |
0 |
0 |
T4 |
419711 |
654 |
0 |
0 |
T5 |
136725 |
334 |
0 |
0 |
T6 |
0 |
3606 |
0 |
0 |
T7 |
0 |
2652 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T21 |
0 |
6 |
0 |
0 |
T43 |
0 |
698 |
0 |
0 |
T52 |
0 |
62 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T29,T73 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T6 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T5,T52 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T5,T6 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T5,T6 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T2,T29,T73 |
0 |
0 |
1 |
- |
- |
Covered |
T2,T5,T52 |
0 |
0 |
0 |
1 |
- |
Covered |
T2,T5,T6 |
0 |
0 |
0 |
0 |
1 |
Covered |
T2,T5,T6 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
589988 |
0 |
0 |
T2 |
188370 |
12 |
0 |
0 |
T3 |
1086 |
0 |
0 |
0 |
T4 |
419711 |
0 |
0 |
0 |
T5 |
136725 |
142 |
0 |
0 |
T6 |
0 |
4277 |
0 |
0 |
T7 |
0 |
2119 |
0 |
0 |
T8 |
0 |
2340 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
T52 |
0 |
54 |
0 |
0 |
T53 |
0 |
2022 |
0 |
0 |
T54 |
0 |
18 |
0 |
0 |
T55 |
1247 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
589987 |
0 |
0 |
T2 |
188370 |
12 |
0 |
0 |
T3 |
1086 |
0 |
0 |
0 |
T4 |
419711 |
0 |
0 |
0 |
T5 |
136725 |
142 |
0 |
0 |
T6 |
0 |
4277 |
0 |
0 |
T7 |
0 |
2119 |
0 |
0 |
T8 |
0 |
2340 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
T52 |
0 |
54 |
0 |
0 |
T53 |
0 |
2022 |
0 |
0 |
T54 |
0 |
18 |
0 |
0 |
T55 |
1247 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T29,T73 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T6 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T5,T52 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T5,T6 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T5,T6 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T2,T29,T73 |
0 |
0 |
1 |
- |
- |
Covered |
T2,T5,T52 |
0 |
0 |
0 |
1 |
- |
Covered |
T2,T5,T6 |
0 |
0 |
0 |
0 |
1 |
Covered |
T2,T5,T6 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
589677 |
0 |
0 |
T2 |
188370 |
12 |
0 |
0 |
T3 |
1086 |
0 |
0 |
0 |
T4 |
419711 |
0 |
0 |
0 |
T5 |
136725 |
141 |
0 |
0 |
T6 |
0 |
4276 |
0 |
0 |
T7 |
0 |
2119 |
0 |
0 |
T8 |
0 |
2338 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T21 |
0 |
1 |
0 |
0 |
T32 |
0 |
23 |
0 |
0 |
T52 |
0 |
54 |
0 |
0 |
T53 |
0 |
2021 |
0 |
0 |
T54 |
0 |
17 |
0 |
0 |
T55 |
1247 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
589677 |
0 |
0 |
T2 |
188370 |
12 |
0 |
0 |
T3 |
1086 |
0 |
0 |
0 |
T4 |
419711 |
0 |
0 |
0 |
T5 |
136725 |
141 |
0 |
0 |
T6 |
0 |
4276 |
0 |
0 |
T7 |
0 |
2119 |
0 |
0 |
T8 |
0 |
2338 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T21 |
0 |
1 |
0 |
0 |
T32 |
0 |
23 |
0 |
0 |
T52 |
0 |
54 |
0 |
0 |
T53 |
0 |
2021 |
0 |
0 |
T54 |
0 |
17 |
0 |
0 |
T55 |
1247 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T29,T73 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T6 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T5,T52 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T5,T6 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T5,T6 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T2,T29,T73 |
0 |
0 |
1 |
- |
- |
Covered |
T2,T5,T52 |
0 |
0 |
0 |
1 |
- |
Covered |
T2,T5,T6 |
0 |
0 |
0 |
0 |
1 |
Covered |
T2,T5,T6 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
589637 |
0 |
0 |
T2 |
188370 |
12 |
0 |
0 |
T3 |
1086 |
0 |
0 |
0 |
T4 |
419711 |
0 |
0 |
0 |
T5 |
136725 |
141 |
0 |
0 |
T6 |
0 |
4278 |
0 |
0 |
T7 |
0 |
2120 |
0 |
0 |
T8 |
0 |
2331 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T21 |
0 |
1 |
0 |
0 |
T32 |
0 |
22 |
0 |
0 |
T52 |
0 |
54 |
0 |
0 |
T53 |
0 |
2022 |
0 |
0 |
T54 |
0 |
17 |
0 |
0 |
T55 |
1247 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
589636 |
0 |
0 |
T2 |
188370 |
12 |
0 |
0 |
T3 |
1086 |
0 |
0 |
0 |
T4 |
419711 |
0 |
0 |
0 |
T5 |
136725 |
141 |
0 |
0 |
T6 |
0 |
4278 |
0 |
0 |
T7 |
0 |
2120 |
0 |
0 |
T8 |
0 |
2331 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T21 |
0 |
1 |
0 |
0 |
T32 |
0 |
22 |
0 |
0 |
T52 |
0 |
54 |
0 |
0 |
T53 |
0 |
2022 |
0 |
0 |
T54 |
0 |
17 |
0 |
0 |
T55 |
1247 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T29,T73 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T6 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T5,T52 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T5,T6 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T5,T6 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T2,T29,T73 |
0 |
0 |
1 |
- |
- |
Covered |
T2,T5,T52 |
0 |
0 |
0 |
1 |
- |
Covered |
T2,T5,T6 |
0 |
0 |
0 |
0 |
1 |
Covered |
T2,T5,T6 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
589163 |
0 |
0 |
T2 |
188370 |
11 |
0 |
0 |
T3 |
1086 |
0 |
0 |
0 |
T4 |
419711 |
0 |
0 |
0 |
T5 |
136725 |
141 |
0 |
0 |
T6 |
0 |
4275 |
0 |
0 |
T7 |
0 |
2118 |
0 |
0 |
T8 |
0 |
2336 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T21 |
0 |
1 |
0 |
0 |
T32 |
0 |
19 |
0 |
0 |
T52 |
0 |
53 |
0 |
0 |
T53 |
0 |
2022 |
0 |
0 |
T54 |
0 |
15 |
0 |
0 |
T55 |
1247 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
375778543 |
589162 |
0 |
0 |
T2 |
188370 |
11 |
0 |
0 |
T3 |
1086 |
0 |
0 |
0 |
T4 |
419711 |
0 |
0 |
0 |
T5 |
136725 |
141 |
0 |
0 |
T6 |
0 |
4275 |
0 |
0 |
T7 |
0 |
2118 |
0 |
0 |
T8 |
0 |
2336 |
0 |
0 |
T12 |
3359 |
0 |
0 |
0 |
T13 |
4097 |
0 |
0 |
0 |
T17 |
1302 |
0 |
0 |
0 |
T18 |
3485 |
0 |
0 |
0 |
T19 |
4533 |
0 |
0 |
0 |
T21 |
0 |
1 |
0 |
0 |
T32 |
0 |
19 |
0 |
0 |
T52 |
0 |
53 |
0 |
0 |
T53 |
0 |
2022 |
0 |
0 |
T54 |
0 |
15 |
0 |
0 |
T55 |
1247 |
0 |
0 |
0 |