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ASSERTPROPERTIESSEQUENCES
Total1020010
Category 01020010

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1020010
Severity 01020010

Summary for Assertions
NUMBERPERCENT
Total Number1020100.00
Uncovered292.84
Success99197.16
Failure00.00
Incomplete151.47
Without Attempts00.00

Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered330.00
All Matches770.00
First Matches770.00
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ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[220].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[221].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[222].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[223].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[224].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[225].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[226].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[237].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A 001257125700
tb.dut.tlul_assert_device.gen_device.aDataKnown_M 00405243118498526300
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A 00405242445578100
tb.dut.tlul_assert_device.gen_device.contigMask_M 004052431183087442200
tb.dut.tlul_assert_device.gen_device.dDataKnown_A 004050102253777505100
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A 00405242445444200
tb.dut.tlul_assert_device.gen_device.legalAParam_M 004052431183360308800
tb.dut.tlul_assert_device.gen_device.legalDParam_A 004052431184606134800
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M 004052431183360308800
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A 004052431184606134800
tb.dut.tlul_assert_device.gen_device.respOpcode_A 004052431184606134800
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A 004052431184606134800
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A 00405242445416900
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A 00405242445469300
tb.dut.tlul_assert_device.p_dbw.TlDbw_A 001262126200
tb.dut.u_ctrl_arb.u_state_regs.AssertConnected_A 001047104700
tb.dut.u_ctrl_arb.u_state_regs_A 0040259584040174230100
tb.dut.u_disable_buf.NumCopiesMustBeGreaterZero_A 001047104700
tb.dut.u_disable_buf.OutputsKnown_A 0040259581640174227700
tb.dut.u_disable_buf.gen_no_flops.OutputDelay_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.ArbCntMax_A 00402595816171972200
tb.dut.u_eflash.gen_flash_cores[0].u_core.CtrlPrio_A 00402595816171972200
tb.dut.u_eflash.gen_flash_cores[0].u_core.HostTransIdleChk_A 004025958162257351900
tb.dut.u_eflash.gen_flash_cores[0].u_core.NoRemainder_A 001047104700
tb.dut.u_eflash.gen_flash_cores[0].u_core.OneHotReqs_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.Pow2Multiple_A 001047104700
tb.dut.u_eflash.gen_flash_cores[0].u_core.RdTxnCheck_A 0040236292340150938400
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.OneDonePerTxn_A 00402595816124556600
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.PostPackRule_A 0040259581697400
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.PrePackRule_A 0040259581668500
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.WidthCheck_A 001047104700
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs.AssertConnected_A 001047104700
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.NumCopiesMustBeGreaterZero_A 001047104700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.OutputsKnown_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_no_flops.OutputDelay_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckHotOne_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A 001047104700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesReady_A 0040259581610573484200
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesValid_A 0040259581610573484200
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GrantKnown_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IdxKnown_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IndexIsCorrect_A 0040259581610573484200
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A 004025958164848299500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.Priority_A 0040259581611163086500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A 0040259581610573484200
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A 0040259581610573484200
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqImpliesValid_A 0040259581611163086500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ValidKnown_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckHotOne_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A 001047104700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesReady_A 0040259581610573479800
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesValid_A 0040259581610573479800
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GrantKnown_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IdxKnown_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IndexIsCorrect_A 0040259581610573479800
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A 004025958164848301600
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.Priority_A 0040259581611163080000
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A 0040259581610573479800
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A 0040259581610573479800
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqImpliesValid_A 0040259581611163080000
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ValidKnown_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.BufferMatchEcc_A 00402595816102262000
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveOps_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveProgHazard_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveState_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ForwardCheck_A 00402595816233368600
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.IdleCheck_A 004025958165506252700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.MaxBufs_A 001047104700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotAlloc_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotMatch_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotRspMatch_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotUpdate_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf.AllocCheck_A 0040259581673697200
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf.UpdateCheck_A 0040259581673697200
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf.AllocCheck_A 0040259581673690600
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf.UpdateCheck_A 0040259581673690600
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf.AllocCheck_A 0040259581673646800
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf.UpdateCheck_A 0040259581673646600
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf.AllocCheck_A 0040259581673621000
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf.UpdateCheck_A 0040259581673621000
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_addr_xor_storage.DataKnown_A 004025958165505034800
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_addr_xor_storage.DepthKnown_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_addr_xor_storage.RvalidKnown_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_addr_xor_storage.WreadyKnown_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_addr_xor_storage.gen_normal_fifo.depthShallNotExceedParamDepth 004025958165505034800
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.DataKnown_A 004025958161359567400
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.DepthKnown_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.RvalidKnown_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.WreadyKnown_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.gen_normal_fifo.depthShallNotExceedParamDepth 004025958161359567400
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferDecrUnderRun_A 00402595816396917400
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferDepRsp_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferIncrOverFlow_A 00402595816396917600
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.DepBufferRspOrder_A 00402595817922721500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.DataKnown_A 004023629231444896600
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.DepthKnown_A 0040236292340150938400
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.RvalidKnown_A 0040236292340150938400
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.WreadyKnown_A 0040236292340150938400
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.depthShallNotExceedParamDepth 004023629231444896600
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.DataKnown_A 004023629235505034800
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.DepthKnown_A 0040236292340150938400
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.RvalidKnown_A 0040236292340150938400
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.WreadyKnown_A 0040236292340150938400
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 004023629235505034800
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.CheckHotOne_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.CheckNGreaterZero_A 001047104700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GntImpliesReady_A 00402595816280117500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GntImpliesValid_A 00402595816280117500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GrantKnown_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.IdxKnown_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.IndexIsCorrect_A 00402595816280117500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.NoReadyValidNoGrant_A 0040259581628216390100
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReadyAndValidImplyGrant_A 00402595816280117500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqAndReadyImplyGrant_A 00402595816280117500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqImpliesValid_A 0040259581611417494200
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ValidKnown_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs.AssertConnected_A 001047104700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.DataKnown_A 00402362923281416700
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.DepthKnown_A 0040236292340150938400
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.RvalidKnown_A 0040236292340150938400
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.WreadyKnown_A 0040236292340150938400
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 00402362923281416700
tb.dut.u_eflash.gen_flash_cores[1].u_core.ArbCntMax_A 00402595816153772800
tb.dut.u_eflash.gen_flash_cores[1].u_core.CtrlPrio_A 00402595816153772800
tb.dut.u_eflash.gen_flash_cores[1].u_core.HostTransIdleChk_A 004025958162255920600
tb.dut.u_eflash.gen_flash_cores[1].u_core.NoRemainder_A 001047104700
tb.dut.u_eflash.gen_flash_cores[1].u_core.OneHotReqs_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[1].u_core.Pow2Multiple_A 001047104700
tb.dut.u_eflash.gen_flash_cores[1].u_core.RdTxnCheck_A 0040236292340150938400
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.OneDonePerTxn_A 00402595816120683000
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.PostPackRule_A 0040259581699600
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.PrePackRule_A 0040259581668700
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.WidthCheck_A 001047104700
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs.AssertConnected_A 001047104700
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.NumCopiesMustBeGreaterZero_A 001047104700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.OutputsKnown_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_no_flops.OutputDelay_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckHotOne_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A 001047104700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesReady_A 004025958169586586600
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesValid_A 004025958169586586600
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GrantKnown_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IdxKnown_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IndexIsCorrect_A 004025958169586586600
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A 004025958164466658000
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.Priority_A 0040259581610192441900
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A 004025958169586586600
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A 004025958169586586600
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqImpliesValid_A 0040259581610192441900
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ValidKnown_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckHotOne_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A 001047104700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesReady_A 004025958169586564700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesValid_A 004025958169586564700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GrantKnown_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IdxKnown_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IndexIsCorrect_A 004025958169586564700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A 004025958164466658200
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.Priority_A 0040259581610192419800
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A 004025958169586564700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A 004025958169586564700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqImpliesValid_A 0040259581610192419800
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ValidKnown_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.BufferMatchEcc_A 0040259581668111500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveOps_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveProgHazard_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveState_A 0040259581640174227700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ForwardCheck_A 00402595816186043400
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.IdleCheck_A 004025958165140357700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.MaxBufs_A 001047104700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotAlloc_A 0040259581640174227700
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