Go previous page

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	402805504	401926831	0	2727
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1044	1044	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.OutputsKnown_A	0	0	402805504	401960227	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A	0	0	402805504	401926831	0	2727
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1044	1044	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.OutputsKnown_A	0	0	402805504	401960227	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A	0	0	402805504	401926831	0	2727
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1044	1044	0	0
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.OutputsKnown_A	0	0	402805504	401960227	0	0
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	402805504	401926831	0	2727
tb.dut.u_sw_rd_fifo.DataKnown_A	0	0	409476704	51289558	0	0
tb.dut.u_sw_rd_fifo.DepthKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_sw_rd_fifo.RvalidKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_sw_rd_fifo.WreadyKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_sw_rd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	409476704	51289558	0	0
tb.dut.u_tl_adapter_eflash.AddrOutKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_tl_adapter_eflash.DataIntgOptions_A	0	0	1044	1044	0	0
tb.dut.u_tl_adapter_eflash.ReqOutKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_tl_adapter_eflash.SramDwHasByteGranularity_A	0	0	1044	1044	0	0
tb.dut.u_tl_adapter_eflash.SramDwIsMultipleOfTlulWidth_A	0	0	1044	1044	0	0
tb.dut.u_tl_adapter_eflash.TlOutKnownIfFifoKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_tl_adapter_eflash.TlOutValidKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_tl_adapter_eflash.WdataOutKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_tl_adapter_eflash.WeOutKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_tl_adapter_eflash.WmaskOutKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_tl_adapter_eflash.adapterNoReadOrWrite	0	0	1044	1044	0	0
tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.PayLoadWidthCheck	0	0	1044	1044	0	0
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.DataKnown_A	0	0	409476704	33018056	0	0
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.DepthKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.RvalidKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.WreadyKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	409476704	33018056	0	0
tb.dut.u_tl_adapter_eflash.rvalidHighReqFifoEmpty	0	0	409476704	4264217	0	0
tb.dut.u_tl_adapter_eflash.rvalidHighWhenRspFifoFull	0	0	409476704	4264217	0	0
tb.dut.u_tl_adapter_eflash.u_err.dataWidthOnly32_A	0	0	1044	1044	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.DataKnown_A	0	0	409476704	34429914	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.DepthKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.RvalidKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.WreadyKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	409476704	34429914	0	0
tb.dut.u_tl_adapter_eflash.u_rsp_gen.DataWidthCheck_A	0	0	1044	1044	0	0
tb.dut.u_tl_adapter_eflash.u_rsp_gen.PayLoadWidthCheck	0	0	1044	1044	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.DataKnown_A	0	0	409476704	5670807	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.DepthKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.RvalidKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.WreadyKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	409476704	5670807	0	0
tb.dut.u_tl_adapter_eflash.u_sram_byte.SramReadbackAndIntg	0	0	1044	1044	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DataKnown_A	0	0	409476704	33018056	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DepthKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.RvalidKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.WreadyKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	409476704	33018056	0	0
tb.dut.u_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1044	1044	0	0
tb.dut.u_tl_gate.u_err_en_sync.OutputsKnown_A	0	0	402805399	401960122	0	0
tb.dut.u_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A	0	0	402805399	401960122	0	0
tb.dut.u_tl_gate.u_state_regs.AssertConnected_A	0	0	1044	1044	0	0
tb.dut.u_tl_gate.u_state_regs_A	0	0	409476704	408631427	0	0
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A	0	0	1044	1044	0	0
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1044	1044	0	0
tb.dut.u_to_prog_fifo.AddrOutKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_prog_fifo.DataIntgOptions_A	0	0	1044	1044	0	0
tb.dut.u_to_prog_fifo.ReqOutKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_prog_fifo.SramDwHasByteGranularity_A	0	0	1044	1044	0	0
tb.dut.u_to_prog_fifo.SramDwIsMultipleOfTlulWidth_A	0	0	1044	1044	0	0
tb.dut.u_to_prog_fifo.TlOutKnownIfFifoKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_prog_fifo.TlOutValidKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_prog_fifo.WdataOutKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_prog_fifo.WeOutKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_prog_fifo.WmaskOutKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_prog_fifo.adapterNoReadOrWrite	0	0	1044	1044	0	0
tb.dut.u_to_prog_fifo.u_err.dataWidthOnly32_A	0	0	1044	1044	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.DataKnown_A	0	0	409476704	4223979	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.DepthKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.RvalidKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.WreadyKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	409476704	4223979	0	0
tb.dut.u_to_prog_fifo.u_rsp_gen.DataWidthCheck_A	0	0	1044	1044	0	0
tb.dut.u_to_prog_fifo.u_rsp_gen.PayLoadWidthCheck	0	0	1044	1044	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DepthKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.RvalidKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.WreadyKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_prog_fifo.u_sram_byte.SramReadbackAndIntg	0	0	1044	1044	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DepthKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.RvalidKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.WreadyKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_rd_fifo.AddrOutKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_rd_fifo.DataIntgOptions_A	0	0	1044	1044	0	0
tb.dut.u_to_rd_fifo.ReqOutKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_rd_fifo.SramDwHasByteGranularity_A	0	0	1044	1044	0	0
tb.dut.u_to_rd_fifo.SramDwIsMultipleOfTlulWidth_A	0	0	1044	1044	0	0
tb.dut.u_to_rd_fifo.TlOutKnownIfFifoKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_rd_fifo.TlOutValidKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_rd_fifo.WdataOutKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_rd_fifo.WeOutKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_rd_fifo.WmaskOutKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_rd_fifo.adapterNoReadOrWrite	0	0	1044	1044	0	0
tb.dut.u_to_rd_fifo.rvalidHighReqFifoEmpty	0	0	409476704	3382090	0	0
tb.dut.u_to_rd_fifo.rvalidHighWhenRspFifoFull	0	0	408747410	3375844	0	0
tb.dut.u_to_rd_fifo.u_err.dataWidthOnly32_A	0	0	1044	1044	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.DataKnown_A	0	0	409476704	5764932	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.DepthKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.RvalidKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.WreadyKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	409476704	5764932	0	0
tb.dut.u_to_rd_fifo.u_rsp_gen.DataWidthCheck_A	0	0	1044	1044	0	0
tb.dut.u_to_rd_fifo.u_rsp_gen.PayLoadWidthCheck	0	0	1044	1044	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.DataKnown_A	0	0	409233027	5751424	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.DepthKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.RvalidKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.WreadyKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	409476704	5771280	0	0
tb.dut.u_to_rd_fifo.u_sram_byte.SramReadbackAndIntg	0	0	1044	1044	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.DataKnown_A	0	0	409476704	3382090	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.DepthKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.RvalidKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.WreadyKnown_A	0	0	409476704	408631427	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	409476704	3382090	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	409476704	0	0	1039
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	409476704	0	0	1039
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A	0	0	402805399	401926741	0	2727
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	409476704	0	0	1039
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	409476704	0	0	1039
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	409476704	0	0	1039
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	409476704	0	0	1039
tb.dut.u_flash_hw_if.DisableChk_A	0	0	397516357	3380415	0	41
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A	0	0	402805504	401926831	0	2727
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A	0	0	402783538	401905015	0	2577
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A	0	0	402805504	401926831	0	2727
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	402805504	401926831	0	2727
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A	0	0	402805504	401926831	0	2727
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A	0	0	402805504	401926831	0	2727
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	402805504	401926831	0	2727

---

Detail Report for Cover Sequences

Cover Sequences Uncovered:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	412272490	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	412272490	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	412272490	0	0	0

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	412272490	83945	83945	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	412272490	16	16	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	412272490	12	12	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	412272490	9	9	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	412272490	17823	17823	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	412272490	440792	440792	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	412272490	15894037	15894037	1234

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	412272490	83945	83945	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	412272490	16	16	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	412272490	12	12	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	412272490	9	9	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	412272490	17823	17823	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	412272490	440792	440792	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	412272490	15894037	15894037	1234