Unified Coverage Report :: Module :: flash_phy_rd

Module : flash_phy_rd

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.09	100.00	92.36			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd	97.65	100.00	90.61			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd	97.93	100.00	91.70			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.65	100.00	90.61			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.02	97.64	93.24	100.00		99.37	94.83

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.55	100.00	84.91		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_rd.gen_bus_words_intg[0].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[0].u_prim_buf_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_prim_buf_intg	100.00	100.00
u_addr_xor_storage	96.53	100.00	86.11			100.00	100.00
u_bus_inv_data_intg	0.00	0.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_prim_buf_data_xor_out	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	97.44	100.00	87.18	100.00		100.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	92.50	92.31	97.69			100.00	80.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.93	100.00	91.70			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.10	97.64	93.64	100.00		99.37	94.83

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.87	100.00	94.34		100.00	100.00	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_rd.gen_bus_words_intg[0].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[0].u_prim_buf_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_prim_buf_intg	100.00	100.00
u_addr_xor_storage	96.53	100.00	86.11			100.00	100.00
u_bus_inv_data_intg	0.00	0.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_prim_buf_data_xor_out	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	97.44	100.00	87.18	100.00		100.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	92.50	92.31	97.69			100.00	80.00

Line Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
ALWAYS	257	4	4	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
ALWAYS	360	12	12	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	451	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	597	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
ALWAYS	600	6	6	100.00
CONT_ASSIGN	610	1	1	100.00
CONT_ASSIGN	614	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	624	1	1	100.00
CONT_ASSIGN	628	1	1	100.00
CONT_ASSIGN	636	1	1	100.00
CONT_ASSIGN	654	1	1	100.00
CONT_ASSIGN	659	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
ALWAYS	670	8	8	100.00
CONT_ASSIGN	683	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
CONT_ASSIGN	744	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	775	1	1	100.00
CONT_ASSIGN	787	1	1	100.00
CONT_ASSIGN	790	1	1	100.00
CONT_ASSIGN	794	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
CONT_ASSIGN	800	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
140	4	4
141	4	4
146	4	4
152	1	1
154	3	3
186	1	1
193	4	4
194	4	4
196	4	4
212	4	4
218	4	4
222	4	4
229	1	1
232	1	1
257	1	1
258	1	1
259	1	1
260	1	1
			MISSING_ELSE
291	1	1
292	1	1
302	1	1
305	1	1
308	1	1
326	1	1
331	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
371	1	1
372	1	1
			MISSING_ELSE
377	1	1
382	1	1
393	1	1
399	1	1
407	1	1
428	1	1
432	1	1
442	1	1
445	1	1
451	1	1
456	1	1
459	1	1
491	1	1
494	1	1
497	1	1
501	1	1
503	1	1
504	1	1
505	1	1
513	1	1
521	1	1
523	1	1
597	1	1
598	1	1
600	1	1
601	1	1
602	1	1
603	1	1
604	1	1
605	1	1
			MISSING_ELSE
610	1	1
614	1	1
617	1	1
624	1	1
628	1	1
636	1	1
654	1	1
659	1	1
664	4	4
670	1	1
671	1	1
672	1	1
673	1	1
674	1	1
675	1	1
676	1	1
677	1	1
			MISSING_ELSE
683	1	1
704	1	1
724	1	1
736	1	1
738	1	1
744	1	1
745	1	1
747	1	1
751	1	1
762	1	1
775	1	1
787	1	1
790	1	1
794	1	1
797	1	1
800	1	1

---

Cond Coverage for Module : flash_phy_rd

	Total	Covered	Percent
Conditions	458	423	92.36
Logical	458	423	92.36
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
140-790	92.63
790-794	80.00

---

Branch Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	186	2	2	100.00
TERNARY	232	2	2	100.00
TERNARY	302	2	2	100.00
TERNARY	451	2	2	100.00
TERNARY	513	3	3	100.00
TERNARY	624	3	3	100.00
TERNARY	628	3	3	100.00
TERNARY	654	3	3	100.00
TERNARY	683	2	2	100.00
TERNARY	736	2	2	100.00
TERNARY	747	2	2	100.00
TERNARY	775	2	2	100.00
TERNARY	167	2	2	100.00
IF	257	3	3	100.00
IF	360	4	4	100.00
IF	600	4	4	100.00
IF	674	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	186	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	232	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	302	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	451	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T26,T22,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	513	(hint_descram) ? 
-2-:	513	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T23,T41,T46
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	624	(forward) ? 
-2-:	624	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T23
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	628	(forward) ? 
-2-:	628	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T23
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T4,T23

	LineNo.	Expression
-1-:	654	(forward) ? 
-2-:	654	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T23
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	683	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	736	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T57,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	747	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	775	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	257	if ((!rst_ni))
-2-:	259	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	360	if ((!rst_ni))
-2-:	364	if (rd_start)
-3-:	371	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	600	if ((!rst_ni))
-2-:	602	if (calc_req_start)
-3-:	604	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	674	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	780041168	1641707	0	0
ExclusiveOps_A	780041168	778338280	0	0
ExclusiveProgHazard_A	780041168	778338280	0	0
ExclusiveState_A	780041168	778338280	0	0
ForwardCheck_A	780041168	3700893	0	0
IdleCheck_A	780041168	99713062	0	0
MaxBufs_A	2120	2120	0	0
OneHotAlloc_A	780041168	778338280	0	0
OneHotMatch_A	780041168	778338280	0	0
OneHotRspMatch_A	780041168	778338280	0	0
OneHotUpdate_A	780041168	778338280	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780041168	1641707	0	0
T1	420680	1218	0	0
T2	2452	0	0	0
T3	6694	0	0	0
T4	1160532	458	0	0
T5	403392	1544	0	0
T6	0	146	0	0
T11	2538	0	0	0
T14	7016	0	0	0
T18	1925460	0	0	0
T19	2358	0	0	0
T20	3082	0	0	0
T21	0	4	0	0
T22	0	76	0	0
T23	0	74	0	0
T24	0	134400	0	0
T26	0	35	0	0
T31	0	512	0	0
T40	0	1	0	0
T41	0	2678	0	0
T46	0	1490	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780041168	778338280	0	0
T1	420680	420558	0	0
T2	2452	2302	0	0
T3	6694	5306	0	0
T4	1160532	1160192	0	0
T5	403392	385742	0	0
T11	2538	2384	0	0
T14	7016	5688	0	0
T18	1925460	1925130	0	0
T19	2358	2184	0	0
T20	3082	2556	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780041168	778338280	0	0
T1	420680	420558	0	0
T2	2452	2302	0	0
T3	6694	5306	0	0
T4	1160532	1160192	0	0
T5	403392	385742	0	0
T11	2538	2384	0	0
T14	7016	5688	0	0
T18	1925460	1925130	0	0
T19	2358	2184	0	0
T20	3082	2556	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780041168	778338280	0	0
T1	420680	420558	0	0
T2	2452	2302	0	0
T3	6694	5306	0	0
T4	1160532	1160192	0	0
T5	403392	385742	0	0
T11	2538	2384	0	0
T14	7016	5688	0	0
T18	1925460	1925130	0	0
T19	2358	2184	0	0
T20	3082	2556	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780041168	3700893	0	0
T1	420680	1218	0	0
T2	2452	0	0	0
T3	6694	0	0	0
T4	1160532	17266	0	0
T5	403392	0	0	0
T6	0	172	0	0
T7	0	10	0	0
T11	2538	0	0	0
T14	7016	0	0	0
T18	1925460	0	0	0
T19	2358	0	0	0
T20	3082	0	0	0
T22	0	21	0	0
T23	0	39	0	0
T24	0	134400	0	0
T31	0	288	0	0
T35	0	7999	0	0
T40	0	7	0	0
T41	0	19997	0	0
T46	0	10813	0	0
T169	0	9268	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780041168	99713062	0	0
T1	420680	3782	0	0
T2	2452	128	0	0
T3	6694	572	0	0
T4	1160532	882820	0	0
T5	403392	22888	0	0
T6	0	293	0	0
T7	0	12	0	0
T11	2538	128	0	0
T14	7016	686	0	0
T18	1925460	192	0	0
T19	2358	128	0	0
T20	3082	268	0	0
T21	0	28	0	0
T22	0	60	0	0
T23	0	122	0	0
T26	0	29	0	0
T41	0	20016	0	0
T60	0	524288	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2120	2120	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T11	2	2	0	0
T14	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780041168	778338280	0	0
T1	420680	420558	0	0
T2	2452	2302	0	0
T3	6694	5306	0	0
T4	1160532	1160192	0	0
T5	403392	385742	0	0
T11	2538	2384	0	0
T14	7016	5688	0	0
T18	1925460	1925130	0	0
T19	2358	2184	0	0
T20	3082	2556	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780041168	778338280	0	0
T1	420680	420558	0	0
T2	2452	2302	0	0
T3	6694	5306	0	0
T4	1160532	1160192	0	0
T5	403392	385742	0	0
T11	2538	2384	0	0
T14	7016	5688	0	0
T18	1925460	1925130	0	0
T19	2358	2184	0	0
T20	3082	2556	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780041168	778338280	0	0
T1	420680	420558	0	0
T2	2452	2302	0	0
T3	6694	5306	0	0
T4	1160532	1160192	0	0
T5	403392	385742	0	0
T11	2538	2384	0	0
T14	7016	5688	0	0
T18	1925460	1925130	0	0
T19	2358	2184	0	0
T20	3082	2556	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	780041168	778338280	0	0
T1	420680	420558	0	0
T2	2452	2302	0	0
T3	6694	5306	0	0
T4	1160532	1160192	0	0
T5	403392	385742	0	0
T11	2538	2384	0	0
T14	7016	5688	0	0
T18	1925460	1925130	0	0
T19	2358	2184	0	0
T20	3082	2556	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
ALWAYS	257	4	4	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
ALWAYS	360	12	12	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	451	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	597	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
ALWAYS	600	6	6	100.00
CONT_ASSIGN	610	1	1	100.00
CONT_ASSIGN	614	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	624	1	1	100.00
CONT_ASSIGN	628	1	1	100.00
CONT_ASSIGN	636	1	1	100.00
CONT_ASSIGN	654	1	1	100.00
CONT_ASSIGN	659	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
ALWAYS	670	8	8	100.00
CONT_ASSIGN	683	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
CONT_ASSIGN	744	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	775	1	1	100.00
CONT_ASSIGN	787	1	1	100.00
CONT_ASSIGN	790	1	1	100.00
CONT_ASSIGN	794	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
CONT_ASSIGN	800	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
140	4	4
141	4	4
146	4	4
152	1	1
154	3	3
186	1	1
193	4	4
194	4	4
196	4	4
212	4	4
218	4	4
222	4	4
229	1	1
232	1	1
257	1	1
258	1	1
259	1	1
260	1	1
			MISSING_ELSE
291	1	1
292	1	1
302	1	1
305	1	1
308	1	1
326	1	1
331	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
371	1	1
372	1	1
			MISSING_ELSE
377	1	1
382	1	1
393	1	1
399	1	1
407	1	1
428	1	1
432	1	1
442	1	1
445	1	1
451	1	1
456	1	1
459	1	1
491	1	1
494	1	1
497	1	1
501	1	1
503	1	1
504	1	1
505	1	1
513	1	1
521	1	1
523	1	1
597	1	1
598	1	1
600	1	1
601	1	1
602	1	1
603	1	1
604	1	1
605	1	1
			MISSING_ELSE
610	1	1
614	1	1
617	1	1
624	1	1
628	1	1
636	1	1
654	1	1
659	1	1
664	4	4
670	1	1
671	1	1
672	1	1
673	1	1
674	1	1
675	1	1
676	1	1
677	1	1
			MISSING_ELSE
683	1	1
704	1	1
724	1	1
736	1	1
738	1	1
744	1	1
745	1	1
747	1	1
751	1	1
762	1	1
775	1	1
787	1	1
790	1	1
794	1	1
797	1	1
800	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Covered	Percent
Conditions	458	415	90.61
Logical	458	415	90.61
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
140-790	90.71
790-794	83.33

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	186	2	2	100.00
TERNARY	232	2	2	100.00
TERNARY	302	2	2	100.00
TERNARY	451	2	2	100.00
TERNARY	513	3	3	100.00
TERNARY	624	3	3	100.00
TERNARY	628	3	3	100.00
TERNARY	654	3	3	100.00
TERNARY	683	2	2	100.00
TERNARY	736	2	2	100.00
TERNARY	747	2	2	100.00
TERNARY	775	2	2	100.00
TERNARY	167	2	2	100.00
IF	257	3	3	100.00
IF	360	4	4	100.00
IF	600	4	4	100.00
IF	674	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	186	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T23

	LineNo.	Expression
-1-:	232	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T23

	LineNo.	Expression
-1-:	302	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T23
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	451	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T26,T22,T52
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	513	(hint_descram) ? 
-2-:	513	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T23,T21,T60
0	1	Covered	T41,T46,T169
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	624	(forward) ? 
-2-:	624	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T23
0	1	Covered	T23,T21,T60
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	628	(forward) ? 
-2-:	628	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T23
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T4,T23

	LineNo.	Expression
-1-:	654	(forward) ? 
-2-:	654	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T23
0	1	Covered	T23,T21,T60
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	683	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T23
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	736	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T26,T22,T52
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	747	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T23
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	775	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T23,T21,T41
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T23

	LineNo.	Expression
-1-:	257	if ((!rst_ni))
-2-:	259	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T4,T23

	LineNo.	Expression
-1-:	360	if ((!rst_ni))
-2-:	364	if (rd_start)
-3-:	371	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T23
0	0	1	Covered	T1,T4,T23
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	600	if ((!rst_ni))
-2-:	602	if (calc_req_start)
-3-:	604	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T23,T21,T41
0	0	1	Covered	T23,T21,T41
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	674	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T23
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	390020584	930931	0	0
ExclusiveOps_A	390020584	389169140	0	0
ExclusiveProgHazard_A	390020584	389169140	0	0
ExclusiveState_A	390020584	389169140	0	0
ForwardCheck_A	390020584	1962045	0	0
IdleCheck_A	390020584	48631044	0	0
MaxBufs_A	1060	1060	0	0
OneHotAlloc_A	390020584	389169140	0	0
OneHotMatch_A	390020584	389169140	0	0
OneHotRspMatch_A	390020584	389169140	0	0
OneHotUpdate_A	390020584	389169140	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	930931	0	0
T1	210340	684	0	0
T2	1226	0	0	0
T3	3347	0	0	0
T4	580266	3	0	0
T5	201696	0	0	0
T6	0	87	0	0
T11	1269	0	0	0
T14	3508	0	0	0
T18	962730	0	0	0
T19	1179	0	0	0
T20	1541	0	0	0
T21	0	4	0	0
T22	0	8	0	0
T23	0	26	0	0
T26	0	5	0	0
T40	0	1	0	0
T41	0	1296	0	0
T46	0	1490	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	1962045	0	0
T1	210340	684	0	0
T2	1226	0	0	0
T3	3347	0	0	0
T4	580266	7828	0	0
T5	201696	0	0	0
T6	0	103	0	0
T7	0	6	0	0
T11	1269	0	0	0
T14	3508	0	0	0
T18	962730	0	0	0
T19	1179	0	0	0
T20	1541	0	0	0
T23	0	10	0	0
T35	0	7999	0	0
T40	0	1	0	0
T41	0	9360	0	0
T46	0	10813	0	0
T169	0	9268	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	48631044	0	0
T1	210340	2052	0	0
T2	1226	0	0	0
T3	3347	0	0	0
T4	580266	399231	0	0
T5	201696	0	0	0
T6	0	293	0	0
T7	0	12	0	0
T11	1269	0	0	0
T14	3508	0	0	0
T18	962730	0	0	0
T19	1179	0	0	0
T20	1541	0	0	0
T21	0	28	0	0
T22	0	60	0	0
T23	0	122	0	0
T26	0	29	0	0
T41	0	20016	0	0
T60	0	524288	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
ALWAYS	257	4	4	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
ALWAYS	360	12	12	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	451	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	597	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
ALWAYS	600	6	6	100.00
CONT_ASSIGN	610	1	1	100.00
CONT_ASSIGN	614	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	624	1	1	100.00
CONT_ASSIGN	628	1	1	100.00
CONT_ASSIGN	636	1	1	100.00
CONT_ASSIGN	654	1	1	100.00
CONT_ASSIGN	659	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
ALWAYS	670	8	8	100.00
CONT_ASSIGN	683	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
CONT_ASSIGN	744	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	775	1	1	100.00
CONT_ASSIGN	787	1	1	100.00
CONT_ASSIGN	790	1	1	100.00
CONT_ASSIGN	794	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
CONT_ASSIGN	800	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
140	4	4
141	4	4
146	4	4
152	1	1
154	3	3
186	1	1
193	4	4
194	4	4
196	4	4
212	4	4
218	4	4
222	4	4
229	1	1
232	1	1
257	1	1
258	1	1
259	1	1
260	1	1
			MISSING_ELSE
291	1	1
292	1	1
302	1	1
305	1	1
308	1	1
326	1	1
331	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
371	1	1
372	1	1
			MISSING_ELSE
377	1	1
382	1	1
393	1	1
399	1	1
407	1	1
428	1	1
432	1	1
442	1	1
445	1	1
451	1	1
456	1	1
459	1	1
491	1	1
494	1	1
497	1	1
501	1	1
503	1	1
504	1	1
505	1	1
513	1	1
521	1	1
523	1	1
597	1	1
598	1	1
600	1	1
601	1	1
602	1	1
603	1	1
604	1	1
605	1	1
			MISSING_ELSE
610	1	1
614	1	1
617	1	1
624	1	1
628	1	1
636	1	1
654	1	1
659	1	1
664	4	4
670	1	1
671	1	1
672	1	1
673	1	1
674	1	1
675	1	1
676	1	1
677	1	1
			MISSING_ELSE
683	1	1
704	1	1
724	1	1
736	1	1
738	1	1
744	1	1
745	1	1
747	1	1
751	1	1
762	1	1
775	1	1
787	1	1
790	1	1
794	1	1
797	1	1
800	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Covered	Percent
Conditions	458	420	91.70
Logical	458	420	91.70
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
140-790	91.81
790-794	83.33

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	186	2	2	100.00
TERNARY	232	2	2	100.00
TERNARY	302	2	2	100.00
TERNARY	451	2	2	100.00
TERNARY	513	3	3	100.00
TERNARY	624	3	3	100.00
TERNARY	628	3	3	100.00
TERNARY	654	3	3	100.00
TERNARY	683	2	2	100.00
TERNARY	736	2	2	100.00
TERNARY	747	2	2	100.00
TERNARY	775	2	2	100.00
TERNARY	167	2	2	100.00
IF	257	3	3	100.00
IF	360	4	4	100.00
IF	600	4	4	100.00
IF	674	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	186	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	232	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	302	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	451	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T36,T52,T53
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	513	(hint_descram) ? 
-2-:	513	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T23,T41,T46
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	624	(forward) ? 
-2-:	624	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T23
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	628	(forward) ? 
-2-:	628	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T23
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T4,T23

	LineNo.	Expression
-1-:	654	(forward) ? 
-2-:	654	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T23
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	683	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	736	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T57,T177
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	747	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	775	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	257	if ((!rst_ni))
-2-:	259	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	360	if ((!rst_ni))
-2-:	364	if (rd_start)
-3-:	371	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	600	if ((!rst_ni))
-2-:	602	if (calc_req_start)
-3-:	604	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	674	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	390020584	710776	0	0
ExclusiveOps_A	390020584	389169140	0	0
ExclusiveProgHazard_A	390020584	389169140	0	0
ExclusiveState_A	390020584	389169140	0	0
ForwardCheck_A	390020584	1738848	0	0
IdleCheck_A	390020584	51082018	0	0
MaxBufs_A	1060	1060	0	0
OneHotAlloc_A	390020584	389169140	0	0
OneHotMatch_A	390020584	389169140	0	0
OneHotRspMatch_A	390020584	389169140	0	0
OneHotUpdate_A	390020584	389169140	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	710776	0	0
T1	210340	534	0	0
T2	1226	0	0	0
T3	3347	0	0	0
T4	580266	455	0	0
T5	201696	1544	0	0
T6	0	59	0	0
T11	1269	0	0	0
T14	3508	0	0	0
T18	962730	0	0	0
T19	1179	0	0	0
T20	1541	0	0	0
T22	0	68	0	0
T23	0	48	0	0
T24	0	134400	0	0
T26	0	30	0	0
T31	0	512	0	0
T41	0	1382	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	1738848	0	0
T1	210340	534	0	0
T2	1226	0	0	0
T3	3347	0	0	0
T4	580266	9438	0	0
T5	201696	0	0	0
T6	0	69	0	0
T7	0	4	0	0
T11	1269	0	0	0
T14	3508	0	0	0
T18	962730	0	0	0
T19	1179	0	0	0
T20	1541	0	0	0
T22	0	21	0	0
T23	0	29	0	0
T24	0	134400	0	0
T31	0	288	0	0
T40	0	6	0	0
T41	0	10637	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	51082018	0	0
T1	210340	1730	0	0
T2	1226	128	0	0
T3	3347	572	0	0
T4	580266	483589	0	0
T5	201696	22888	0	0
T11	1269	128	0	0
T14	3508	686	0	0
T18	962730	192	0	0
T19	1179	128	0	0
T20	1541	268	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390020584	389169140	0	0
T1	210340	210279	0	0
T2	1226	1151	0	0
T3	3347	2653	0	0
T4	580266	580096	0	0
T5	201696	192871	0	0
T11	1269	1192	0	0
T14	3508	2844	0	0
T18	962730	962565	0	0
T19	1179	1092	0	0
T20	1541	1278	0	0