Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.57 96.63 84.91 100.00 91.30 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.63 96.73 92.29 96.90 100.00 96.82 97.06


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.89 97.67 90.00 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prog_data.u_prog 97.56 100.00 93.85 95.00 100.00 96.49 100.00
u_disable_buf 100.00 100.00 100.00
u_erase 92.22 100.00 88.89 100.00 80.00
u_host_arb 93.98 75.93 100.00 100.00 100.00
u_host_outstanding_cnt 100.00 100.00
u_rd 96.90 97.64 92.67 100.00 99.37 94.83
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.59 98.88 96.23 100.00 97.83 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.64 96.96 93.94 100.00 100.00 97.88 97.06


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.89 97.67 90.00 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prog_data.u_prog 98.39 100.00 93.85 100.00 100.00 96.49 100.00
u_disable_buf 100.00 100.00 100.00
u_erase 92.22 100.00 88.89 100.00 80.00
u_host_arb 93.98 75.93 100.00 100.00 100.00
u_host_outstanding_cnt 100.00 100.00
u_rd 97.10 97.64 93.64 100.00 99.37 94.83
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : flash_phy_core
Line No.TotalCoveredPercent
TOTAL898898.88
ALWAYS15266100.00
ALWAYS16533100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN20011100.00
ALWAYS20344100.00
ALWAYS21566100.00
ALWAYS2296583.33
CONT_ASSIGN27711100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28711100.00
CONT_ASSIGN31711100.00
CONT_ASSIGN32111100.00
ALWAYS3252929100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55111100.00
CONT_ASSIGN55211100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55611100.00
CONT_ASSIGN55711100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56011100.00
CONT_ASSIGN56111100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN58511100.00
CONT_ASSIGN58611100.00
CONT_ASSIGN58711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
157 1 1
MISSING_ELSE
165 3 3
196 1 1
200 1 1
203 1 1
204 1 1
205 1 1
206 1 1
MISSING_ELSE
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
220 1 1
MISSING_ELSE
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
234 0 1
MISSING_ELSE
277 1 1
280 1 1
281 1 1
282 1 1
287 1 1
317 1 1
321 1 1
325 1 1
326 1 1
327 1 1
328 1 1
329 1 1
331 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
341 1 1
MISSING_ELSE
347 1 1
348 1 1
349 1 1
MISSING_ELSE
356 1 1
357 1 1
358 1 1
359 1 1
MISSING_ELSE
365 1 1
366 1 1
367 1 1
368 1 1
369 1 1
MISSING_ELSE
374 1 1
375 1 1
388 1 1
392 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
398 1 1
415 1 1
428 1 1
523 1 1
550 1 1
551 1 1
552 1 1
553 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
560 1 1
561 1 1
568 1 1
585 1 1
586 1 1
587 1 1


Cond Coverage for Module : flash_phy_core
TotalCoveredPercent
Conditions10610296.23
Logical10610296.23
Non-Logical00
Event00

 LINE       196
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T7
11CoveredT53,T201,T215

 LINE       196
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       200
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T7
11Not Covered

 LINE       205
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT53,T201,T215

 LINE       217
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT1,T2,T3

 LINE       231
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT4,T6,T7
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       231
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT1,T2,T3

 LINE       242
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T6,T7
110Not Covered
111CoveredT4,T6,T7

 LINE       242
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT4,T6,T7
101CoveredT4,T6,T7
110CoveredT61,T62,T69
111CoveredT4,T6,T7

 LINE       281
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT164,T50
10CoveredT4,T6,T7
11CoveredT4,T6,T7

 LINE       282
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T7
11CoveredT4,T6,T7

 LINE       317
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T7

 LINE       317
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01CoveredT165
10CoveredT1,T2,T3
11CoveredT4,T6,T7

 LINE       321
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT4,T6,T7
10CoveredT1,T2,T3
11CoveredT4,T6,T7

 LINE       336
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       338
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT3,T11,T23
11CoveredT1,T2,T5

 LINE       388
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT61,T62,T69
10CoveredT216,T217

 LINE       388
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT216,T217

 LINE       388
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT4,T6,T7
10CoveredT1,T2,T3
11CoveredT61,T62,T69

 LINE       388
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       392
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T7

 LINE       393
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T7

 LINE       394
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T7

 LINE       395
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T7

 LINE       396
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       397
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T5

 LINE       398
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT3,T11,T23
10CoveredT1,T2,T3
11CoveredT3,T11,T23

 LINE       398
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT23,T24,T25
10CoveredT3,T11,T23

 LINE       428
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT53,T201

 LINE       428
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT4,T6,T7
10CoveredT53,T201
11CoveredT53,T201

 LINE       428
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T7

 LINE       431
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       431
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T6,T7
10CoveredT1,T2,T3

 LINE       431
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT53,T201

 LINE       523
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT13,T14,T15
10CoveredT13,T14,T15

 LINE       550
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T11,T7

 LINE       551
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T11,T7

 LINE       552
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T11,T7

 LINE       553
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T11,T7

FSM Coverage for Module : flash_phy_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
StCtrl 341 Covered T3,T11,T23
StCtrlProg 339 Covered T1,T2,T5
StCtrlRead 337 Covered T1,T2,T3
StDisable 335 Covered T3,T11,T12
StIdle 349 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
StCtrl->StIdle 369 Covered T3,T11,T23
StCtrlProg->StIdle 359 Covered T1,T2,T5
StCtrlRead->StIdle 349 Covered T1,T2,T3
StIdle->StCtrl 341 Covered T3,T11,T23
StIdle->StCtrlProg 339 Covered T1,T2,T5
StIdle->StCtrlRead 337 Covered T1,T2,T3
StIdle->StDisable 335 Covered T3,T11,T12



Branch Coverage for Module : flash_phy_core
Line No.TotalCoveredPercent
Branches 46 45 97.83
TERNARY 317 2 2 100.00
TERNARY 392 2 2 100.00
TERNARY 393 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 395 2 2 100.00
TERNARY 552 2 2 100.00
TERNARY 553 2 2 100.00
TERNARY 431 2 2 100.00
IF 152 4 4 100.00
IF 165 2 2 100.00
IF 203 3 3 100.00
IF 215 4 4 100.00
IF 229 4 3 75.00
CASE 331 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 317 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 395 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 552 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T2,T11,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 553 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T2,T11,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 431 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Covered T53,T201
0 Covered T1,T2,T3


LineNo. Expression -1-: 152 if ((!rst_ni)) -2-: 154 if (ctrl_rsp_vld) -3-: 156 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T4,T6,T7
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 165 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 203 if ((!rst_ni)) -2-: 205 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T53,T201,T215
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 215 if ((!rst_ni)) -2-: 217 if ((host_outstanding == '0)) -3-: 219 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T53,T201
0 0 0 Covered T4,T6,T7


LineNo. Expression -1-: 229 if ((!rst_ni)) -2-: 231 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 233 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 331 case (state_q) -2-: 334 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 336 if ((ctrl_gnt && rd_i)) -4-: 338 if ((ctrl_gnt && prog_i)) -5-: 340 if (ctrl_gnt) -6-: 347 if (rd_stage_data_valid) -7-: 357 if (prog_ack) -8-: 367 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T3,T11,T12
StIdle 0 1 - - - - - Covered T1,T2,T3
StIdle 0 0 1 - - - - Covered T1,T2,T5
StIdle 0 0 0 1 - - - Covered T3,T11,T23
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T1,T2,T3
StCtrlRead - - - - 0 - - Covered T1,T2,T3
StCtrlProg - - - - - 1 - Covered T1,T2,T5
StCtrlProg - - - - - 0 - Covered T1,T2,T5
StCtrl - - - - - - 1 Covered T3,T11,T23
StCtrl - - - - - - 0 Covered T3,T11,T23
StDisable - - - - - - - Covered T3,T11,T12
default - - - - - - - Covered T13,T14,T15


Assert Coverage for Module : flash_phy_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
ArbCntMax_A 787959466 2972210 0 0
CtrlPrio_A 787959466 2972210 0 0
HostTransIdleChk_A 787959466 43896939 0 0
NoRemainder_A 2090 2090 0 0
OneHotReqs_A 787959466 786155052 0 0
Pow2Multiple_A 2090 2090 0 0
RdTxnCheck_A 787558244 785753830 0 0
u_state_regs_A 787959466 786155052 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 787959466 2972210 0 0
T4 240488 86108 0 0
T5 6768 0 0 0
T6 89552 1817 0 0
T7 343582 7093 0 0
T11 770710 0 0 0
T12 2034 0 0 0
T16 6624 0 0 0
T17 78966 4518 0 0
T18 202026 8973 0 0
T20 0 5472 0 0
T23 1033878 0 0 0
T38 0 4646 0 0
T39 0 53 0 0
T52 0 7638 0 0
T56 0 10839 0 0
T64 0 14271 0 0
T171 0 1518 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 787959466 2972210 0 0
T4 240488 86108 0 0
T5 6768 0 0 0
T6 89552 1817 0 0
T7 343582 7093 0 0
T11 770710 0 0 0
T12 2034 0 0 0
T16 6624 0 0 0
T17 78966 4518 0 0
T18 202026 8973 0 0
T20 0 5472 0 0
T23 1033878 0 0 0
T38 0 4646 0 0
T39 0 53 0 0
T52 0 7638 0 0
T56 0 10839 0 0
T64 0 14271 0 0
T171 0 1518 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 787959466 43896939 0 0
T4 240488 835227 0 0
T5 6768 0 0 0
T6 89552 32144 0 0
T7 343582 51128 0 0
T11 770710 0 0 0
T12 2034 0 0 0
T16 6624 0 0 0
T17 78966 33364 0 0
T18 202026 80237 0 0
T23 1033878 0 0 0
T26 0 32 0 0
T38 0 55006 0 0
T51 0 884 0 0
T52 0 82054 0 0
T56 0 134787 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2090 2090 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T7 2 2 0 0
T11 2 2 0 0
T16 2 2 0 0
T17 2 2 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 787959466 786155052 0 0
T1 4582 4430 0 0
T2 437420 437226 0 0
T3 2514 2376 0 0
T4 240488 240460 0 0
T5 6768 6580 0 0
T6 89552 89422 0 0
T7 343582 343476 0 0
T11 770710 770680 0 0
T16 6624 6486 0 0
T17 78966 78710 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2090 2090 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T7 2 2 0 0
T11 2 2 0 0
T16 2 2 0 0
T17 2 2 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 787558244 785753830 0 0
T1 4582 4430 0 0
T2 437420 437226 0 0
T3 2514 2376 0 0
T4 240488 240460 0 0
T5 6768 6580 0 0
T6 89552 89422 0 0
T7 343582 343476 0 0
T11 770710 770680 0 0
T16 6624 6486 0 0
T17 78966 78710 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 787959466 786155052 0 0
T1 4582 4430 0 0
T2 437420 437226 0 0
T3 2514 2376 0 0
T4 240488 240460 0 0
T5 6768 6580 0 0
T6 89552 89422 0 0
T7 343582 343476 0 0
T11 770710 770680 0 0
T16 6624 6486 0 0
T17 78966 78710 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Line No.TotalCoveredPercent
TOTAL898696.63
ALWAYS15266100.00
ALWAYS16533100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN20011100.00
ALWAYS2034375.00
ALWAYS2156583.33
ALWAYS2296583.33
CONT_ASSIGN27711100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28711100.00
CONT_ASSIGN31711100.00
CONT_ASSIGN32111100.00
ALWAYS3252929100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55111100.00
CONT_ASSIGN55211100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55611100.00
CONT_ASSIGN55711100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56011100.00
CONT_ASSIGN56111100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN58511100.00
CONT_ASSIGN58611100.00
CONT_ASSIGN58711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
157 1 1
MISSING_ELSE
165 3 3
196 1 1
200 1 1
203 1 1
204 1 1
205 1 1
206 0 1
MISSING_ELSE
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
220 0 1
MISSING_ELSE
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
234 0 1
MISSING_ELSE
277 1 1
280 1 1
281 1 1
282 1 1
287 1 1
317 1 1
321 1 1
325 1 1
326 1 1
327 1 1
328 1 1
329 1 1
331 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
341 1 1
MISSING_ELSE
347 1 1
348 1 1
349 1 1
MISSING_ELSE
356 1 1
357 1 1
358 1 1
359 1 1
MISSING_ELSE
365 1 1
366 1 1
367 1 1
368 1 1
369 1 1
MISSING_ELSE
374 1 1
375 1 1
388 1 1
392 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
398 1 1
415 1 1
428 1 1
523 1 1
550 1 1
551 1 1
552 1 1
553 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
560 1 1
561 1 1
568 1 1
585 1 1
586 1 1
587 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
TotalCoveredPercent
Conditions1069084.91
Logical1069084.91
Non-Logical00
Event00

 LINE       196
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T7
11Not Covered

 LINE       196
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       200
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T7
11Not Covered

 LINE       205
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       217
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT1,T2,T3

 LINE       231
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT4,T6,T7
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       231
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT1,T2,T3

 LINE       242
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T6,T7
110Not Covered
111CoveredT4,T6,T7

 LINE       242
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT4,T6,T7
101CoveredT4,T6,T7
110Not Covered
111CoveredT4,T6,T7

 LINE       281
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT164
10CoveredT4,T6,T7
11CoveredT4,T6,T7

 LINE       282
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT1,T4,T6
10CoveredT4,T6,T7
11CoveredT4,T6,T7

 LINE       317
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T7

 LINE       317
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT4,T6,T7

 LINE       321
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT4,T6,T7
10CoveredT1,T2,T3
11CoveredT4,T6,T7

 LINE       336
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T4,T6

 LINE       338
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT3,T11,T23
11CoveredT1,T2,T5

 LINE       388
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       388
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       388
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT4,T6,T7
10CoveredT1,T2,T3
11Not Covered

 LINE       388
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       392
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T7

 LINE       393
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T7

 LINE       394
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T7

 LINE       395
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T7

 LINE       396
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T4,T6

 LINE       397
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T3,T4
11CoveredT1,T2,T5

 LINE       398
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT3,T11,T23
10CoveredT1,T2,T4
11CoveredT3,T11,T23

 LINE       398
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT23,T24,T25
10CoveredT3,T11,T23

 LINE       428
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       428
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT4,T6,T7
10Not Covered
11Not Covered

 LINE       428
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T7

 LINE       431
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T4,T6

 LINE       431
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T6,T7
10CoveredT1,T2,T3

 LINE       431
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       523
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT13,T14,T15
10CoveredT13,T14,T15

 LINE       550
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T18,T38
10CoveredT11,T18,T66

 LINE       551
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T18,T38
10CoveredT11,T18,T66

 LINE       552
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T18,T66

 LINE       553
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T18,T66

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
StCtrl 341 Covered T3,T11,T23
StCtrlProg 339 Covered T1,T2,T5
StCtrlRead 337 Covered T1,T4,T6
StDisable 335 Covered T3,T11,T12
StIdle 349 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
StCtrl->StIdle 369 Covered T3,T11,T23
StCtrlProg->StIdle 359 Covered T1,T2,T5
StCtrlRead->StIdle 349 Covered T1,T4,T6
StIdle->StCtrl 341 Covered T3,T11,T23
StIdle->StCtrlProg 339 Covered T1,T2,T5
StIdle->StCtrlRead 337 Covered T1,T4,T6
StIdle->StDisable 335 Covered T3,T11,T12



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Line No.TotalCoveredPercent
Branches 46 42 91.30
TERNARY 317 2 2 100.00
TERNARY 392 2 2 100.00
TERNARY 393 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 395 2 2 100.00
TERNARY 552 2 2 100.00
TERNARY 553 2 2 100.00
TERNARY 431 2 1 50.00
IF 152 4 4 100.00
IF 165 2 2 100.00
IF 203 3 2 66.67
IF 215 4 3 75.00
IF 229 4 3 75.00
CASE 331 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 317 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 395 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 552 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T11,T18,T66
0 Covered T1,T2,T3


LineNo. Expression -1-: 553 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T11,T18,T66
0 Covered T1,T2,T3


LineNo. Expression -1-: 431 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 152 if ((!rst_ni)) -2-: 154 if (ctrl_rsp_vld) -3-: 156 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T4,T6,T7
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 165 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 203 if ((!rst_ni)) -2-: 205 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 215 if ((!rst_ni)) -2-: 217 if ((host_outstanding == '0)) -3-: 219 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T4,T6,T7


LineNo. Expression -1-: 229 if ((!rst_ni)) -2-: 231 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 233 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 331 case (state_q) -2-: 334 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 336 if ((ctrl_gnt && rd_i)) -4-: 338 if ((ctrl_gnt && prog_i)) -5-: 340 if (ctrl_gnt) -6-: 347 if (rd_stage_data_valid) -7-: 357 if (prog_ack) -8-: 367 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T3,T11,T12
StIdle 0 1 - - - - - Covered T1,T4,T6
StIdle 0 0 1 - - - - Covered T1,T2,T5
StIdle 0 0 0 1 - - - Covered T3,T11,T23
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T1,T4,T6
StCtrlRead - - - - 0 - - Covered T1,T4,T6
StCtrlProg - - - - - 1 - Covered T1,T2,T5
StCtrlProg - - - - - 0 - Covered T1,T2,T5
StCtrl - - - - - - 1 Covered T3,T11,T23
StCtrl - - - - - - 0 Covered T3,T11,T23
StDisable - - - - - - - Covered T3,T11,T12
default - - - - - - - Covered T13,T14,T15


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
ArbCntMax_A 393979733 1353096 0 0
CtrlPrio_A 393979733 1353096 0 0
HostTransIdleChk_A 393979733 21370198 0 0
NoRemainder_A 1045 1045 0 0
OneHotReqs_A 393979733 393077526 0 0
Pow2Multiple_A 1045 1045 0 0
RdTxnCheck_A 393779122 392876915 0 0
u_state_regs_A 393979733 393077526 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393979733 1353096 0 0
T4 120244 46659 0 0
T5 3384 0 0 0
T6 44776 680 0 0
T7 171791 3551 0 0
T11 385355 0 0 0
T12 1017 0 0 0
T16 3312 0 0 0
T17 39483 0 0 0
T18 101013 3894 0 0
T20 0 2853 0 0
T23 516939 0 0 0
T39 0 53 0 0
T52 0 4635 0 0
T56 0 6372 0 0
T64 0 7938 0 0
T171 0 1518 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393979733 1353096 0 0
T4 120244 46659 0 0
T5 3384 0 0 0
T6 44776 680 0 0
T7 171791 3551 0 0
T11 385355 0 0 0
T12 1017 0 0 0
T16 3312 0 0 0
T17 39483 0 0 0
T18 101013 3894 0 0
T20 0 2853 0 0
T23 516939 0 0 0
T39 0 53 0 0
T52 0 4635 0 0
T56 0 6372 0 0
T64 0 7938 0 0
T171 0 1518 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393979733 21370198 0 0
T4 120244 411927 0 0
T5 3384 0 0 0
T6 44776 15164 0 0
T7 171791 24134 0 0
T11 385355 0 0 0
T12 1017 0 0 0
T16 3312 0 0 0
T17 39483 16904 0 0
T18 101013 39576 0 0
T23 516939 0 0 0
T26 0 16 0 0
T38 0 29792 0 0
T51 0 353 0 0
T52 0 47602 0 0
T56 0 76815 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1045 1045 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393979733 393077526 0 0
T1 2291 2215 0 0
T2 218710 218613 0 0
T3 1257 1188 0 0
T4 120244 120230 0 0
T5 3384 3290 0 0
T6 44776 44711 0 0
T7 171791 171738 0 0
T11 385355 385340 0 0
T16 3312 3243 0 0
T17 39483 39355 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1045 1045 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393779122 392876915 0 0
T1 2291 2215 0 0
T2 218710 218613 0 0
T3 1257 1188 0 0
T4 120244 120230 0 0
T5 3384 3290 0 0
T6 44776 44711 0 0
T7 171791 171738 0 0
T11 385355 385340 0 0
T16 3312 3243 0 0
T17 39483 39355 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393979733 393077526 0 0
T1 2291 2215 0 0
T2 218710 218613 0 0
T3 1257 1188 0 0
T4 120244 120230 0 0
T5 3384 3290 0 0
T6 44776 44711 0 0
T7 171791 171738 0 0
T11 385355 385340 0 0
T16 3312 3243 0 0
T17 39483 39355 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Line No.TotalCoveredPercent
TOTAL898898.88
ALWAYS15266100.00
ALWAYS16533100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN20011100.00
ALWAYS20344100.00
ALWAYS21566100.00
ALWAYS2296583.33
CONT_ASSIGN27711100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28711100.00
CONT_ASSIGN31711100.00
CONT_ASSIGN32111100.00
ALWAYS3252929100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN42811100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55111100.00
CONT_ASSIGN55211100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55611100.00
CONT_ASSIGN55711100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56011100.00
CONT_ASSIGN56111100.00
CONT_ASSIGN56811100.00
CONT_ASSIGN58511100.00
CONT_ASSIGN58611100.00
CONT_ASSIGN58711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
157 1 1
MISSING_ELSE
165 3 3
196 1 1
200 1 1
203 1 1
204 1 1
205 1 1
206 1 1
MISSING_ELSE
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
220 1 1
MISSING_ELSE
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
234 0 1
MISSING_ELSE
277 1 1
280 1 1
281 1 1
282 1 1
287 1 1
317 1 1
321 1 1
325 1 1
326 1 1
327 1 1
328 1 1
329 1 1
331 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
341 1 1
MISSING_ELSE
347 1 1
348 1 1
349 1 1
MISSING_ELSE
356 1 1
357 1 1
358 1 1
359 1 1
MISSING_ELSE
365 1 1
366 1 1
367 1 1
368 1 1
369 1 1
MISSING_ELSE
374 1 1
375 1 1
388 1 1
392 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
398 1 1
415 1 1
428 1 1
523 1 1
550 1 1
551 1 1
552 1 1
553 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
560 1 1
561 1 1
568 1 1
585 1 1
586 1 1
587 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
TotalCoveredPercent
Conditions10610296.23
Logical10610296.23
Non-Logical00
Event00

 LINE       196
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T7
11CoveredT53,T201,T215

 LINE       196
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       200
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T7
11Not Covered

 LINE       205
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT53,T201,T215

 LINE       217
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT1,T2,T3

 LINE       231
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT4,T6,T7
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       231
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT4,T6,T7
1CoveredT1,T2,T3

 LINE       242
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T6,T7
110Not Covered
111CoveredT4,T6,T7

 LINE       242
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT4,T6,T7
101CoveredT4,T6,T7
110CoveredT61,T62,T69
111CoveredT4,T6,T7

 LINE       281
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT50
10CoveredT4,T6,T7
11CoveredT4,T6,T7

 LINE       282
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T6,T7
11CoveredT4,T6,T7

 LINE       317
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T7

 LINE       317
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01CoveredT165
10CoveredT1,T2,T3
11CoveredT4,T6,T7

 LINE       321
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT4,T6,T7
10CoveredT1,T2,T3
11CoveredT4,T6,T7

 LINE       336
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T4,T6
10CoveredT1,T2,T5
11CoveredT1,T2,T3

 LINE       338
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT11,T23,T24
11CoveredT1,T2,T5

 LINE       388
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT61,T62,T69
10CoveredT216,T217

 LINE       388
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT216,T217

 LINE       388
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT4,T6,T7
10CoveredT1,T2,T3
11CoveredT61,T62,T69

 LINE       388
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       392
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T7

 LINE       393
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T7

 LINE       394
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T7

 LINE       395
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T7

 LINE       396
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T5
11CoveredT1,T2,T3

 LINE       397
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T5

 LINE       398
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT3,T11,T23
10CoveredT1,T2,T3
11CoveredT11,T23,T24

 LINE       398
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT23,T24,T25
10CoveredT3,T11,T23

 LINE       428
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT53,T201

 LINE       428
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT4,T6,T7
10CoveredT53,T201
11CoveredT53,T201

 LINE       428
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T6,T7

 LINE       431
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T5
11CoveredT1,T2,T3

 LINE       431
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T6,T7
10CoveredT1,T2,T3

 LINE       431
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT53,T201

 LINE       523
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT13,T14,T15
10CoveredT13,T14,T15

 LINE       550
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T11,T7

 LINE       551
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T11,T7

 LINE       552
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T11,T7

 LINE       553
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T11,T7

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
StCtrl 341 Covered T11,T23,T24
StCtrlProg 339 Covered T1,T2,T5
StCtrlRead 337 Covered T1,T2,T3
StDisable 335 Covered T3,T11,T12
StIdle 349 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
StCtrl->StIdle 369 Covered T11,T23,T24
StCtrlProg->StIdle 359 Covered T1,T2,T5
StCtrlRead->StIdle 349 Covered T1,T2,T3
StIdle->StCtrl 341 Covered T11,T23,T24
StIdle->StCtrlProg 339 Covered T1,T2,T5
StIdle->StCtrlRead 337 Covered T1,T2,T3
StIdle->StDisable 335 Covered T3,T11,T12



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Line No.TotalCoveredPercent
Branches 46 45 97.83
TERNARY 317 2 2 100.00
TERNARY 392 2 2 100.00
TERNARY 393 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 395 2 2 100.00
TERNARY 552 2 2 100.00
TERNARY 553 2 2 100.00
TERNARY 431 2 2 100.00
IF 152 4 4 100.00
IF 165 2 2 100.00
IF 203 3 3 100.00
IF 215 4 4 100.00
IF 229 4 3 75.00
CASE 331 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 317 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 395 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 552 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T2,T11,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 553 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T2,T11,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 431 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Covered T53,T201
0 Covered T1,T2,T3


LineNo. Expression -1-: 152 if ((!rst_ni)) -2-: 154 if (ctrl_rsp_vld) -3-: 156 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T4,T6,T7
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 165 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 203 if ((!rst_ni)) -2-: 205 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T53,T201,T215
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 215 if ((!rst_ni)) -2-: 217 if ((host_outstanding == '0)) -3-: 219 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T53,T201
0 0 0 Covered T4,T6,T7


LineNo. Expression -1-: 229 if ((!rst_ni)) -2-: 231 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 233 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 331 case (state_q) -2-: 334 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 336 if ((ctrl_gnt && rd_i)) -4-: 338 if ((ctrl_gnt && prog_i)) -5-: 340 if (ctrl_gnt) -6-: 347 if (rd_stage_data_valid) -7-: 357 if (prog_ack) -8-: 367 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T3,T11,T12
StIdle 0 1 - - - - - Covered T1,T2,T3
StIdle 0 0 1 - - - - Covered T1,T2,T5
StIdle 0 0 0 1 - - - Covered T11,T23,T24
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T1,T2,T3
StCtrlRead - - - - 0 - - Covered T1,T2,T3
StCtrlProg - - - - - 1 - Covered T1,T2,T5
StCtrlProg - - - - - 0 - Covered T1,T2,T5
StCtrl - - - - - - 1 Covered T11,T23,T24
StCtrl - - - - - - 0 Covered T11,T23,T24
StDisable - - - - - - - Covered T3,T11,T12
default - - - - - - - Covered T13,T14,T15


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
ArbCntMax_A 393979733 1619114 0 0
CtrlPrio_A 393979733 1619114 0 0
HostTransIdleChk_A 393979733 22526741 0 0
NoRemainder_A 1045 1045 0 0
OneHotReqs_A 393979733 393077526 0 0
Pow2Multiple_A 1045 1045 0 0
RdTxnCheck_A 393779122 392876915 0 0
u_state_regs_A 393979733 393077526 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393979733 1619114 0 0
T4 120244 39449 0 0
T5 3384 0 0 0
T6 44776 1137 0 0
T7 171791 3542 0 0
T11 385355 0 0 0
T12 1017 0 0 0
T16 3312 0 0 0
T17 39483 4518 0 0
T18 101013 5079 0 0
T20 0 2619 0 0
T23 516939 0 0 0
T38 0 4646 0 0
T52 0 3003 0 0
T56 0 4467 0 0
T64 0 6333 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393979733 1619114 0 0
T4 120244 39449 0 0
T5 3384 0 0 0
T6 44776 1137 0 0
T7 171791 3542 0 0
T11 385355 0 0 0
T12 1017 0 0 0
T16 3312 0 0 0
T17 39483 4518 0 0
T18 101013 5079 0 0
T20 0 2619 0 0
T23 516939 0 0 0
T38 0 4646 0 0
T52 0 3003 0 0
T56 0 4467 0 0
T64 0 6333 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393979733 22526741 0 0
T4 120244 423300 0 0
T5 3384 0 0 0
T6 44776 16980 0 0
T7 171791 26994 0 0
T11 385355 0 0 0
T12 1017 0 0 0
T16 3312 0 0 0
T17 39483 16460 0 0
T18 101013 40661 0 0
T23 516939 0 0 0
T26 0 16 0 0
T38 0 25214 0 0
T51 0 531 0 0
T52 0 34452 0 0
T56 0 57972 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1045 1045 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393979733 393077526 0 0
T1 2291 2215 0 0
T2 218710 218613 0 0
T3 1257 1188 0 0
T4 120244 120230 0 0
T5 3384 3290 0 0
T6 44776 44711 0 0
T7 171791 171738 0 0
T11 385355 385340 0 0
T16 3312 3243 0 0
T17 39483 39355 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1045 1045 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T11 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393779122 392876915 0 0
T1 2291 2215 0 0
T2 218710 218613 0 0
T3 1257 1188 0 0
T4 120244 120230 0 0
T5 3384 3290 0 0
T6 44776 44711 0 0
T7 171791 171738 0 0
T11 385355 385340 0 0
T16 3312 3243 0 0
T17 39483 39355 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393979733 393077526 0 0
T1 2291 2215 0 0
T2 218710 218613 0 0
T3 1257 1188 0 0
T4 120244 120230 0 0
T5 3384 3290 0 0
T6 44776 44711 0 0
T7 171791 171738 0 0
T11 385355 385340 0 0
T16 3312 3243 0 0
T17 39483 39355 0 0