Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	22978587	1		T1	58		T2	94		T3	68
full_word	7524620	1		T1	3		T2	56		T3	167

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30502967	1		T1	61		T2	150		T3	235
auto[TlIntgErrCmd]	83	1		T237	3		T238	3		T239	2
auto[TlIntgErrData]	87	1		T237	4		T238	2		T239	5
auto[TlIntgErrBoth]	70	1		T237	3		T238	5		T239	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	26114135	1		T1	57		T2	109		T3	107
auto[1]	4389072	1		T1	4		T2	41		T3	128

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22327064	1		T1	57		T2	86		T3	54
auto[TlIntgErrNone]	partial	auto[1]	651303	1		T1	1		T2	8		T3	14
auto[TlIntgErrNone]	full_word	auto[0]	3786967	1		T2	23		T3	53		T13	473
auto[TlIntgErrNone]	full_word	auto[1]	3737633	1		T1	3		T2	33		T3	114
auto[TlIntgErrCmd]	partial	auto[0]	29	1		T237	1		T238	2		T239	1
auto[TlIntgErrCmd]	partial	auto[1]	46	1		T237	1		T238	1		T336	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T251	1		T343	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T237	1		T239	1		T344	1
auto[TlIntgErrData]	partial	auto[0]	36	1		T237	2		T238	2		T239	3
auto[TlIntgErrData]	partial	auto[1]	42	1		T237	1		T239	1		T338	3
auto[TlIntgErrData]	full_word	auto[0]	7	1		T237	1		T239	1		T336	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T337	1		T345	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	29	1		T237	2		T238	2		T239	3
auto[TlIntgErrBoth]	partial	auto[1]	38	1		T237	1		T238	3		T336	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T346	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T336	1		T341	1		-	-

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20566	1		T112	365		T113	1041		T81	19
full_word	3782868	1		T1	10		T13	261		T14	208

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3803205	1		T1	10		T13	261		T14	208
auto[TlIntgErrCmd]	81	1		T237	2		T238	4		T239	3
auto[TlIntgErrData]	82	1		T237	2		T238	4		T239	2
auto[TlIntgErrBoth]	66	1		T237	5		T238	2		T239	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3777061	1		T1	10		T13	261		T14	208
auto[1]	26373	1		T112	590		T113	1209		T81	26

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1288	1		T112	16		T113	47		T81	1
auto[TlIntgErrNone]	partial	auto[1]	19067	1		T112	349		T113	994		T81	18
auto[TlIntgErrNone]	full_word	auto[0]	3775675	1		T1	10		T13	261		T14	208
auto[TlIntgErrNone]	full_word	auto[1]	7175	1		T112	241		T113	215		T81	8
auto[TlIntgErrCmd]	partial	auto[0]	29	1		T238	1		T338	2		T337	2
auto[TlIntgErrCmd]	partial	auto[1]	46	1		T237	2		T238	3		T239	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T343	1		T341	1		T347	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T251	1		T339	1		T342	1
auto[TlIntgErrData]	partial	auto[0]	33	1		T239	1		T336	2		T338	4
auto[TlIntgErrData]	partial	auto[1]	41	1		T237	2		T238	4		T336	1
auto[TlIntgErrData]	full_word	auto[0]	6	1		T239	1		T336	1		T344	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T348	1		T339	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	24	1		T238	1		T239	1		T336	1
auto[TlIntgErrBoth]	partial	auto[1]	38	1		T237	4		T238	1		T239	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T237	1		T239	1		T342	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1		T347	1		-	-		-	-