Module Definition
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Module : prim_mubi4_sender
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi 100.00 100.00 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi 100.00 100.00 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi 100.00 100.00 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi 100.00 100.00 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi 100.00 100.00 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi 100.00 100.00 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi 100.00 100.00 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi 100.00 100.00 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi 100.00 100.00 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi 100.00 100.00 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi 100.00 100.00 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
67.86 35.71 100.00 gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
67.86 35.71 100.00 gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
71.43 42.86 100.00 gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
71.43 42.86 100.00 gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
67.86 35.71 100.00 gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
67.86 35.71 100.00 gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
71.43 42.86 100.00 gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
71.43 42.86 100.00 gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_sec_buf.u_prim_sec_buf 100.00 100.00

Line Coverage for Module : prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 1/1 assign mubi_int = mubi; Tests: T1 T2 T3  49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 1/1 if (!rst_ni) begin Tests: T1 T2 T3  56 1/1 unused_logic <= MuBi4False; Tests: T1 T2 T3  57 end else begin 58 1/1 unused_logic <= mubi_i; Tests: T1 T2 T3  59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 assign mubi_out = mubi_int; 83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Branch Coverage for Module : prim_mubi4_sender
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00


55 if (!rst_ni) begin -1- 56 unused_logic <= MuBi4False; ==> 57 end else begin 58 unused_logic <= mubi_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 2147483647 2147483647 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 19632 18744 0 0
T2 23412 22512 0 0
T3 40584 39720 0 0
T7 50952 43128 0 0
T13 284520 283680 0 0
T14 74952 73776 0 0
T15 40980 40284 0 0
T18 35352 34344 0 0
T19 5830932 5614452 0 0
T20 844296 843372 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 1/1 assign mubi_int = mubi; Tests: T1 T2 T3  49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 1/1 if (!rst_ni) begin Tests: T1 T2 T3  56 1/1 unused_logic <= MuBi4False; Tests: T1 T2 T3  57 end else begin 58 1/1 unused_logic <= mubi_i; Tests: T1 T2 T3  59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 assign mubi_out = mubi_int; 83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00


55 if (!rst_ni) begin -1- 56 unused_logic <= MuBi4False; ==> 57 end else begin 58 unused_logic <= mubi_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 384864519 384030917 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384864519 384030917 0 0
T1 1636 1562 0 0
T2 1951 1876 0 0
T3 3382 3310 0 0
T7 4246 3594 0 0
T13 23710 23640 0 0
T14 6246 6148 0 0
T15 3415 3357 0 0
T18 2946 2862 0 0
T19 485911 467871 0 0
T20 70358 70281 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 1/1 assign mubi_int = mubi; Tests: T1 T2 T3  49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 1/1 if (!rst_ni) begin Tests: T1 T2 T3  56 1/1 unused_logic <= MuBi4False; Tests: T1 T2 T3  57 end else begin 58 1/1 unused_logic <= mubi_i; Tests: T1 T2 T3  59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 assign mubi_out = mubi_int; 83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00


55 if (!rst_ni) begin -1- 56 unused_logic <= MuBi4False; ==> 57 end else begin 58 unused_logic <= mubi_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 384864519 384030917 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384864519 384030917 0 0
T1 1636 1562 0 0
T2 1951 1876 0 0
T3 3382 3310 0 0
T7 4246 3594 0 0
T13 23710 23640 0 0
T14 6246 6148 0 0
T15 3415 3357 0 0
T18 2946 2862 0 0
T19 485911 467871 0 0
T20 70358 70281 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 1/1 assign mubi_int = mubi; Tests: T1 T2 T3  49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 1/1 if (!rst_ni) begin Tests: T1 T2 T3  56 1/1 unused_logic <= MuBi4False; Tests: T1 T2 T3  57 end else begin 58 1/1 unused_logic <= mubi_i; Tests: T1 T2 T3  59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 assign mubi_out = mubi_int; 83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00


55 if (!rst_ni) begin -1- 56 unused_logic <= MuBi4False; ==> 57 end else begin 58 unused_logic <= mubi_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 384864519 384030917 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384864519 384030917 0 0
T1 1636 1562 0 0
T2 1951 1876 0 0
T3 3382 3310 0 0
T7 4246 3594 0 0
T13 23710 23640 0 0
T14 6246 6148 0 0
T15 3415 3357 0 0
T18 2946 2862 0 0
T19 485911 467871 0 0
T20 70358 70281 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 1/1 assign mubi_int = mubi; Tests: T1 T2 T3  49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 1/1 if (!rst_ni) begin Tests: T1 T2 T3  56 1/1 unused_logic <= MuBi4False; Tests: T1 T2 T3  57 end else begin 58 1/1 unused_logic <= mubi_i; Tests: T1 T2 T3  59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 assign mubi_out = mubi_int; 83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00


55 if (!rst_ni) begin -1- 56 unused_logic <= MuBi4False; ==> 57 end else begin 58 unused_logic <= mubi_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 384864519 384030917 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384864519 384030917 0 0
T1 1636 1562 0 0
T2 1951 1876 0 0
T3 3382 3310 0 0
T7 4246 3594 0 0
T13 23710 23640 0 0
T14 6246 6148 0 0
T15 3415 3357 0 0
T18 2946 2862 0 0
T19 485911 467871 0 0
T20 70358 70281 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 1/1 assign mubi_int = mubi; Tests: T1 T2 T3  49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 1/1 if (!rst_ni) begin Tests: T1 T2 T3  56 1/1 unused_logic <= MuBi4False; Tests: T1 T2 T3  57 end else begin 58 1/1 unused_logic <= mubi_i; Tests: T1 T2 T3  59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 assign mubi_out = mubi_int; 83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00


55 if (!rst_ni) begin -1- 56 unused_logic <= MuBi4False; ==> 57 end else begin 58 unused_logic <= mubi_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 384864519 384030917 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384864519 384030917 0 0
T1 1636 1562 0 0
T2 1951 1876 0 0
T3 3382 3310 0 0
T7 4246 3594 0 0
T13 23710 23640 0 0
T14 6246 6148 0 0
T15 3415 3357 0 0
T18 2946 2862 0 0
T19 485911 467871 0 0
T20 70358 70281 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 1/1 assign mubi_int = mubi; Tests: T1 T2 T3  49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 1/1 if (!rst_ni) begin Tests: T1 T2 T3  56 1/1 unused_logic <= MuBi4False; Tests: T1 T2 T3  57 end else begin 58 1/1 unused_logic <= mubi_i; Tests: T1 T2 T3  59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 assign mubi_out = mubi_int; 83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00


55 if (!rst_ni) begin -1- 56 unused_logic <= MuBi4False; ==> 57 end else begin 58 unused_logic <= mubi_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 384864519 384030917 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384864519 384030917 0 0
T1 1636 1562 0 0
T2 1951 1876 0 0
T3 3382 3310 0 0
T7 4246 3594 0 0
T13 23710 23640 0 0
T14 6246 6148 0 0
T15 3415 3357 0 0
T18 2946 2862 0 0
T19 485911 467871 0 0
T20 70358 70281 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 1/1 assign mubi_int = mubi; Tests: T1 T2 T3  49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 1/1 if (!rst_ni) begin Tests: T1 T2 T3  56 1/1 unused_logic <= MuBi4False; Tests: T1 T2 T3  57 end else begin 58 1/1 unused_logic <= mubi_i; Tests: T1 T2 T3  59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 assign mubi_out = mubi_int; 83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00


55 if (!rst_ni) begin -1- 56 unused_logic <= MuBi4False; ==> 57 end else begin 58 unused_logic <= mubi_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 384864519 384030917 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384864519 384030917 0 0
T1 1636 1562 0 0
T2 1951 1876 0 0
T3 3382 3310 0 0
T7 4246 3594 0 0
T13 23710 23640 0 0
T14 6246 6148 0 0
T15 3415 3357 0 0
T18 2946 2862 0 0
T19 485911 467871 0 0
T20 70358 70281 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 1/1 assign mubi_int = mubi; Tests: T1 T2 T3  49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 1/1 if (!rst_ni) begin Tests: T1 T2 T3  56 1/1 unused_logic <= MuBi4False; Tests: T1 T2 T3  57 end else begin 58 1/1 unused_logic <= mubi_i; Tests: T1 T2 T3  59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 assign mubi_out = mubi_int; 83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00


55 if (!rst_ni) begin -1- 56 unused_logic <= MuBi4False; ==> 57 end else begin 58 unused_logic <= mubi_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 384864519 384030917 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384864519 384030917 0 0
T1 1636 1562 0 0
T2 1951 1876 0 0
T3 3382 3310 0 0
T7 4246 3594 0 0
T13 23710 23640 0 0
T14 6246 6148 0 0
T15 3415 3357 0 0
T18 2946 2862 0 0
T19 485911 467871 0 0
T20 70358 70281 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 1/1 assign mubi_int = mubi; Tests: T1 T2 T3  49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 1/1 if (!rst_ni) begin Tests: T1 T2 T3  56 1/1 unused_logic <= MuBi4False; Tests: T1 T2 T3  57 end else begin 58 1/1 unused_logic <= mubi_i; Tests: T1 T2 T3  59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 assign mubi_out = mubi_int; 83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00


55 if (!rst_ni) begin -1- 56 unused_logic <= MuBi4False; ==> 57 end else begin 58 unused_logic <= mubi_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 384864519 384030917 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384864519 384030917 0 0
T1 1636 1562 0 0
T2 1951 1876 0 0
T3 3382 3310 0 0
T7 4246 3594 0 0
T13 23710 23640 0 0
T14 6246 6148 0 0
T15 3415 3357 0 0
T18 2946 2862 0 0
T19 485911 467871 0 0
T20 70358 70281 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 1/1 assign mubi_int = mubi; Tests: T1 T2 T3  49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 1/1 if (!rst_ni) begin Tests: T1 T2 T3  56 1/1 unused_logic <= MuBi4False; Tests: T1 T2 T3  57 end else begin 58 1/1 unused_logic <= mubi_i; Tests: T1 T2 T3  59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 assign mubi_out = mubi_int; 83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00


55 if (!rst_ni) begin -1- 56 unused_logic <= MuBi4False; ==> 57 end else begin 58 unused_logic <= mubi_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 384864519 384030917 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384864519 384030917 0 0
T1 1636 1562 0 0
T2 1951 1876 0 0
T3 3382 3310 0 0
T7 4246 3594 0 0
T13 23710 23640 0 0
T14 6246 6148 0 0
T15 3415 3357 0 0
T18 2946 2862 0 0
T19 485911 467871 0 0
T20 70358 70281 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 1/1 assign mubi_int = mubi; Tests: T1 T2 T3  49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 1/1 if (!rst_ni) begin Tests: T1 T2 T3  56 1/1 unused_logic <= MuBi4False; Tests: T1 T2 T3  57 end else begin 58 1/1 unused_logic <= mubi_i; Tests: T1 T2 T3  59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 assign mubi_out = mubi_int; 83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00


55 if (!rst_ni) begin -1- 56 unused_logic <= MuBi4False; ==> 57 end else begin 58 unused_logic <= mubi_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 384864519 384030917 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384864519 384030917 0 0
T1 1636 1562 0 0
T2 1951 1876 0 0
T3 3382 3310 0 0
T7 4246 3594 0 0
T13 23710 23640 0 0
T14 6246 6148 0 0
T15 3415 3357 0 0
T18 2946 2862 0 0
T19 485911 467871 0 0
T20 70358 70281 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00

33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out; 34 1/1 assign mubi = MuBi4Width'(mubi_i); Tests: T1 T2 T3  35 36 // first generation block decides whether a flop should be present 37 if (AsyncOn) begin : gen_flops 38 prim_flop #( 39 .Width(MuBi4Width), 40 .ResetValue(MuBi4Width'(ResetValue)) 41 ) u_prim_flop ( 42 .clk_i, 43 .rst_ni, 44 .d_i ( mubi ), 45 .q_o ( mubi_int ) 46 ); 47 end else begin : gen_no_flops 48 1/1 assign mubi_int = mubi; Tests: T1 T2 T3  49 50 // This unused companion logic helps remove lint errors 51 // for modules where clock and reset are used for assertions only 52 // This logic will be removed for sythesis since it is unloaded. 53 mubi4_t unused_logic; 54 always_ff @(posedge clk_i or negedge rst_ni) begin 55 1/1 if (!rst_ni) begin Tests: T1 T2 T3  56 1/1 unused_logic <= MuBi4False; Tests: T1 T2 T3  57 end else begin 58 1/1 unused_logic <= mubi_i; Tests: T1 T2 T3  59 end 60 end 61 end 62 63 // second generation block determines output buffer type 64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block 65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer 66 // 3. If not EnSecBuf and AsyncOn -> feed through 67 if (EnSecBuf) begin : gen_sec_buf 68 prim_sec_anchor_buf #( 69 .Width(4) 70 ) u_prim_sec_buf ( 71 .in_i(mubi_int), 72 .out_o(mubi_out) 73 ); 74 end else if (!AsyncOn) begin : gen_prim_buf 75 prim_buf #( 76 .Width(4) 77 ) u_prim_buf ( 78 .in_i(mubi_int), 79 .out_o(mubi_out) 80 ); 81 end else begin : gen_feedthru 82 assign mubi_out = mubi_int; 83 end 84 85 1/1 assign mubi_o = mubi4_t'(mubi_out); Tests: T1 T2 T3 

Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00


55 if (!rst_ni) begin -1- 56 unused_logic <= MuBi4False; ==> 57 end else begin 58 unused_logic <= mubi_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 384864519 384030917 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 384864519 384030917 0 0
T1 1636 1562 0 0
T2 1951 1876 0 0
T3 3382 3310 0 0
T7 4246 3594 0 0
T13 23710 23640 0 0
T14 6246 6148 0 0
T15 3415 3357 0 0
T18 2946 2862 0 0
T19 485911 467871 0 0
T20 70358 70281 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%