Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.u_scramble.gen_gf_mult.u_mult

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.40 100.00 86.21 100.00 u_scramble


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_gf_mult
Line No.TotalCoveredPercent
TOTAL3030100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9700
ALWAYS10155100.00
ALWAYS11177100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12911100.00
ROUTINE13722100.00
ROUTINE14855100.00
ROUTINE16355100.00

81 // select current slice 82 1/1 assign reformat_data = operand_b_i; Tests: T1 T2 T3  83 1/1 assign op_i_slice = reformat_data[cnt]; Tests: T1 T2 T3  84 85 1/1 assign first = cnt == 0; Tests: T1 T2 T3  86 87 if (StagesPerCycle == Width) begin : gen_all_combo 88 89 assign ack_o = 1'b1; 90 assign cnt = '0; 91 assign prod_q = '0; 92 assign vector = '0; 93 94 end else begin : gen_decomposed 95 96 // multiply is done 97 unreachable assign ack_o = int'(cnt) == (Loops - 1); 98 99 // advance the stage count and also advance the bit position count 100 always_ff @(posedge clk_i or negedge rst_ni) begin 101 1/1 if (!rst_ni) begin Tests: T1 T2 T3  102 1/1 cnt <= '0; Tests: T1 T2 T3  103 1/1 end else if (req_i && ack_o) begin Tests: T1 T2 T3  104 unreachable cnt <= '0; 105 1/1 end else if (req_i && int'(cnt) < (Loops - 1)) begin Tests: T1 T2 T3  106 1/1 cnt <= cnt + 1'b1; Tests: T1 T2 T3  107 end MISSING_ELSE 108 end 109 110 always_ff @(posedge clk_i or negedge rst_ni) begin 111 1/1 if (!rst_ni) begin Tests: T1 T2 T3  112 1/1 prod_q <= '0; Tests: T1 T2 T3  113 1/1 vector <= '0; Tests: T1 T2 T3  114 1/1 end else if (ack_o) begin Tests: T1 T2 T3  115 unreachable prod_q <= '0; 116 unreachable vector <= '0; 117 1/1 end else if (req_i) begin Tests: T1 T2 T3  118 1/1 prod_q <= prod_d; Tests: T1 T2 T3  119 1/1 vector <= matrix[StagesPerCycle-1]; Tests: T1 T2 T3  120 end MISSING_ELSE 121 end 122 end 123 124 125 1/1 assign matrix = first ? gen_matrix(operand_a_i, 1'b1) : gen_matrix(vector, 1'b0); Tests: T1 T2 T3  126 1/1 assign prod_d = prod_q ^ gf_mult(matrix, op_i_slice); Tests: T1 T2 T3  127 128 // The output is not toggled until it is ready 129 1/1 assign prod_o = ack_o ? prod_d : operand_a_i; Tests: T1 T2 T3  130 131 132 // GF(2^Width) * x 133 function automatic logic [Width-1:0] gf_mult2( 134 logic [Width-1:0] operand 135 ); 136 logic [Width-1:0] mult_out; 137 1/1 mult_out = operand[Width-1] ? (operand << 1) ^ IPoly : (operand << 1); Tests: T1 T2 T3  138 1/1 return mult_out; Tests: T1 T2 T3  139 endfunction 140 141 // Matrix generate step 142 function automatic logic [StagesPerCycle-1:0][Width-1:0] gen_matrix( 143 logic [Width-1:0] seed, 144 logic init 145 ); 146 logic [StagesPerCycle-1:0][Width-1:0] matrix_out; 147 148 1/1 matrix_out[0] = init ? seed : gf_mult2(seed); Tests: T1 T2 T3  149 1/1 matrix_out[StagesPerCycle-1:1] = '0; Tests: T1 T2 T3  150 1/1 for (int i = 1; i < StagesPerCycle; i++) begin Tests: T1 T2 T3  151 1/1 matrix_out[i] = gf_mult2(matrix_out[i-1]); Tests: T1 T2 T3  152 end 153 1/1 return matrix_out; Tests: T1 T2 T3  154 endfunction 155 156 // Galois multiply step 157 function automatic logic [Width-1:0] gf_mult( 158 logic [StagesPerCycle-1:0][Width-1:0] matrix_, 159 logic [StagesPerCycle-1:0] operand 160 ); 161 logic [Width-1:0] mult_out; 162 logic [Width-1:0] add_vector; 163 1/1 mult_out = '0; Tests: T1 T2 T3  164 1/1 for (int i = 0; i < StagesPerCycle; i++) begin Tests: T1 T2 T3  165 1/1 add_vector = operand[i] ? matrix_[i] : '0; Tests: T1 T2 T3  166 1/1 mult_out = mult_out ^ add_vector; Tests: T1 T2 T3  167 end 168 1/1 return mult_out; Tests: T1 T2 T3 

Cond Coverage for Module : prim_gf_mult
TotalCoveredPercent
Conditions1515100.00
Logical1515100.00
Non-Logical00
Event00

 LINE       85
 EXPRESSION (cnt == 1'b0)
            ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       97
 EXPRESSION (int'(cnt) == (Loops - 1))
            -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1UnreachableT1,T2,T3

 LINE       103
 EXPRESSION (req_i && ack_o)
             --1--    --2--
-1--2-StatusTests
01UnreachableT82
10CoveredT1,T2,T3
11UnreachableT1,T2,T3

 LINE       105
 EXPRESSION (req_i && (int'(cnt) < (Loops - 1)))
             --1--    ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11CoveredT1,T2,T3

 LINE       125
 EXPRESSION (first ? prim_gf_mult.gen_matrix(operand_a_i, 1'b1) : prim_gf_mult.gen_matrix(vector, 1'b0))
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       129
 EXPRESSION (ack_o ? prod_d : operand_a_i)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1UnreachableT1,T2,T3

 LINE       137
 EXPRESSION (operand[(Width - 1)] ? (((operand << 1) ^ IPoly)) : ((operand << 1)))
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       148
 EXPRESSION (init ? seed : gf_mult2(seed))
             --1-
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       165
 EXPRESSION (operand[i] ? matrix_[i] : '0)
             -----1----
-1-StatusTests
0CoveredT1,T3,T13
1CoveredT1,T2,T3

Branch Coverage for Module : prim_gf_mult
Line No.TotalCoveredPercent
Branches 15 15 100.00
TERNARY 125 2 2 100.00
TERNARY 129 1 1 100.00
IF 101 3 3 100.00
IF 111 3 3 100.00
TERNARY 137 2 2 100.00
TERNARY 148 2 2 100.00
TERNARY 165 2 2 100.00


125 assign matrix = first ? gen_matrix(operand_a_i, 1'b1) : gen_matrix(vector, 1'b0); -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


129 assign prod_o = ack_o ? prod_d : operand_a_i; -1- ==> (Unreachable) ==>

Branches:
-1-StatusTests
1 Unreachable T1,T2,T3
0 Covered T1,T2,T3


101 if (!rst_ni) begin -1- 102 cnt <= '0; ==> 103 end else if (req_i && ack_o) begin -2- 104 cnt <= '0; ==> (Unreachable) 105 end else if (req_i && int'(cnt) < (Loops - 1)) begin -3- 106 cnt <= cnt + 1'b1; ==> 107 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Unreachable T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


111 if (!rst_ni) begin -1- 112 prod_q <= '0; ==> 113 vector <= '0; 114 end else if (ack_o) begin -2- 115 prod_q <= '0; ==> (Unreachable) 116 vector <= '0; 117 end else if (req_i) begin -3- 118 prod_q <= prod_d; ==> 119 vector <= matrix[StagesPerCycle-1]; 120 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Unreachable T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


137 mult_out = operand[Width-1] ? (operand << 1) ^ IPoly : (operand << 1); -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


148 matrix_out[0] = init ? seed : gf_mult2(seed); -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


165 add_vector = operand[i] ? matrix_[i] : '0; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T13


Assert Coverage for Module : prim_gf_mult
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntegerLoops_A 1042 1042 0 0
StagePow2_A 1042 1042 0 0


IntegerLoops_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

StagePow2_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%