Module Definition
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Module Instance : tb.dut.u_eflash.u_scramble

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.40 100.00 86.21 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00 100.00 93.94


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.56 97.67 86.00 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_gf_mult.u_mult 100.00 100.00 100.00 100.00 100.00
gen_prince.u_cipher 100.00 100.00
u_prim_arbiter_tree_calc 97.06 100.00 94.51 100.00 93.75
u_prim_arbiter_tree_op 95.40 100.00 87.85 100.00 93.75


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_phy_scramble
Line No.TotalCoveredPercent
TOTAL3838100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN5811100.00
CONT_ASSIGN5811100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10211100.00
ALWAYS11844100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN16611100.00
ALWAYS17344100.00
ALWAYS18933100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN23211100.00
CONT_ASSIGN23511100.00

42 // Inputs for GF mult 43 2/2 assign calc_req_banks[k] = scramble_req_i[k].calc_req; Tests: T1 T2 T3  | T1 T2 T3  44 2/2 assign calc_addr_in_banks[k] = scramble_req_i[k].addr; Tests: T1 T2 T3  | T1 T2 T3  45 // Outputs for GF mult 46 2/2 assign scramble_rsp_o[k].calc_ack = calc_ack_banks[k]; Tests: T1 T2 T3  | T4 T16 T10  47 2/2 assign scramble_rsp_o[k].mask = calc_mask; Tests: T1 T2 T3  | T1 T2 T3  48 49 50 // Inputs for scrambling primitive 51 2/2 assign op_req_banks[k] = scramble_req_i[k].op_req; Tests: T1 T2 T3  | T1 T2 T3  52 2/2 assign op_data_in_banks[k] = {scramble_req_i[k].op_type, Tests: T1 T2 T3  | T1 T2 T3  53 scramble_req_i[k].plain_data, 54 scramble_req_i[k].scrambled_data}; 55 // Outputs for scrambling primitive 56 2/2 assign scramble_rsp_o[k].op_ack = op_ack_banks[k]; Tests: T1 T2 T3  | T1 T2 T3  57 2/2 assign scramble_rsp_o[k].plain_data = plain_data_out; Tests: T1 T2 T3  | T1 T2 T3  58 2/2 assign scramble_rsp_o[k].scrambled_data = scrambled_data_out; Tests: T1 T2 T3  | T1 T2 T3  59 end 60 61 // SEC_CM: PHY_ARBITER.CTRL.REDUN 62 logic [NumBanks-1:0] local_err; 63 prim_arbiter_tree_dup #( 64 .N(NumBanks), 65 .DW(BankAddrW), 66 .EnDataPort(1) 67 ) u_prim_arbiter_tree_calc ( 68 .clk_i, 69 .rst_ni, 70 .req_chk_i(1'b1), 71 .req_i (calc_req_banks), 72 .data_i (calc_addr_in_banks), 73 .gnt_o (calc_ack_banks), 74 .idx_o (), 75 .valid_o (calc_req), 76 .data_o (calc_addr_in), 77 .ready_i (calc_ack), 78 .err_o (local_err[0]) 79 ); 80 81 // SEC_CM: PHY_ARBITER.CTRL.REDUN 82 prim_arbiter_tree_dup #( 83 .N(NumBanks), 84 .DW(OpDataWidth), 85 .EnDataPort(1) 86 ) u_prim_arbiter_tree_op ( 87 .clk_i, 88 .rst_ni, 89 .req_chk_i(1'b1), 90 .req_i (op_req_banks), 91 .data_i (op_data_in_banks), 92 .gnt_o (op_ack_banks), 93 .idx_o (), 94 .valid_o (op_req), 95 .data_o (op_data_in), 96 .ready_i (op_ack), 97 .err_o (local_err[1]) 98 ); 99 100 1/1 assign arb_err_o = |local_err; Tests: T1 T2 T3  101 102 1/1 assign {op_type, Tests: T1 T2 T3  103 plain_data_in, 104 scrambled_data_in} = op_data_in; 105 106 /////////////////////////// 107 // GF multiplier 108 /////////////////////////// 109 110 localparam int AddrPadWidth = DataWidth - BankAddrW; 111 localparam int UnusedWidth = KeySize - AddrPadWidth; 112 113 // unused portion of addr_key 114 logic [KeySize-1:0] muxed_addr_key; 115 116 logic addr_key_sel; 117 always_ff @(posedge clk_i or negedge rst_ni) begin 118 1/1 if (!rst_ni) begin Tests: T1 T2 T3  119 1/1 addr_key_sel <= '0; Tests: T1 T2 T3  120 1/1 end else if (!calc_req || calc_req && calc_ack) begin Tests: T1 T2 T3  121 1/1 addr_key_sel <= disable_i; Tests: T1 T2 T3  122 end MISSING_ELSE 123 end 124 125 1/1 assign muxed_addr_key = addr_key_sel ? rand_addr_key_i : addr_key_i; Tests: T1 T2 T3  126 127 logic [UnusedWidth-1:0] unused_key; 128 1/1 assign unused_key = muxed_addr_key[KeySize-1 -: UnusedWidth]; Tests: T1 T2 T3  129 130 // Galois Multiply portion 131 // Note: Degree of IPoly and width parameters must match (leading MSB of IPoly is dropped). 132 if (SecScrambleEn) begin : gen_gf_mult 133 prim_gf_mult # ( 134 .Width(DataWidth), 135 .StagesPerCycle(DataWidth / GfMultCycles), 136 .IPoly(ScrambleIPoly) 137 ) u_mult ( 138 .clk_i, 139 .rst_ni, 140 .req_i(calc_req), 141 .operand_a_i({muxed_addr_key[DataWidth +: AddrPadWidth], calc_addr_in}), 142 .operand_b_i(muxed_addr_key[DataWidth-1:0]), 143 .ack_o(calc_ack), 144 .prod_o(calc_mask) 145 ); 146 end else begin : gen_no_gf_mult 147 assign calc_mask = '0; 148 149 always_ff @(posedge clk_i or negedge rst_ni) begin 150 if (!rst_ni) begin 151 calc_ack <= '0; 152 end else if (calc_req && calc_ack) begin 153 calc_ack <= '0; 154 end else if (calc_req && !calc_ack) begin 155 calc_ack <= '1; 156 end 157 end 158 end 159 160 /////////////////////////// 161 // cipher 162 /////////////////////////// 163 164 logic dec; 165 logic [DataWidth-1:0] data; 166 1/1 assign dec = op_type == DeScrambleOp; Tests: T1 T2 T3  167 168 // Do not allow the key to change during a transaction. 169 // While this may be desirable for security reasons, it creates 170 // timing issues for physical design 171 logic data_key_sel; 172 always_ff @(posedge clk_i or negedge rst_ni) begin 173 1/1 if (!rst_ni) begin Tests: T1 T2 T3  174 1/1 data_key_sel <= '0; Tests: T1 T2 T3  175 1/1 end else if (!op_req || op_req && op_ack) begin Tests: T1 T2 T3  176 1/1 data_key_sel <= disable_i; Tests: T1 T2 T3  177 end MISSING_ELSE 178 end 179 180 // the prim_prince valid_o is a flopped version of valid_i 181 // As a result, when op_req stays high due to multiple transactions 182 // in-flight, the receiving logic can misinterpret the 'ack' if we just 183 // tie it to valid_o. 184 // Add a little bit of shimming logic here to properly create the ack 185 logic cipher_valid_in_d, cipher_valid_in_q; 186 logic cipher_valid_out; 187 188 always_ff @(posedge clk_i or negedge rst_ni) begin 189 1/1 if (!rst_ni) begin Tests: T1 T2 T3  190 1/1 cipher_valid_in_q <= '0; Tests: T1 T2 T3  191 end else begin 192 1/1 cipher_valid_in_q <= cipher_valid_in_d; Tests: T1 T2 T3  193 end 194 end 195 196 1/1 assign cipher_valid_in_d = op_ack ? '0 : op_req & !cipher_valid_out; Tests: T1 T2 T3  197 1/1 assign op_ack = cipher_valid_in_q & cipher_valid_out; Tests: T1 T2 T3  198 199 if (SecScrambleEn) begin : gen_prince 200 prim_prince # ( 201 .DataWidth(DataWidth), 202 .KeyWidth(KeySize), 203 // Use improved key schedule proposed by https://eprint.iacr.org/2014/656.pdf (see appendix). 204 .UseOldKeySched(1'b0), 205 .HalfwayDataReg(1'b1), 206 // No key register is needed half way, since the data_key_i and operation op_type inputs 207 // remain constant until one data block has been processed. 208 .HalfwayKeyReg (1'b0) 209 ) u_cipher ( 210 .clk_i, 211 .rst_ni, 212 .valid_i(cipher_valid_in_d), 213 .data_i(dec ? scrambled_data_in : plain_data_in), 214 .key_i(data_key_sel ? rand_data_key_i : data_key_i), 215 .dec_i(dec), 216 .data_o(data), 217 .valid_o(cipher_valid_out) 218 ); 219 220 end else begin : gen_no_prince 221 always_ff @(posedge clk_i or negedge rst_ni) begin 222 if (!rst_ni) begin 223 cipher_valid_out <= '0; 224 end else begin 225 cipher_valid_out <= cipher_valid_in_d; 226 end 227 end 228 assign data = dec ? scrambled_data_in : plain_data_in; 229 end 230 231 // if decrypt, output the unscrambled data, feed input through otherwise 232 1/1 assign plain_data_out = dec ? data : scrambled_data_in; Tests: T1 T2 T3  233 234 // if encrypt, output the scrambled data, feed input through otherwise 235 1/1 assign scrambled_data_out = dec ? plain_data_in : data; Tests: T1 T2 T3 

Cond Coverage for Module : flash_phy_scramble
TotalCoveredPercent
Conditions292586.21
Logical292586.21
Non-Logical00
Event00

 LINE       120
 EXPRESSION (((!calc_req)) || (calc_req && calc_ack))
             ------1------    -----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01UnreachableT1,T2,T3
10CoveredT1,T2,T3

 LINE       120
 SUB-EXPRESSION (calc_req && calc_ack)
                 ----1---    ----2---
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11UnreachableT1,T2,T3

 LINE       125
 EXPRESSION (addr_key_sel ? rand_addr_key_i : addr_key_i)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       166
 EXPRESSION (op_type == DeScrambleOp)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       175
 EXPRESSION (((!op_req)) || (op_req && op_ack))
             -----1-----    ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       175
 SUB-EXPRESSION (op_req && op_ack)
                 ---1--    ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       196
 EXPRESSION (op_ack ? '0 : (op_req & ((!cipher_valid_out))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       196
 SUB-EXPRESSION (op_req & ((!cipher_valid_out)))
                 ---1--   ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       197
 EXPRESSION (cipher_valid_in_q & cipher_valid_out)
             --------1--------   --------2-------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

 LINE       209
 EXPRESSION (dec ? scrambled_data_in : plain_data_in)
             -1-
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T3

 LINE       209
 EXPRESSION (data_key_sel ? rand_data_key_i : data_key_i)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       232
 EXPRESSION (dec ? data : scrambled_data_in)
             -1-
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T3

 LINE       235
 EXPRESSION (dec ? plain_data_in : data)
             -1-
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T3

Branch Coverage for Module : flash_phy_scramble
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 125 2 2 100.00
TERNARY 196 2 2 100.00
TERNARY 232 2 2 100.00
TERNARY 235 2 2 100.00
TERNARY 209 2 2 100.00
TERNARY 209 2 2 100.00
IF 118 3 3 100.00
IF 173 3 3 100.00
IF 189 2 2 100.00


125 assign muxed_addr_key = addr_key_sel ? rand_addr_key_i : addr_key_i; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


196 assign cipher_valid_in_d = op_ack ? '0 : op_req & !cipher_valid_out; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


232 assign plain_data_out = dec ? data : scrambled_data_in; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T4,T5


235 assign scrambled_data_out = dec ? plain_data_in : data; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T4,T5


209 ) u_cipher ( 210 .clk_i, 211 .rst_ni, 212 .valid_i(cipher_valid_in_d), 213 .data_i(dec ? scrambled_data_in : plain_data_in), -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T4,T5


209 ) u_cipher ( 210 .clk_i, 211 .rst_ni, 212 .valid_i(cipher_valid_in_d), 213 .data_i(dec ? scrambled_data_in : plain_data_in), -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


118 if (!rst_ni) begin -1- 119 addr_key_sel <= '0; ==> 120 end else if (!calc_req || calc_req && calc_ack) begin -2- 121 addr_key_sel <= disable_i; ==> 122 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


173 if (!rst_ni) begin -1- 174 data_key_sel <= '0; ==> 175 end else if (!op_req || op_req && op_ack) begin -2- 176 data_key_sel <= disable_i; ==> 177 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


189 if (!rst_ni) begin -1- 190 cipher_valid_in_q <= '0; ==> 191 end else begin 192 cipher_valid_in_q <= cipher_valid_in_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3