Line Coverage for Module :
flash_phy
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 43 | 42 | 97.67 |
| CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 129 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 133 | 0 | 0 | |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 143 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 178 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 178 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 178 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 178 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 178 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 178 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 178 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 178 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 178 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 199 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 201 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 230 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 230 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 254 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 254 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 255 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 255 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 333 | 0 | 0 | |
| CONT_ASSIGN | 349 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 389 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 392 | 1 | 0 | 0.00 |
120 // select which bank each is operating on
121 1/1 assign host_bank_sel = host_req_i ? host_addr_i[BusAddrW-1 -: BankW] : '0;
Tests: T1 T2 T3
122 1/1 assign ctrl_bank_sel = flash_ctrl_i.addr[BusAddrW-1 -: BankW];
Tests: T1 T2 T3
123
124 // accept transaction if bank is ready and previous response NOT pending
125 1/1 assign host_req_rdy_o = host_req_rdy[host_bank_sel] & host_rsp_avail[host_bank_sel] &
Tests: T1 T2 T3
126 seq_fifo_rdy;
127
128 1/1 assign host_req_done_o = seq_fifo_pending & host_rsp_vld[rsp_bank_sel];
Tests: T1 T2 T3
129 1/1 assign host_rderr_o = host_rsp_err[rsp_bank_sel];
Tests: T1 T2 T3
130 1/1 assign host_rdata_o = host_rsp_data[rsp_bank_sel];
Tests: T1 T2 T3
131
132 // all banks are assumed to be the same in terms of prog_type support
133 unreachable assign flash_ctrl_o.prog_type_avail = prog_type_avail;
134 1/1 assign flash_ctrl_o.rd_done = rd_done[ctrl_bank_sel];
Tests: T1 T2 T3
135 1/1 assign flash_ctrl_o.prog_done = prog_done[ctrl_bank_sel];
Tests: T1 T2 T3
136 1/1 assign flash_ctrl_o.erase_done = erase_done[ctrl_bank_sel];
Tests: T1 T2 T3
137 1/1 assign flash_ctrl_o.rd_data = rd_data_ctrl[ctrl_bank_sel];
Tests: T1 T2 T3
138 1/1 assign flash_ctrl_o.rd_err = rd_err[ctrl_bank_sel];
Tests: T1 T2 T3
139 1/1 assign flash_ctrl_o.init_busy = init_busy;
Tests: T1 T2 T3
140 1/1 assign flash_ctrl_o.prog_intg_err = |prog_intg_err;
Tests: T1 T2 T3
141 1/1 assign flash_ctrl_o.storage_relbl_err = |relbl_ecc_err;
Tests: T1 T2 T3
142 1/1 assign flash_ctrl_o.storage_intg_err = |intg_ecc_err;
Tests: T1 T2 T3
143 1/1 assign flash_ctrl_o.fsm_err = |fsm_err;
Tests: T1 T2 T3
144 1/1 assign flash_ctrl_o.spurious_ack = |spurious_acks;
Tests: T1 T2 T3
145 1/1 assign flash_ctrl_o.arb_err = |arb_err | scramble_arb_err;
Tests: T1 T2 T3
146 1/1 assign flash_ctrl_o.host_gnt_err = |{host_gnt_err, cnt_err} ;
Tests: T1 T2 T3
147 1/1 assign flash_ctrl_o.fifo_err = |{rsp_fifo_err, core_fifo_err};
Tests: T1 T2 T3
148
149
150 // This fifo holds the expected return order
151 prim_fifo_sync #(
152 .Width (BankW),
153 .Pass (0),
154 .Depth (SeqFifoDepth)
155 ) u_bank_sequence_fifo (
156 .clk_i,
157 .rst_ni,
158 .clr_i (1'b0),
159 .wvalid_i(host_req_i & host_req_rdy_o),
160 .wready_o(seq_fifo_rdy),
161 .wdata_i (host_bank_sel),
162 .depth_o (),
163 .full_o (),
164 .rvalid_o(seq_fifo_pending),
165 .rready_i(host_req_done_o),
166 .rdata_o (rsp_bank_sel),
167 .err_o ()
168 );
169
170 // Generate host scramble_en indication, broadcasted to all banks
171 localparam int TotalRegions = MpRegions + 1;
172 logic host_scramble_en, host_ecc_en;
173 data_region_attr_t region_attrs [TotalRegions];
174 mp_region_cfg_t region_cfg, unused_cfg;
175
176 for(genvar i = 0; i < TotalRegions; i++) begin : gen_region_attrs
177 assign region_attrs[i].phase = PhaseInvalid;
178 9/9 assign region_attrs[i].cfg = flash_ctrl_i.region_cfgs[i];
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
179 end
180
181 // the region decode only accepts page address
182 flash_mp_data_region_sel #(
183 .Regions(TotalRegions)
184 ) u_region_sel (
185 .req_i(host_req_i),
186 .phase_i(PhaseInvalid),
187 .addr_i(host_addr_i[BusAddrW-1 -: AllPagesW]),
188 .region_attrs_i(region_attrs),
189 .sel_cfg_o(region_cfg)
190 );
191
192 // most attributes are unused
193 1/1 assign unused_cfg = region_cfg;
Tests: T1 T2 T4
194
195 // only scramble/ecc attributes are looked at
196 import prim_mubi_pkg::mubi4_test_true_strict;
197 import prim_mubi_pkg::mubi4_and_hi;
198
199 1/1 assign host_scramble_en = mubi4_test_true_strict(
Tests: T1 T2 T4
200 mubi4_and_hi(region_cfg.scramble_en, region_cfg.en));
201 1/1 assign host_ecc_en = mubi4_test_true_strict(mubi4_and_hi(region_cfg.ecc_en, region_cfg.en));
Tests: T1 T2 T4
202
203 // Prim flash to flash_phy_core connections
204 flash_phy_pkg::scramble_req_t [NumBanks-1:0] scramble_req;
205 flash_phy_pkg::scramble_rsp_t [NumBanks-1:0] scramble_rsp;
206 flash_phy_pkg::flash_phy_prim_flash_req_t [NumBanks-1:0] prim_flash_req;
207 flash_phy_pkg::flash_phy_prim_flash_rsp_t [NumBanks-1:0] prim_flash_rsp;
208 logic [NumBanks-1:0] ecc_single_err;
209 logic [NumBanks-1:0][BusAddrW-1:0] ecc_addr;
210
211 1/1 assign flash_ctrl_o.ecc_single_err = ecc_single_err;
Tests: T1 T2 T3
212 1/1 assign flash_ctrl_o.ecc_addr = ecc_addr;
Tests: T1 T2 T3
213
214 // One extra copy for the flash scrambling module.
215 mubi4_t [NumBanks:0] flash_disable;
216 prim_mubi4_sync #(
217 .NumCopies(NumBanks+1),
218 .AsyncOn(0)
219 ) u_disable_buf (
220 .clk_i,
221 .rst_ni,
222 .mubi_i(flash_ctrl_i.flash_disable),
223 .mubi_o(flash_disable)
224 );
225
226
227 for (genvar bank = 0; bank < NumBanks; bank++) begin : gen_flash_cores
228
229 // pop if the response came from the appropriate fifo
230 2/2 assign host_rsp_ack[bank] = host_req_done_o & (rsp_bank_sel == bank);
Tests: T1 T2 T3 | T1 T2 T3
231
232 prim_fifo_sync #(
233 .Width (BusFullWidth + 1),
234 .Pass (1'b1),
235 .Depth (FlashMacroOustanding),
236 .Secure (1'b1) // SEC_CM: FIFO.CTR.REDUN
237 ) u_host_rsp_fifo (
238 .clk_i,
239 .rst_ni,
240 .clr_i (1'b0),
241 .wvalid_i(host_req_done[bank]),
242 .wready_o(host_rsp_avail[bank]),
243 .wdata_i ({rd_err[bank], rd_data_host[bank]}),
244 .depth_o (),
245 .full_o (),
246 .rvalid_o(host_rsp_vld[bank]),
247 .rready_i(host_rsp_ack[bank]),
248 .rdata_o ({host_rsp_err[bank], host_rsp_data[bank]}),
249 .err_o (rsp_fifo_err[bank])
250 );
251
252 logic host_req;
253 logic ctrl_req;
254 2/2 assign host_req = host_req_i & (host_bank_sel == bank) & host_rsp_avail[bank];
Tests: T1 T2 T3 | T1 T2 T3
255 2/2 assign ctrl_req = flash_ctrl_i.req & (ctrl_bank_sel == bank);
Tests: T1 T2 T3 | T1 T2 T3
256 assign ecc_addr[bank][BusBankAddrW +: BankW] = bank;
257
258 flash_phy_core u_core (
259 .clk_i,
260 .rst_ni,
261 // integrity error is either from host or from controller
262 .req_i(ctrl_req),
263 .scramble_en_i(flash_ctrl_i.scramble_en),
264 .ecc_en_i(flash_ctrl_i.ecc_en),
265 .he_en_i(flash_ctrl_i.he_en),
266 // host request must be suppressed if response fifo cannot hold more
267 // otherwise the flash_phy_core and flash_phy will get out of sync
268 .host_req_i(host_req),
269 .host_scramble_en_i(host_scramble_en),
270 .host_ecc_en_i(host_ecc_en),
271 .host_addr_i(host_addr_i[0 +: BusBankAddrW]),
272 .rd_i(flash_ctrl_i.rd),
273 .prog_i(flash_ctrl_i.prog),
274 .pg_erase_i(flash_ctrl_i.pg_erase),
275 .bk_erase_i(flash_ctrl_i.bk_erase),
276 .erase_suspend_req_i(flash_ctrl_i.erase_suspend),
277 .part_i(flash_ctrl_i.part),
278 .info_sel_i(flash_ctrl_i.info_sel),
279 .addr_i(flash_ctrl_i.addr[0 +: BusBankAddrW]),
280 .prog_data_i(flash_ctrl_i.prog_data),
281 .prog_last_i(flash_ctrl_i.prog_last),
282 .prog_type_i(flash_ctrl_i.prog_type),
283 .rd_buf_en_i(flash_ctrl_i.rd_buf_en),
284 .host_req_rdy_o(host_req_rdy[bank]),
285 .host_req_done_o(host_req_done[bank]),
286 .rd_done_o(rd_done[bank]),
287 .prog_done_o(prog_done[bank]),
288 .erase_done_o(erase_done[bank]),
289 .rd_data_host_o(rd_data_host[bank]),
290 .rd_data_ctrl_o(rd_data_ctrl[bank]),
291 .rd_err_o(rd_err[bank]),
292 .flash_disable_i(flash_disable[bank]),
293 .scramble_req_o(scramble_req[bank]),
294 .scramble_rsp_i(scramble_rsp[bank]),
295 .prim_flash_req_o(prim_flash_req[bank]),
296 .prim_flash_rsp_i(prim_flash_rsp[bank]),
297 .ecc_single_err_o(ecc_single_err[bank]),
298 .ecc_addr_o(ecc_addr[bank][BusBankAddrW-1:0]),
299 .fsm_err_o(fsm_err[bank]),
300 .prog_intg_err_o(prog_intg_err[bank]),
301 .relbl_ecc_err_o(relbl_ecc_err[bank]),
302 .intg_ecc_err_o(intg_ecc_err[bank]),
303 .spurious_ack_o(spurious_acks[bank]),
304 .arb_err_o(arb_err[bank]),
305 .host_gnt_err_o(host_gnt_err[bank]),
306 .fifo_err_o(core_fifo_err[bank]),
307 .cnt_err_o(cnt_err[bank])
308 );
309 end // block: gen_flash_banks
310
311 // shared scrambling module
312 // SEC_CM: MEM.SCRAMBLE
313 flash_phy_scramble #(
314 .SecScrambleEn(SecScrambleEn)
315 ) u_scramble (
316 .clk_i,
317 .rst_ni,
318 // both escalation and integrity error cause the scramble keys to change
319 .disable_i(prim_mubi_pkg::mubi4_test_true_loose(flash_disable[NumBanks])),
320 .addr_key_i(flash_ctrl_i.addr_key),
321 .data_key_i(flash_ctrl_i.data_key),
322 .rand_addr_key_i(flash_ctrl_i.rand_addr_key),
323 .rand_data_key_i(flash_ctrl_i.rand_data_key),
324 .scramble_req_i(scramble_req),
325 .scramble_rsp_o(scramble_rsp),
326 .arb_err_o(scramble_arb_err) // fatal error from redundant arbiter logic
327 );
328
329 // life cycle handling
330 logic tdo;
331 lc_ctrl_pkg::lc_tx_t [FlashLcDftLast-1:0] lc_nvm_debug_en;
332
333 unreachable assign flash_ctrl_o.jtag_rsp.tdo = tdo &
334 lc_ctrl_pkg::lc_tx_test_true_strict(lc_nvm_debug_en[FlashLcTdoSel]);
335
336 prim_lc_sync #(
337 .NumCopies(int'(FlashLcDftLast))
338 ) u_lc_nvm_debug_en_sync (
339 .clk_i,
340 .rst_ni,
341 .lc_en_i(lc_nvm_debug_en_i),
342 .lc_en_o(lc_nvm_debug_en)
343 );
344
345 import lc_ctrl_pkg::lc_tx_test_true_strict;
346 // if nvm debug is enabled, flash_bist_enable controls entry to flash test mode.
347 // if nvm debug is disabled, flash_bist_enable is always turned off.
348 mubi4_t bist_enable_qual;
349 1/1 assign bist_enable_qual = (lc_tx_test_true_strict(lc_nvm_debug_en[FlashBistSel])) ?
Tests: T1 T2 T3
350 flash_bist_enable_i :
351 MuBi4False;
352
353 prim_flash #(
354 .NumBanks(NumBanks),
355 .InfosPerBank(InfosPerBank),
356 .InfoTypes(InfoTypes),
357 .InfoTypesWidth(InfoTypesWidth),
358 .PagesPerBank(PagesPerBank),
359 .WordsPerPage(WordsPerPage),
360 .DataWidth(flash_phy_pkg::FullDataWidth)
361 ) u_flash (
362 .clk_i,
363 .rst_ni,
364 .tl_i,
365 .tl_o,
366 .flash_req_i(prim_flash_req),
367 .flash_rsp_o(prim_flash_rsp),
368 .prog_type_avail_o(prog_type_avail),
369 .init_busy_o(init_busy),
370 .tck_i(flash_ctrl_i.jtag_req.tck & lc_tx_test_true_strict(lc_nvm_debug_en[FlashLcTckSel])),
371 .tdi_i(flash_ctrl_i.jtag_req.tdi & lc_tx_test_true_strict(lc_nvm_debug_en[FlashLcTdiSel])),
372 .tms_i(flash_ctrl_i.jtag_req.tms & lc_tx_test_true_strict(lc_nvm_debug_en[FlashLcTmsSel])),
373 .tdo_o(tdo),
374 .bist_enable_i(bist_enable_qual),
375 .obs_ctrl_i,
376 .fla_obs_o,
377 .scanmode_i,
378 .scan_en_i,
379 .scan_rst_ni,
380 .flash_power_ready_h_i,
381 .flash_power_down_h_i,
382 .flash_test_mode_a_io,
383 .flash_test_voltage_h_io,
384 .flash_err_o(flash_ctrl_o.macro_err),
385 .fatal_alert_o(fatal_prim_flash_alert_o),
386 .recov_alert_o(recov_prim_flash_alert_o)
387 );
388 logic unused_alert;
389 1/1 assign unused_alert = flash_ctrl_i.alert_trig & flash_ctrl_i.alert_ack;
Tests: T1 T2 T3
390
391 logic unused_trst_n;
392 0/1 ==> assign unused_trst_n = flash_ctrl_i.jtag_req.trst_n;
Cond Coverage for Module :
flash_phy
| Total | Covered | Percent |
|---|
| Conditions | 50 | 43 | 86.00 |
| Logical | 50 | 43 | 86.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 121
EXPRESSION (host_req_i ? host_addr_i[(flash_ctrl_pkg::BusAddrW - 1)-:flash_ctrl_pkg::BankW] : '0)
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T8,T6,T20 |
LINE 125
EXPRESSION (host_req_rdy[host_bank_sel] & host_rsp_avail[host_bank_sel] & seq_fifo_rdy)
-------------1------------- --------------2-------------- ------3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Not Covered | |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T8,T6,T20 |
LINE 128
EXPRESSION (seq_fifo_pending & host_rsp_vld[rsp_bank_sel])
--------1------- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T14,T72 |
| 1 | 0 | Covered | T8,T6,T20 |
| 1 | 1 | Covered | T8,T6,T20 |
LINE 145
EXPRESSION (((|arb_err)) | scramble_arb_err)
------1----- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T19 |
| 1 | 0 | Covered | T103,T104,T105 |
LINE 155
EXPRESSION (host_req_i & host_req_rdy_o)
-----1---- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T10,T11,T34 |
| 1 | 1 | Covered | T8,T6,T20 |
LINE 230
EXPRESSION (host_req_done_o & (rsp_bank_sel == 0))
-------1------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T8,T10,T11 |
| 1 | 1 | Covered | T8,T6,T20 |
LINE 230
SUB-EXPRESSION (rsp_bank_sel == 0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 230
EXPRESSION (host_req_done_o & (rsp_bank_sel == 1))
-------1------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T8,T10,T11 |
| 1 | 0 | Covered | T8,T6,T20 |
| 1 | 1 | Covered | T8,T10,T11 |
LINE 230
SUB-EXPRESSION (rsp_bank_sel == 1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T8,T10,T11 |
LINE 254
EXPRESSION (host_req_i & (host_bank_sel == 0) & host_rsp_avail[0])
-----1---- ----------2--------- --------3--------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T8,T10,T11 |
| 1 | 1 | 0 | Covered | T74,T106,T103 |
| 1 | 1 | 1 | Covered | T8,T6,T20 |
LINE 254
SUB-EXPRESSION (host_bank_sel == 0)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T4 |
| 1 | Covered | T1,T2,T3 |
LINE 254
EXPRESSION (host_req_i & (host_bank_sel == 1) & host_rsp_avail[1])
-----1---- ----------2--------- --------3--------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Not Covered | |
| 1 | 0 | 1 | Covered | T8,T6,T20 |
| 1 | 1 | 0 | Covered | T19,T51,T107 |
| 1 | 1 | 1 | Covered | T8,T10,T11 |
LINE 254
SUB-EXPRESSION (host_bank_sel == 1)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T8,T10,T11 |
LINE 255
EXPRESSION (flash_ctrl_i.req & (ctrl_bank_sel == 0))
--------1------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T16,T8 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 255
SUB-EXPRESSION (ctrl_bank_sel == 0)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 255
EXPRESSION (flash_ctrl_i.req & (ctrl_bank_sel == 1))
--------1------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T16,T8 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T4,T16,T8 |
LINE 255
SUB-EXPRESSION (ctrl_bank_sel == 1)
----------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T16,T8 |
LINE 389
EXPRESSION (flash_ctrl_i.alert_trig & flash_ctrl_i.alert_ack)
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
Branch Coverage for Module :
flash_phy
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
121 |
2 |
2 |
100.00 |
121 assign host_bank_sel = host_req_i ? host_addr_i[BusAddrW-1 -: BankW] : '0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T8,T6,T20 |
| 0 |
Covered |
T1,T2,T3 |