Unified Coverage Report :: Module :: prim_generic_flash_bank

Module : prim_generic_flash_bank

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.55	96.48	92.86		93.75	91.11

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank	93.55	96.48	92.86		93.75	91.11
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank	93.55	96.48	92.86		93.75	91.11

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.55	96.48	92.86		93.75	91.11

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.67	96.04	90.48		93.75	93.10	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	80.00						gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_info_types[0].u_info_mem	95.24	85.71				100.00	100.00
gen_info_types[1].u_info_mem	95.24	85.71				100.00	100.00
gen_info_types[2].u_info_mem	95.24	85.71				100.00	100.00
u_cmd_fifo	97.22	100.00	88.89			100.00	100.00
u_mem	95.24	85.71				100.00	100.00
u_phy_cov_if	89.51	100.00	85.19			83.33

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.55	96.48	92.86		93.75	91.11

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.67	96.04	90.48		93.75	93.10	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	80.00						gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_info_types[0].u_info_mem	95.24	85.71				100.00	100.00
gen_info_types[1].u_info_mem	95.24	85.71				100.00	100.00
gen_info_types[2].u_info_mem	95.24	85.71				100.00	100.00
u_cmd_fifo	97.22	100.00	88.89			100.00	100.00
u_mem	95.24	85.71				100.00	100.00
u_phy_cov_if	89.51	100.00	85.19			83.33

Line Coverage for Module : prim_generic_flash_bank

	Line No.	Total	Covered	Percent
TOTAL		142	137	96.48
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	181	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
ALWAYS	189	3	3	100.00
ALWAYS	194	9	9	100.00
ALWAYS	210	4	4	100.00
ALWAYS	221	6	6	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	236	13	12	92.31
ALWAYS	251	86	82	95.35
CONT_ASSIGN	402	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	453	1	1	100.00

126                     
127        1/1            assign cmd_d = '{
           Tests:       T1 T2 T3 
128                         rd :       rd_i,
129                         prog:      prog_i,
130                         prog_last: prog_last_i,
131                         prog_type: prog_type_i,
132                         pg_erase:  pg_erase_i,
133                         bk_erase:  bk_erase_i,
134                         addr:      addr_i,
135                         part:      part_i,
136                         info_sel:  info_sel_i,
137                         prog_data: prog_data_i
138                       };
139                     
140                       // for read transactions, in order to reduce latency, the
141                       // command fifo is popped early (before done_o).  This is to ensure that when
142                       // the current transaction is complete, during the same cycle
143                       // a new read can be issued. As a result, the command is popped
144                       // immediately after the read is issued, rather than waiting for
145                       // the read to be completed.  The same restrictions are not necessary
146                       // for program / erase, which do not have the same performance
147                       // requirements.
148                     
149                       // when the flash is going through init, do not accept any transactions
150                       logic wvalid;
151                       logic ack;
152        1/1            assign wvalid = (rd_i | prog_i | pg_erase_i | bk_erase_i) & !init_busy_o;
           Tests:       T1 T2 T3 
153        1/1            assign ack_o = ack & !init_busy_o;
           Tests:       T1 T2 T3 
154                     
155                       prim_fifo_sync #(
156                         .Width   ($bits(cmd_payload_t)),
157                         .Pass    (0),
158                         .Depth   (2)
159                       ) u_cmd_fifo (
160                         .clk_i,
161                         .rst_ni,
162                         .clr_i   (1'b0),
163                         .wvalid_i(wvalid),
164                         .wready_o(ack),
165                         .wdata_i (cmd_d),
166                         .depth_o (),
167                         .full_o (),
168                         .rvalid_o(cmd_valid),
169                         .rready_i(pop_cmd),
170                         .rdata_o (cmd_q),
171                         .err_o   ()
172                       );
173                     
174                       logic rd_req, prog_req, pg_erase_req, bk_erase_req;
175        1/1            assign rd_req = cmd_valid & cmd_q.rd;
           Tests:       T1 T2 T3 
176        1/1            assign prog_req = cmd_valid & cmd_q.prog;
           Tests:       T1 T2 T3 
177        1/1            assign pg_erase_req = cmd_valid & cmd_q.pg_erase;
           Tests:       T1 T2 T3 
178        1/1            assign bk_erase_req = cmd_valid & cmd_q.bk_erase;
           Tests:       T1 T2 T3 
179                     
180                       // for read / program operations, the index cnt should be 0
181        1/1            assign mem_rd_d = mem_req & ~mem_wr;
           Tests:       T1 T2 T3 
182        1/1            assign mem_addr = cmd_q.addr + index_cnt[AddrW-1:0];
           Tests:       T1 T2 T3 
183        1/1            assign mem_part = cmd_q.part;
           Tests:       T1 T2 T3 
184        1/1            assign mem_bk_erase = cmd_q.bk_erase;
           Tests:       T1 T2 T3 
185                     
186        1/1            assign mem_info_sel = cmd_q.info_sel;
           Tests:       T1 T2 T3 
187                     
188                       always_ff @(posedge clk_i or negedge rst_ni) begin
189        2/2              if (!rst_ni) st_q <= StReset;
           Tests:       T1 T2 T3  | T1 T2 T3 
190        1/1              else st_q <= st_d;
           Tests:       T1 T2 T3 
191                       end
192                     
193                       always_ff @(posedge clk_i or negedge rst_ni) begin
194        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
195        1/1                time_limit_q  <= 'h0;
           Tests:       T1 T2 T3 
196        1/1                index_limit_q <= 'h0;
           Tests:       T1 T2 T3 
197        1/1                prog_pend_q   <= 'h0;
           Tests:       T1 T2 T3 
198        1/1                mem_rd_q      <= 'h0;
           Tests:       T1 T2 T3 
199                         end else begin
200        1/1                time_limit_q  <= time_limit_d;
           Tests:       T1 T2 T3 
201        1/1                index_limit_q <= index_limit_d;
           Tests:       T1 T2 T3 
202        1/1                prog_pend_q   <= prog_pend_d;
           Tests:       T1 T2 T3 
203        1/1                mem_rd_q      <= mem_rd_d;
           Tests:       T1 T2 T3 
204                         end
205                       end
206                     
207                       // latch read data from emulated memories the cycle after a read
208                       logic [DataWidth-1:0] rd_data_q, rd_data_d;
209                       always_ff @(posedge clk_i or negedge rst_ni) begin
210        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
211        1/1                rd_data_q <= '0;
           Tests:       T1 T2 T3 
212        1/1              end else if (mem_rd_q) begin
           Tests:       T1 T2 T3 
213        1/1                rd_data_q <= rd_data_d;
           Tests:       T1 T2 T3 
214                         end
                        MISSING_ELSE
215                       end
216                     
217                       // latch partiton being read since the command fifo is popped early
218                       flash_ctrl_pkg::flash_part_e rd_part_q;
219                       logic [InfoTypesWidth-1:0] info_sel_q;
220                       always_ff @(posedge clk_i or negedge rst_ni) begin
221        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
222        1/1                rd_part_q <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
223        1/1                info_sel_q <= '0;
           Tests:       T1 T2 T3 
224        1/1              end else if (mem_rd_d) begin
           Tests:       T1 T2 T3 
225        1/1                rd_part_q <= cmd_q.part;
           Tests:       T1 T2 T3 
226        1/1                info_sel_q <= cmd_q.info_sel;
           Tests:       T1 T2 T3 
227                         end
                        MISSING_ELSE
228                       end
229                     
230                       // if read cycle is only 1, we can expose the unlatched data directly
231        1/1            assign rd_data_o = ReadLatency == 1 ? rd_data_d : rd_data_q;
           Tests:       T1 T2 T3 
232                     
233                       // prog_pend_q is necessary to emulate flash behavior that a bit written to 0 cannot be written
234                       // back to 1 without an erase
235                       always_ff @(posedge clk_i or negedge rst_ni) begin
236        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
237        1/1                time_cnt  <= 'h0;
           Tests:       T1 T2 T3 
238        1/1                index_cnt <= 'h0;
           Tests:       T1 T2 T3 
239                         end else begin
240        2/2                if (time_cnt_inc) time_cnt <= time_cnt + 1'b1;
           Tests:       T1 T2 T3  | T1 T2 T3 
241        1/2     ==>        else if (time_cnt_set1) time_cnt <= 32'h1;
           Tests:       T1 T2 T3 
242        2/2                else if (time_cnt_clr) time_cnt <= 32'h0;
           Tests:       T1 T2 T3  | T1 T2 T3 
                        MISSING_ELSE
243                     
244        2/2                if (index_cnt_inc) index_cnt <= index_cnt + 1'b1;
           Tests:       T1 T2 T3  | T1 T2 T3 
245        2/2                else if (index_cnt_clr) index_cnt <= 32'h0;
           Tests:       T1 T2 T3  | T1 T2 T3 
                        MISSING_ELSE
246                         end
247                       end
248                     
249                       always_comb begin
250                         // state
251        1/1              st_d             = st_q;
           Tests:       T1 T2 T3 
252                     
253                         // internally consumed signals
254        1/1              index_limit_d    = index_limit_q;
           Tests:       T1 T2 T3 
255        1/1              time_limit_d     = time_limit_q;
           Tests:       T1 T2 T3 
256        1/1              prog_pend_d      = prog_pend_q;
           Tests:       T1 T2 T3 
257        1/1              mem_req          = '0;
           Tests:       T1 T2 T3 
258        1/1              mem_wr           = '0;
           Tests:       T1 T2 T3 
259        1/1              mem_wdata        = '0;
           Tests:       T1 T2 T3 
260        1/1              time_cnt_inc     = '0;
           Tests:       T1 T2 T3 
261        1/1              time_cnt_clr     = '0;
           Tests:       T1 T2 T3 
262        1/1              time_cnt_set1    = '0;
           Tests:       T1 T2 T3 
263        1/1              index_cnt_inc    = '0;
           Tests:       T1 T2 T3 
264        1/1              index_cnt_clr    = '0;
           Tests:       T1 T2 T3 
265                     
266                         // i/o
267        1/1              init_busy_o      = '0;
           Tests:       T1 T2 T3 
268        1/1              pop_cmd          = '0;
           Tests:       T1 T2 T3 
269        1/1              done_o           = '0;
           Tests:       T1 T2 T3 
270                     
271        1/1              unique case (st_q)
           Tests:       T1 T2 T3 
272                           StReset: begin
273        1/1                  init_busy_o = 1'b1;
           Tests:       T1 T2 T3 
274        1/1                  if (init_i && flash_power_ready_h_i && !flash_power_down_h_i) begin
           Tests:       T1 T2 T3 
275        1/1                    st_d = StInit;
           Tests:       T1 T2 T3 
276                             end
                        MISSING_ELSE
277                           end
278                     
279                           // Emulate flash initilaization with a wait timer
280                           StInit: begin
281        1/1                  init_busy_o = 1'h1;
           Tests:       T1 T2 T3 
282        1/1                  if (index_cnt < InitCycles) begin
           Tests:       T1 T2 T3 
283        1/1                    st_d = StInit;
           Tests:       T1 T2 T3 
284        1/1                    index_cnt_inc = 1'b1;
           Tests:       T1 T2 T3 
285                             end else begin
286        1/1                    st_d = StIdle;
           Tests:       T1 T2 T3 
287        1/1                    index_cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
288                             end
289                           end
290                     
291                           StIdle: begin
292        1/1                  if (rd_req) begin
           Tests:       T1 T2 T3 
293        1/1                    pop_cmd = 1'b1;
           Tests:       T1 T2 T3 
294        1/1                    mem_req = 1'b1;
           Tests:       T1 T2 T3 
295        1/1                    time_cnt_inc = 1'b1;
           Tests:       T1 T2 T3 
296        1/1                    st_d = StRead;
           Tests:       T1 T2 T3 
297        1/1                  end else if (prog_req) begin
           Tests:       T1 T2 T3 
298        1/1                    mem_req = 1'b1;
           Tests:       T2 T4 T5 
299        1/1                    prog_pend_d = 1'b1;
           Tests:       T2 T4 T5 
300        1/1                    st_d = StRead;
           Tests:       T2 T4 T5 
301        1/1                  end else if (pg_erase_req) begin
           Tests:       T1 T2 T3 
302        1/1                    st_d = StErase;
           Tests:       T9 T27 T28 
303        1/1                    index_limit_d = WordsPerPage;
           Tests:       T9 T27 T28 
304        1/1                    time_limit_d = EraseLatency;
           Tests:       T9 T27 T28 
305        1/1                  end else if (bk_erase_req) begin
           Tests:       T1 T2 T3 
306        1/1                    st_d = StErase;
           Tests:       T29 T30 T31 
307        1/1                    index_limit_d = WordsPerBank;
           Tests:       T29 T30 T31 
308        1/1                    time_limit_d = BkEraseCycles;
           Tests:       T29 T30 T31 
309                             end
                        MISSING_ELSE
310                           end
311                     
312                           StRead: begin
313        1/1                  if (time_cnt < ReadLatency) begin
           Tests:       T1 T2 T3 
314        1/1                    time_cnt_inc = 1'b1;
           Tests:       T2 T4 T5 
315                     
316        1/1                  end else if (!prog_pend_q) begin
           Tests:       T1 T2 T3 
317        1/1                    done_o = 1'b1;
           Tests:       T1 T2 T3 
318                     
319                               // if another request already pending
320        1/1                    if (rd_req) begin
           Tests:       T1 T2 T3 
321        0/1     ==>              pop_cmd = 1'b1;
322        0/1     ==>              mem_req = 1'b1;
323        0/1     ==>              time_cnt_set1 = 1'b1;
324        0/1     ==>              st_d = StRead;
325                               end else begin
326        1/1                      time_cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
327        1/1                      st_d = StIdle;
           Tests:       T1 T2 T3 
328                               end
329                     
330        1/1                  end else if (prog_pend_q) begin
           Tests:       T2 T4 T5 
331                               // this is the read performed before a program operation
332        1/1                    prog_pend_d = 1'b0;
           Tests:       T2 T4 T5 
333        1/1                    time_cnt_clr = 1'b1;
           Tests:       T2 T4 T5 
334        1/1                    st_d = StProg;
           Tests:       T2 T4 T5 
335                             end
                   ==>  MISSING_ELSE
336                           end
337                     
338                           StProg: begin
339                             // if data is already 0, cannot program to 1 without erase
340        1/1                  mem_wdata = cmd_q.prog_data & rd_data_q;
           Tests:       T2 T4 T5 
341        1/1                  if (time_cnt < ProgLatency) begin
           Tests:       T2 T4 T5 
342        1/1                    mem_req = 1'b1;
           Tests:       T2 T4 T5 
343        1/1                    mem_wr = 1'b1;
           Tests:       T2 T4 T5 
344        1/1                    time_cnt_inc = 1'b1;
           Tests:       T2 T4 T5 
345                             end else begin
346        1/1                    st_d = StIdle;
           Tests:       T2 T4 T5 
347        1/1                    pop_cmd = 1'b1;
           Tests:       T2 T4 T5 
348        1/1                    done_o = cmd_q.prog_last;
           Tests:       T2 T4 T5 
349        1/1                    time_cnt_clr = 1'b1;
           Tests:       T2 T4 T5 
350                             end
351                           end
352                     
353                           StErase: begin
354                             // Actual erasing of the page
355        1/1                  if (erase_suspend_req_i) begin
           Tests:       T9 T27 T28 
356        1/1                    st_d = StErSuspend;
           Tests:       T35 T67 T68 
357        1/1                  end else if (index_cnt < index_limit_q || time_cnt < time_limit_q) begin
           Tests:       T9 T27 T28 
358        1/1                    mem_req = 1'b1;
           Tests:       T9 T27 T28 
359        1/1                    mem_wr = 1'b1;
           Tests:       T9 T27 T28 
360        1/1                    mem_wdata = {DataWidth{1'b1}};
           Tests:       T9 T27 T28 
361        1/1                    time_cnt_inc = (time_cnt < time_limit_q);
           Tests:       T9 T27 T28 
362        1/1                    index_cnt_inc = (index_cnt < index_limit_q);
           Tests:       T9 T27 T28 
363                             end else begin
364        1/1                    st_d = StIdle;
           Tests:       T9 T27 T28 
365        1/1                    pop_cmd = 1'b1;
           Tests:       T9 T27 T28 
366        1/1                    done_o = 1'b1;
           Tests:       T9 T27 T28 
367        1/1                    time_cnt_clr = 1'b1;
           Tests:       T9 T27 T28 
368        1/1                    index_cnt_clr = 1'b1;
           Tests:       T9 T27 T28 
369                             end
370                           end // case: StErase
371                     
372                           // The done can actually be signaled back in `StErase`, but move it
373                           // to a different state to better model the ack_o/done_o timing separation
374                           StErSuspend: begin
375        1/1                   done_o = 1'b1;
           Tests:       T35 T67 T68 
376        1/1                   pop_cmd = 1'b1;
           Tests:       T35 T67 T68 
377        1/1                   time_cnt_clr = 1'b1;
           Tests:       T35 T67 T68 
378        1/1                   index_cnt_clr = 1'b1;
           Tests:       T35 T67 T68 
379        1/1                   st_d = StIdle;
           Tests:       T35 T67 T68 
380                           end
381                     
382                     
383                           default: begin
384                             st_d = StIdle;
385                           end
386                     
387                         endcase // unique case (st_q)
388                     
389                         // Emulate power down and power loss behavior
390        1/1              if (!flash_power_ready_h_i || flash_power_down_h_i) begin
           Tests:       T1 T2 T3 
391        1/1                st_d = StReset;
           Tests:       T1 T2 T3 
392                         end
                        MISSING_ELSE
393                     
394                       end // always_comb
395                     
396                       logic [DataWidth-1:0] rd_data_main, rd_data_info;
397                       logic [InfoTypes-1:0][DataWidth-1:0] rd_nom_data_info;
398                     
399                       // data memory is requested whenver it's a transaction targetted at the data partition
400                       // OR if it's a bank erase
401                       logic data_mem_req;
402        1/1            assign data_mem_req = mem_req &
           Tests:       T1 T2 T3 
403                                             (mem_part == flash_ctrl_pkg::FlashPartData |
404                                              mem_bk_erase);
405                     
406                       prim_ram_1p #(
407                         .Width(DataWidth),
408                         .Depth(WordsPerBank),
409                         .DataBitsPerMask(DataWidth)
410                       ) u_mem (
411                         .clk_i,
412                         .req_i    (data_mem_req),
413                         .write_i  (mem_wr),
414                         .addr_i   (mem_addr),
415                         .wdata_i  (mem_wdata),
416                         .wmask_i  ({DataWidth{1'b1}}),
417                         .rdata_o  (rd_data_main),
418                         .cfg_i    ('0)
419                       );
420                     
421                       for (genvar info_type = 0; info_type < InfoTypes; info_type++) begin : gen_info_types
422                     
423                         // when info partitions are selected for bank erase, all info types are erased.
424                         // if NOT bank erase, then only the selected info partition is erased
425                         logic info_mem_req;
426        3/3              assign info_mem_req = mem_req &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
427                                               (mem_part == flash_ctrl_pkg::FlashPartInfo) &
428                                               ((mem_info_sel == info_type) | mem_bk_erase);
429                     
430                         prim_ram_1p #(
431                           .Width(DataWidth),
432                           .Depth(WordsPerInfoBank),
433                           .DataBitsPerMask(DataWidth)
434                         ) u_info_mem (
435                           .clk_i,
436                           .req_i    (info_mem_req),
437                           .write_i  (mem_wr),
438                           .addr_i   (mem_addr[0 +: InfoAddrW]),
439                           .wdata_i  (mem_wdata),
440                           .wmask_i  ({DataWidth{1'b1}}),
441                           .rdata_o  (rd_nom_data_info[info_type]),
442                           .cfg_i    ('0)
443                         );
444                       end
445                     
446        1/1            assign rd_data_info = rd_nom_data_info[info_sel_q];
           Tests:       T1 T2 T3 
447        1/1            assign rd_data_d    = rd_part_q == flash_ctrl_pkg::FlashPartData ? rd_data_main : rd_data_info;
           Tests:       T1 T2 T3 
448                     
449                       flash_ctrl_pkg::flash_prog_e unused_prog_type;
450        1/1            assign unused_prog_type = cmd_q.prog_type;
           Tests:       T1 T2 T3 
451                     
452                       logic unused_he;
453        1/1            assign unused_he = he_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_generic_flash_bank

	Total	Covered	Percent
Conditions	84	78	92.86
Logical	84	78	92.86
Non-Logical	0	0
Event	0	0

 LINE       152
 EXPRESSION ((rd_i | prog_i | pg_erase_i | bk_erase_i) & ((!init_busy_o)))
             --------------------1--------------------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T67,T68,T71
1	1	Covered	T1,T2,T3

 LINE       152
 SUB-EXPRESSION (rd_i | prog_i | pg_erase_i | bk_erase_i)
                 --1-   ---2--   -----3----   -----4----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T29,T30,T31
0	0	1	0	Covered	T9,T27,T28
0	1	0	0	Covered	T2,T4,T5
1	0	0	0	Covered	T1,T2,T3

 LINE       153
 EXPRESSION (ack & ((!init_busy_o)))
             -1-   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       175
 EXPRESSION (cmd_valid & cmd_q.rd)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       176
 EXPRESSION (cmd_valid & cmd_q.prog)
             ----1----   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       177
 EXPRESSION (cmd_valid & cmd_q.pg_erase)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T27,T28

 LINE       178
 EXPRESSION (cmd_valid & cmd_q.bk_erase)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T29,T30,T31

 LINE       181
 EXPRESSION (mem_req & ((~mem_wr)))
             ---1---   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION ((ReadLatency == 1) ? rd_data_d : rd_data_q)
             ---------1--------

-1-	Status	Tests
0	Covered	T49,T41,T79
1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (ReadLatency == 1)
                ---------1--------

-1-	Status	Tests
0	Covered	T49,T41,T79
1	Covered	T1,T2,T3

 LINE       274
 EXPRESSION (init_i && flash_power_ready_h_i && ((!flash_power_down_h_i)))
             ---1--    ----------2----------    ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Covered	T35,T67,T68
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       357
 EXPRESSION ((index_cnt < index_limit_q) || (time_cnt < time_limit_q))
             -------------1-------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T27,T28
0	1	Not Covered
1	0	Covered	T9,T27,T28

 LINE       390
 EXPRESSION (((!flash_power_ready_h_i)) || flash_power_down_h_i)
             -------------1------------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T35,T67,T68

 LINE       402
 EXPRESSION (mem_req & ((mem_part == FlashPartData) | mem_bk_erase))
             ---1---   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       402
 SUB-EXPRESSION ((mem_part == FlashPartData) | mem_bk_erase)
                 -------------1-------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T32,T80,T81
1	0	Covered	T1,T2,T3

 LINE       402
 SUB-EXPRESSION (mem_part == FlashPartData)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 0) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T11,T34
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T27,T36,T52
1	1	1	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 0) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T27,T36,T52
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 0)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 1) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T32,T80,T81
1	0	1	Covered	T52,T74,T29
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T52,T82,T83

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 1) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T52,T74,T61

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T52,T74,T61

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 2) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T36,T84,T85
1	0	1	Covered	T27,T36,T52
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T27,T36,T52

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 2) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T27,T36,T52

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 2)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T27,T36,T52

 LINE       447
 EXPRESSION ((rd_part_q == FlashPartData) ? rd_data_main : rd_data_info)
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       447
 SUB-EXPRESSION (rd_part_q == FlashPartData)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : prim_generic_flash_bank

Summary for FSM :: st_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	16	15	93.75
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StErSuspend	356	Covered	T35,T67,T68
StErase	302	Covered	T9,T27,T28
StIdle	286	Covered	T1,T2,T3
StInit	275	Covered	T1,T2,T3
StProg	334	Covered	T2,T4,T5
StRead	296	Covered	T1,T2,T3
StReset	391	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StErSuspend->StIdle	379	Covered	T35,T69,T70
StErSuspend->StReset	391	Covered	T67,T68,T71
StErase->StErSuspend	356	Covered	T35,T67,T68
StErase->StIdle	364	Covered	T9,T27,T28
StErase->StReset	391	Covered	T35,T67,T86
StIdle->StErase	302	Covered	T9,T27,T28
StIdle->StRead	296	Covered	T1,T2,T3
StIdle->StReset	391	Covered	T1,T4,T59
StInit->StIdle	286	Covered	T1,T2,T3
StInit->StReset	391	Not Covered
StProg->StIdle	346	Covered	T2,T4,T5
StProg->StReset	391	Covered	T11,T35,T67
StRead->StIdle	327	Covered	T1,T2,T3
StRead->StProg	334	Covered	T2,T4,T5
StRead->StReset	391	Covered	T67,T87,T71
StReset->StInit	275	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_generic_flash_bank

	Line No.	Total	Covered	Percent
Branches		45	41	91.11
TERNARY	231	2	2	100.00
TERNARY	447	2	2	100.00
IF	189	2	2	100.00
IF	194	2	2	100.00
IF	210	3	3	100.00
IF	221	3	3	100.00
IF	236	8	7	87.50
CASE	271	21	18	85.71
IF	390	2	2	100.00

231          assign rd_data_o = ReadLatency == 1 ? rd_data_d : rd_data_q;
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T49,T41,T79

447          assign rd_data_d    = rd_part_q == flash_ctrl_pkg::FlashPartData ? rd_data_main : rd_data_info;
                                                                              -1-  
                                                                              ==>  
                                                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

189            if (!rst_ni) st_q <= StReset;
               -1-  
               ==>
190            else st_q <= st_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

194            if (!rst_ni) begin
               -1-  
195              time_limit_q  <= 'h0;
                 ==>
196              index_limit_q <= 'h0;
197              prog_pend_q   <= 'h0;
198              mem_rd_q      <= 'h0;
199            end else begin
200              time_limit_q  <= time_limit_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

210            if (!rst_ni) begin
               -1-  
211              rd_data_q <= '0;
                 ==>
212            end else if (mem_rd_q) begin
                        -2-  
213              rd_data_q <= rd_data_d;
                 ==>
214            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

221            if (!rst_ni) begin
               -1-  
222              rd_part_q <= flash_ctrl_pkg::FlashPartData;
                 ==>
223              info_sel_q <= '0;
224            end else if (mem_rd_d) begin
                        -2-  
225              rd_part_q <= cmd_q.part;
                 ==>
226              info_sel_q <= cmd_q.info_sel;
227            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

236            if (!rst_ni) begin
               -1-  
237              time_cnt  <= 'h0;
                 ==>
238              index_cnt <= 'h0;
239            end else begin
240              if (time_cnt_inc) time_cnt <= time_cnt + 1'b1;
                 -2-  
                 ==>
241              else if (time_cnt_set1) time_cnt <= 32'h1;
                      -3-  
                 ==>
242              else if (time_cnt_clr) time_cnt <= 32'h0;
                      -4-  
                 ==>
                 MISSING_ELSE
                 ==>
243        
244              if (index_cnt_inc) index_cnt <= index_cnt + 1'b1;
                 -5-  
                 ==>
245              else if (index_cnt_clr) index_cnt <= 32'h0;
                      -6-  
                 ==>
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	-	Not Covered
0	0	0	1	-	-	Covered	T1,T2,T3
0	0	0	0	-	-	Covered	T1,T2,T3
0	-	-	-	1	-	Covered	T1,T2,T3
0	-	-	-	0	1	Covered	T1,T2,T3
0	-	-	-	0	0	Covered	T1,T2,T3

271            unique case (st_q)
                      -1-  
272              StReset: begin
273                init_busy_o = 1'b1;
274                if (init_i && flash_power_ready_h_i && !flash_power_down_h_i) begin
                   -2-  
275                  st_d = StInit;
                     ==>
276                end
                   MISSING_ELSE
                   ==>
277              end
278        
279              // Emulate flash initilaization with a wait timer
280              StInit: begin
281                init_busy_o = 1'h1;
282                if (index_cnt < InitCycles) begin
                   -3-  
283                  st_d = StInit;
                     ==>
284                  index_cnt_inc = 1'b1;
285                end else begin
286                  st_d = StIdle;
                     ==>
287                  index_cnt_clr = 1'b1;
288                end
289              end
290        
291              StIdle: begin
292                if (rd_req) begin
                   -4-  
293                  pop_cmd = 1'b1;
                     ==>
294                  mem_req = 1'b1;
295                  time_cnt_inc = 1'b1;
296                  st_d = StRead;
297                end else if (prog_req) begin
                            -5-  
298                  mem_req = 1'b1;
                     ==>
299                  prog_pend_d = 1'b1;
300                  st_d = StRead;
301                end else if (pg_erase_req) begin
                            -6-  
302                  st_d = StErase;
                     ==>
303                  index_limit_d = WordsPerPage;
304                  time_limit_d = EraseLatency;
305                end else if (bk_erase_req) begin
                            -7-  
306                  st_d = StErase;
                     ==>
307                  index_limit_d = WordsPerBank;
308                  time_limit_d = BkEraseCycles;
309                end
                   MISSING_ELSE
                   ==>
310              end
311        
312              StRead: begin
313                if (time_cnt < ReadLatency) begin
                   -8-  
314                  time_cnt_inc = 1'b1;
                     ==>
315        
316                end else if (!prog_pend_q) begin
                            -9-  
317                  done_o = 1'b1;
318        
319                  // if another request already pending
320                  if (rd_req) begin
                     -10-  
321                    pop_cmd = 1'b1;
                       ==>
322                    mem_req = 1'b1;
323                    time_cnt_set1 = 1'b1;
324                    st_d = StRead;
325                  end else begin
326                    time_cnt_clr = 1'b1;
                       ==>
327                    st_d = StIdle;
328                  end
329        
330                end else if (prog_pend_q) begin
                            -11-  
331                  // this is the read performed before a program operation
332                  prog_pend_d = 1'b0;
                     ==>
333                  time_cnt_clr = 1'b1;
334                  st_d = StProg;
335                end
                   MISSING_ELSE
                   ==>
336              end
337        
338              StProg: begin
339                // if data is already 0, cannot program to 1 without erase
340                mem_wdata = cmd_q.prog_data & rd_data_q;
341                if (time_cnt < ProgLatency) begin
                   -12-  
342                  mem_req = 1'b1;
                     ==>
343                  mem_wr = 1'b1;
344                  time_cnt_inc = 1'b1;
345                end else begin
346                  st_d = StIdle;
                     ==>
347                  pop_cmd = 1'b1;
348                  done_o = cmd_q.prog_last;
349                  time_cnt_clr = 1'b1;
350                end
351              end
352        
353              StErase: begin
354                // Actual erasing of the page
355                if (erase_suspend_req_i) begin
                   -13-  
356                  st_d = StErSuspend;
                     ==>
357                end else if (index_cnt < index_limit_q || time_cnt < time_limit_q) begin
                            -14-  
358                  mem_req = 1'b1;
                     ==>
359                  mem_wr = 1'b1;
360                  mem_wdata = {DataWidth{1'b1}};
361                  time_cnt_inc = (time_cnt < time_limit_q);
362                  index_cnt_inc = (index_cnt < index_limit_q);
363                end else begin
364                  st_d = StIdle;
                     ==>
365                  pop_cmd = 1'b1;
366                  done_o = 1'b1;
367                  time_cnt_clr = 1'b1;
368                  index_cnt_clr = 1'b1;
369                end
370              end // case: StErase
371        
372              // The done can actually be signaled back in `StErase`, but move it
373              // to a different state to better model the ack_o/done_o timing separation
374              StErSuspend: begin
375                 done_o = 1'b1;
                    ==>
376                 pop_cmd = 1'b1;
377                 time_cnt_clr = 1'b1;
378                 index_cnt_clr = 1'b1;
379                 st_d = StIdle;
380              end
381        
382        
383              default: begin
384                st_d = StIdle;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
StReset	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReset	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StInit	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StInit	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
StIdle	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T9,T27,T28
StIdle	-	-	0	0	0	1	-	-	-	-	-	-	-	Covered	T29,T30,T31
StIdle	-	-	0	0	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRead	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T4,T5
StRead	-	-	-	-	-	-	0	1	1	-	-	-	-	Not Covered
StRead	-	-	-	-	-	-	0	1	0	-	-	-	-	Covered	T1,T2,T3
StRead	-	-	-	-	-	-	0	0	-	1	-	-	-	Covered	T2,T4,T5
StRead	-	-	-	-	-	-	0	0	-	0	-	-	-	Not Covered
StProg	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T2,T4,T5
StProg	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T4,T5
StErase	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T35,T67,T68
StErase	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T9,T27,T28
StErase	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T9,T27,T28
StErSuspend	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T35,T67,T68
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

390            if (!flash_power_ready_h_i || flash_power_down_h_i) begin
               -1-  
391              st_d = StReset;
                 ==>
392            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank

	Line No.	Total	Covered	Percent
TOTAL		142	137	96.48
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	181	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
ALWAYS	189	3	3	100.00
ALWAYS	194	9	9	100.00
ALWAYS	210	4	4	100.00
ALWAYS	221	6	6	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	236	13	12	92.31
ALWAYS	251	86	82	95.35
CONT_ASSIGN	402	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	453	1	1	100.00

126                     
127        1/1            assign cmd_d = '{
           Tests:       T1 T2 T3 
128                         rd :       rd_i,
129                         prog:      prog_i,
130                         prog_last: prog_last_i,
131                         prog_type: prog_type_i,
132                         pg_erase:  pg_erase_i,
133                         bk_erase:  bk_erase_i,
134                         addr:      addr_i,
135                         part:      part_i,
136                         info_sel:  info_sel_i,
137                         prog_data: prog_data_i
138                       };
139                     
140                       // for read transactions, in order to reduce latency, the
141                       // command fifo is popped early (before done_o).  This is to ensure that when
142                       // the current transaction is complete, during the same cycle
143                       // a new read can be issued. As a result, the command is popped
144                       // immediately after the read is issued, rather than waiting for
145                       // the read to be completed.  The same restrictions are not necessary
146                       // for program / erase, which do not have the same performance
147                       // requirements.
148                     
149                       // when the flash is going through init, do not accept any transactions
150                       logic wvalid;
151                       logic ack;
152        1/1            assign wvalid = (rd_i | prog_i | pg_erase_i | bk_erase_i) & !init_busy_o;
           Tests:       T1 T2 T3 
153        1/1            assign ack_o = ack & !init_busy_o;
           Tests:       T1 T2 T3 
154                     
155                       prim_fifo_sync #(
156                         .Width   ($bits(cmd_payload_t)),
157                         .Pass    (0),
158                         .Depth   (2)
159                       ) u_cmd_fifo (
160                         .clk_i,
161                         .rst_ni,
162                         .clr_i   (1'b0),
163                         .wvalid_i(wvalid),
164                         .wready_o(ack),
165                         .wdata_i (cmd_d),
166                         .depth_o (),
167                         .full_o (),
168                         .rvalid_o(cmd_valid),
169                         .rready_i(pop_cmd),
170                         .rdata_o (cmd_q),
171                         .err_o   ()
172                       );
173                     
174                       logic rd_req, prog_req, pg_erase_req, bk_erase_req;
175        1/1            assign rd_req = cmd_valid & cmd_q.rd;
           Tests:       T1 T2 T3 
176        1/1            assign prog_req = cmd_valid & cmd_q.prog;
           Tests:       T1 T2 T3 
177        1/1            assign pg_erase_req = cmd_valid & cmd_q.pg_erase;
           Tests:       T1 T2 T3 
178        1/1            assign bk_erase_req = cmd_valid & cmd_q.bk_erase;
           Tests:       T1 T2 T3 
179                     
180                       // for read / program operations, the index cnt should be 0
181        1/1            assign mem_rd_d = mem_req & ~mem_wr;
           Tests:       T1 T2 T3 
182        1/1            assign mem_addr = cmd_q.addr + index_cnt[AddrW-1:0];
           Tests:       T1 T2 T3 
183        1/1            assign mem_part = cmd_q.part;
           Tests:       T1 T2 T3 
184        1/1            assign mem_bk_erase = cmd_q.bk_erase;
           Tests:       T1 T2 T3 
185                     
186        1/1            assign mem_info_sel = cmd_q.info_sel;
           Tests:       T1 T2 T3 
187                     
188                       always_ff @(posedge clk_i or negedge rst_ni) begin
189        2/2              if (!rst_ni) st_q <= StReset;
           Tests:       T1 T2 T3  | T1 T2 T3 
190        1/1              else st_q <= st_d;
           Tests:       T1 T2 T3 
191                       end
192                     
193                       always_ff @(posedge clk_i or negedge rst_ni) begin
194        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
195        1/1                time_limit_q  <= 'h0;
           Tests:       T1 T2 T3 
196        1/1                index_limit_q <= 'h0;
           Tests:       T1 T2 T3 
197        1/1                prog_pend_q   <= 'h0;
           Tests:       T1 T2 T3 
198        1/1                mem_rd_q      <= 'h0;
           Tests:       T1 T2 T3 
199                         end else begin
200        1/1                time_limit_q  <= time_limit_d;
           Tests:       T1 T2 T3 
201        1/1                index_limit_q <= index_limit_d;
           Tests:       T1 T2 T3 
202        1/1                prog_pend_q   <= prog_pend_d;
           Tests:       T1 T2 T3 
203        1/1                mem_rd_q      <= mem_rd_d;
           Tests:       T1 T2 T3 
204                         end
205                       end
206                     
207                       // latch read data from emulated memories the cycle after a read
208                       logic [DataWidth-1:0] rd_data_q, rd_data_d;
209                       always_ff @(posedge clk_i or negedge rst_ni) begin
210        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
211        1/1                rd_data_q <= '0;
           Tests:       T1 T2 T3 
212        1/1              end else if (mem_rd_q) begin
           Tests:       T1 T2 T3 
213        1/1                rd_data_q <= rd_data_d;
           Tests:       T1 T2 T3 
214                         end
                        MISSING_ELSE
215                       end
216                     
217                       // latch partiton being read since the command fifo is popped early
218                       flash_ctrl_pkg::flash_part_e rd_part_q;
219                       logic [InfoTypesWidth-1:0] info_sel_q;
220                       always_ff @(posedge clk_i or negedge rst_ni) begin
221        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
222        1/1                rd_part_q <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
223        1/1                info_sel_q <= '0;
           Tests:       T1 T2 T3 
224        1/1              end else if (mem_rd_d) begin
           Tests:       T1 T2 T3 
225        1/1                rd_part_q <= cmd_q.part;
           Tests:       T1 T2 T3 
226        1/1                info_sel_q <= cmd_q.info_sel;
           Tests:       T1 T2 T3 
227                         end
                        MISSING_ELSE
228                       end
229                     
230                       // if read cycle is only 1, we can expose the unlatched data directly
231        1/1            assign rd_data_o = ReadLatency == 1 ? rd_data_d : rd_data_q;
           Tests:       T1 T2 T3 
232                     
233                       // prog_pend_q is necessary to emulate flash behavior that a bit written to 0 cannot be written
234                       // back to 1 without an erase
235                       always_ff @(posedge clk_i or negedge rst_ni) begin
236        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
237        1/1                time_cnt  <= 'h0;
           Tests:       T1 T2 T3 
238        1/1                index_cnt <= 'h0;
           Tests:       T1 T2 T3 
239                         end else begin
240        2/2                if (time_cnt_inc) time_cnt <= time_cnt + 1'b1;
           Tests:       T1 T2 T3  | T1 T2 T3 
241        1/2     ==>        else if (time_cnt_set1) time_cnt <= 32'h1;
           Tests:       T1 T2 T3 
242        2/2                else if (time_cnt_clr) time_cnt <= 32'h0;
           Tests:       T1 T2 T3  | T1 T2 T3 
                        MISSING_ELSE
243                     
244        2/2                if (index_cnt_inc) index_cnt <= index_cnt + 1'b1;
           Tests:       T1 T2 T3  | T1 T2 T3 
245        2/2                else if (index_cnt_clr) index_cnt <= 32'h0;
           Tests:       T1 T2 T3  | T1 T2 T3 
                        MISSING_ELSE
246                         end
247                       end
248                     
249                       always_comb begin
250                         // state
251        1/1              st_d             = st_q;
           Tests:       T1 T2 T3 
252                     
253                         // internally consumed signals
254        1/1              index_limit_d    = index_limit_q;
           Tests:       T1 T2 T3 
255        1/1              time_limit_d     = time_limit_q;
           Tests:       T1 T2 T3 
256        1/1              prog_pend_d      = prog_pend_q;
           Tests:       T1 T2 T3 
257        1/1              mem_req          = '0;
           Tests:       T1 T2 T3 
258        1/1              mem_wr           = '0;
           Tests:       T1 T2 T3 
259        1/1              mem_wdata        = '0;
           Tests:       T1 T2 T3 
260        1/1              time_cnt_inc     = '0;
           Tests:       T1 T2 T3 
261        1/1              time_cnt_clr     = '0;
           Tests:       T1 T2 T3 
262        1/1              time_cnt_set1    = '0;
           Tests:       T1 T2 T3 
263        1/1              index_cnt_inc    = '0;
           Tests:       T1 T2 T3 
264        1/1              index_cnt_clr    = '0;
           Tests:       T1 T2 T3 
265                     
266                         // i/o
267        1/1              init_busy_o      = '0;
           Tests:       T1 T2 T3 
268        1/1              pop_cmd          = '0;
           Tests:       T1 T2 T3 
269        1/1              done_o           = '0;
           Tests:       T1 T2 T3 
270                     
271        1/1              unique case (st_q)
           Tests:       T1 T2 T3 
272                           StReset: begin
273        1/1                  init_busy_o = 1'b1;
           Tests:       T1 T2 T3 
274        1/1                  if (init_i && flash_power_ready_h_i && !flash_power_down_h_i) begin
           Tests:       T1 T2 T3 
275        1/1                    st_d = StInit;
           Tests:       T1 T2 T3 
276                             end
                        MISSING_ELSE
277                           end
278                     
279                           // Emulate flash initilaization with a wait timer
280                           StInit: begin
281        1/1                  init_busy_o = 1'h1;
           Tests:       T1 T2 T3 
282        1/1                  if (index_cnt < InitCycles) begin
           Tests:       T1 T2 T3 
283        1/1                    st_d = StInit;
           Tests:       T1 T2 T3 
284        1/1                    index_cnt_inc = 1'b1;
           Tests:       T1 T2 T3 
285                             end else begin
286        1/1                    st_d = StIdle;
           Tests:       T1 T2 T3 
287        1/1                    index_cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
288                             end
289                           end
290                     
291                           StIdle: begin
292        1/1                  if (rd_req) begin
           Tests:       T1 T2 T3 
293        1/1                    pop_cmd = 1'b1;
           Tests:       T1 T2 T3 
294        1/1                    mem_req = 1'b1;
           Tests:       T1 T2 T3 
295        1/1                    time_cnt_inc = 1'b1;
           Tests:       T1 T2 T3 
296        1/1                    st_d = StRead;
           Tests:       T1 T2 T3 
297        1/1                  end else if (prog_req) begin
           Tests:       T1 T2 T3 
298        1/1                    mem_req = 1'b1;
           Tests:       T2 T4 T5 
299        1/1                    prog_pend_d = 1'b1;
           Tests:       T2 T4 T5 
300        1/1                    st_d = StRead;
           Tests:       T2 T4 T5 
301        1/1                  end else if (pg_erase_req) begin
           Tests:       T1 T2 T3 
302        1/1                    st_d = StErase;
           Tests:       T9 T27 T28 
303        1/1                    index_limit_d = WordsPerPage;
           Tests:       T9 T27 T28 
304        1/1                    time_limit_d = EraseLatency;
           Tests:       T9 T27 T28 
305        1/1                  end else if (bk_erase_req) begin
           Tests:       T1 T2 T3 
306        1/1                    st_d = StErase;
           Tests:       T30 T31 T32 
307        1/1                    index_limit_d = WordsPerBank;
           Tests:       T30 T31 T32 
308        1/1                    time_limit_d = BkEraseCycles;
           Tests:       T30 T31 T32 
309                             end
                        MISSING_ELSE
310                           end
311                     
312                           StRead: begin
313        1/1                  if (time_cnt < ReadLatency) begin
           Tests:       T1 T2 T3 
314        1/1                    time_cnt_inc = 1'b1;
           Tests:       T2 T4 T5 
315                     
316        1/1                  end else if (!prog_pend_q) begin
           Tests:       T1 T2 T3 
317        1/1                    done_o = 1'b1;
           Tests:       T1 T2 T3 
318                     
319                               // if another request already pending
320        1/1                    if (rd_req) begin
           Tests:       T1 T2 T3 
321        0/1     ==>              pop_cmd = 1'b1;
322        0/1     ==>              mem_req = 1'b1;
323        0/1     ==>              time_cnt_set1 = 1'b1;
324        0/1     ==>              st_d = StRead;
325                               end else begin
326        1/1                      time_cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
327        1/1                      st_d = StIdle;
           Tests:       T1 T2 T3 
328                               end
329                     
330        1/1                  end else if (prog_pend_q) begin
           Tests:       T2 T4 T5 
331                               // this is the read performed before a program operation
332        1/1                    prog_pend_d = 1'b0;
           Tests:       T2 T4 T5 
333        1/1                    time_cnt_clr = 1'b1;
           Tests:       T2 T4 T5 
334        1/1                    st_d = StProg;
           Tests:       T2 T4 T5 
335                             end
                   ==>  MISSING_ELSE
336                           end
337                     
338                           StProg: begin
339                             // if data is already 0, cannot program to 1 without erase
340        1/1                  mem_wdata = cmd_q.prog_data & rd_data_q;
           Tests:       T2 T4 T5 
341        1/1                  if (time_cnt < ProgLatency) begin
           Tests:       T2 T4 T5 
342        1/1                    mem_req = 1'b1;
           Tests:       T2 T4 T5 
343        1/1                    mem_wr = 1'b1;
           Tests:       T2 T4 T5 
344        1/1                    time_cnt_inc = 1'b1;
           Tests:       T2 T4 T5 
345                             end else begin
346        1/1                    st_d = StIdle;
           Tests:       T2 T4 T5 
347        1/1                    pop_cmd = 1'b1;
           Tests:       T2 T4 T5 
348        1/1                    done_o = cmd_q.prog_last;
           Tests:       T2 T4 T5 
349        1/1                    time_cnt_clr = 1'b1;
           Tests:       T2 T4 T5 
350                             end
351                           end
352                     
353                           StErase: begin
354                             // Actual erasing of the page
355        1/1                  if (erase_suspend_req_i) begin
           Tests:       T9 T27 T28 
356        1/1                    st_d = StErSuspend;
           Tests:       T67 T69 T70 
357        1/1                  end else if (index_cnt < index_limit_q || time_cnt < time_limit_q) begin
           Tests:       T9 T27 T28 
358        1/1                    mem_req = 1'b1;
           Tests:       T9 T27 T28 
359        1/1                    mem_wr = 1'b1;
           Tests:       T9 T27 T28 
360        1/1                    mem_wdata = {DataWidth{1'b1}};
           Tests:       T9 T27 T28 
361        1/1                    time_cnt_inc = (time_cnt < time_limit_q);
           Tests:       T9 T27 T28 
362        1/1                    index_cnt_inc = (index_cnt < index_limit_q);
           Tests:       T9 T27 T28 
363                             end else begin
364        1/1                    st_d = StIdle;
           Tests:       T9 T27 T28 
365        1/1                    pop_cmd = 1'b1;
           Tests:       T9 T27 T28 
366        1/1                    done_o = 1'b1;
           Tests:       T9 T27 T28 
367        1/1                    time_cnt_clr = 1'b1;
           Tests:       T9 T27 T28 
368        1/1                    index_cnt_clr = 1'b1;
           Tests:       T9 T27 T28 
369                             end
370                           end // case: StErase
371                     
372                           // The done can actually be signaled back in `StErase`, but move it
373                           // to a different state to better model the ack_o/done_o timing separation
374                           StErSuspend: begin
375        1/1                   done_o = 1'b1;
           Tests:       T67 T69 T70 
376        1/1                   pop_cmd = 1'b1;
           Tests:       T67 T69 T70 
377        1/1                   time_cnt_clr = 1'b1;
           Tests:       T67 T69 T70 
378        1/1                   index_cnt_clr = 1'b1;
           Tests:       T67 T69 T70 
379        1/1                   st_d = StIdle;
           Tests:       T67 T69 T70 
380                           end
381                     
382                     
383                           default: begin
384                             st_d = StIdle;
385                           end
386                     
387                         endcase // unique case (st_q)
388                     
389                         // Emulate power down and power loss behavior
390        1/1              if (!flash_power_ready_h_i || flash_power_down_h_i) begin
           Tests:       T1 T2 T3 
391        1/1                st_d = StReset;
           Tests:       T1 T2 T3 
392                         end
                        MISSING_ELSE
393                     
394                       end // always_comb
395                     
396                       logic [DataWidth-1:0] rd_data_main, rd_data_info;
397                       logic [InfoTypes-1:0][DataWidth-1:0] rd_nom_data_info;
398                     
399                       // data memory is requested whenver it's a transaction targetted at the data partition
400                       // OR if it's a bank erase
401                       logic data_mem_req;
402        1/1            assign data_mem_req = mem_req &
           Tests:       T1 T2 T3 
403                                             (mem_part == flash_ctrl_pkg::FlashPartData |
404                                              mem_bk_erase);
405                     
406                       prim_ram_1p #(
407                         .Width(DataWidth),
408                         .Depth(WordsPerBank),
409                         .DataBitsPerMask(DataWidth)
410                       ) u_mem (
411                         .clk_i,
412                         .req_i    (data_mem_req),
413                         .write_i  (mem_wr),
414                         .addr_i   (mem_addr),
415                         .wdata_i  (mem_wdata),
416                         .wmask_i  ({DataWidth{1'b1}}),
417                         .rdata_o  (rd_data_main),
418                         .cfg_i    ('0)
419                       );
420                     
421                       for (genvar info_type = 0; info_type < InfoTypes; info_type++) begin : gen_info_types
422                     
423                         // when info partitions are selected for bank erase, all info types are erased.
424                         // if NOT bank erase, then only the selected info partition is erased
425                         logic info_mem_req;
426        3/3              assign info_mem_req = mem_req &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
427                                               (mem_part == flash_ctrl_pkg::FlashPartInfo) &
428                                               ((mem_info_sel == info_type) | mem_bk_erase);
429                     
430                         prim_ram_1p #(
431                           .Width(DataWidth),
432                           .Depth(WordsPerInfoBank),
433                           .DataBitsPerMask(DataWidth)
434                         ) u_info_mem (
435                           .clk_i,
436                           .req_i    (info_mem_req),
437                           .write_i  (mem_wr),
438                           .addr_i   (mem_addr[0 +: InfoAddrW]),
439                           .wdata_i  (mem_wdata),
440                           .wmask_i  ({DataWidth{1'b1}}),
441                           .rdata_o  (rd_nom_data_info[info_type]),
442                           .cfg_i    ('0)
443                         );
444                       end
445                     
446        1/1            assign rd_data_info = rd_nom_data_info[info_sel_q];
           Tests:       T1 T2 T3 
447        1/1            assign rd_data_d    = rd_part_q == flash_ctrl_pkg::FlashPartData ? rd_data_main : rd_data_info;
           Tests:       T1 T2 T3 
448                     
449                       flash_ctrl_pkg::flash_prog_e unused_prog_type;
450        1/1            assign unused_prog_type = cmd_q.prog_type;
           Tests:       T1 T2 T3 
451                     
452                       logic unused_he;
453        1/1            assign unused_he = he_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank

	Total	Covered	Percent
Conditions	84	78	92.86
Logical	84	78	92.86
Non-Logical	0	0
Event	0	0

 LINE       152
 EXPRESSION ((rd_i | prog_i | pg_erase_i | bk_erase_i) & ((!init_busy_o)))
             --------------------1--------------------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T67,T68,T88
1	1	Covered	T1,T2,T3

 LINE       152
 SUB-EXPRESSION (rd_i | prog_i | pg_erase_i | bk_erase_i)
                 --1-   ---2--   -----3----   -----4----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T30,T31,T32
0	0	1	0	Covered	T9,T27,T28
0	1	0	0	Covered	T2,T4,T5
1	0	0	0	Covered	T1,T2,T3

 LINE       153
 EXPRESSION (ack & ((!init_busy_o)))
             -1-   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       175
 EXPRESSION (cmd_valid & cmd_q.rd)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       176
 EXPRESSION (cmd_valid & cmd_q.prog)
             ----1----   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       177
 EXPRESSION (cmd_valid & cmd_q.pg_erase)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T27,T28

 LINE       178
 EXPRESSION (cmd_valid & cmd_q.bk_erase)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T30,T31,T32

 LINE       181
 EXPRESSION (mem_req & ((~mem_wr)))
             ---1---   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION ((ReadLatency == 1) ? rd_data_d : rd_data_q)
             ---------1--------

-1-	Status	Tests
0	Covered	T49,T41,T79
1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (ReadLatency == 1)
                ---------1--------

-1-	Status	Tests
0	Covered	T49,T41,T79
1	Covered	T1,T2,T3

 LINE       274
 EXPRESSION (init_i && flash_power_ready_h_i && ((!flash_power_down_h_i)))
             ---1--    ----------2----------    ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Covered	T35,T67,T68
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       357
 EXPRESSION ((index_cnt < index_limit_q) || (time_cnt < time_limit_q))
             -------------1-------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T27,T28
0	1	Not Covered
1	0	Covered	T9,T27,T28

 LINE       390
 EXPRESSION (((!flash_power_ready_h_i)) || flash_power_down_h_i)
             -------------1------------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T35,T67,T68

 LINE       402
 EXPRESSION (mem_req & ((mem_part == FlashPartData) | mem_bk_erase))
             ---1---   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       402
 SUB-EXPRESSION ((mem_part == FlashPartData) | mem_bk_erase)
                 -------------1-------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T32,T80,T89
1	0	Covered	T1,T2,T3

 LINE       402
 SUB-EXPRESSION (mem_part == FlashPartData)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 0) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T11,T34
1	0	1	Covered	T2,T3,T5
1	1	0	Covered	T27,T36,T52
1	1	1	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 0) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T27,T36,T52
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 0)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 1) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T32,T80,T89
1	0	1	Covered	T52,T74,T61
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T52,T82,T83

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 1) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T30,T31,T32
1	0	Covered	T52,T74,T61

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T52,T74,T61

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 2) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T36,T84,T85
1	0	1	Covered	T27,T36,T52
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T27,T36,T52

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 2) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T30,T31,T32
1	0	Covered	T27,T36,T52

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 2)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T27,T36,T52

 LINE       447
 EXPRESSION ((rd_part_q == FlashPartData) ? rd_data_main : rd_data_info)
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       447
 SUB-EXPRESSION (rd_part_q == FlashPartData)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank

Summary for FSM :: st_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	16	15	93.75
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StErSuspend	356	Covered	T67,T69,T70
StErase	302	Covered	T9,T27,T28
StIdle	286	Covered	T1,T2,T3
StInit	275	Covered	T1,T2,T3
StProg	334	Covered	T2,T4,T5
StRead	296	Covered	T1,T2,T3
StReset	391	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StErSuspend->StIdle	379	Covered	T69,T70,T90
StErSuspend->StReset	391	Covered	T67
StErase->StErSuspend	356	Covered	T67,T69,T70
StErase->StIdle	364	Covered	T9,T27,T28
StErase->StReset	391	Covered	T35,T67,T86
StIdle->StErase	302	Covered	T9,T27,T28
StIdle->StRead	296	Covered	T1,T2,T3
StIdle->StReset	391	Covered	T1,T4,T59
StInit->StIdle	286	Covered	T1,T2,T3
StInit->StReset	391	Not Covered
StProg->StIdle	346	Covered	T2,T4,T5
StProg->StReset	391	Covered	T11,T35,T67
StRead->StIdle	327	Covered	T1,T2,T3
StRead->StProg	334	Covered	T2,T4,T5
StRead->StReset	391	Covered	T67,T71,T91
StReset->StInit	275	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank

	Line No.	Total	Covered	Percent
Branches		45	41	91.11
TERNARY	231	2	2	100.00
TERNARY	447	2	2	100.00
IF	189	2	2	100.00
IF	194	2	2	100.00
IF	210	3	3	100.00
IF	221	3	3	100.00
IF	236	8	7	87.50
CASE	271	21	18	85.71
IF	390	2	2	100.00

231          assign rd_data_o = ReadLatency == 1 ? rd_data_d : rd_data_q;
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T49,T41,T79

447          assign rd_data_d    = rd_part_q == flash_ctrl_pkg::FlashPartData ? rd_data_main : rd_data_info;
                                                                              -1-  
                                                                              ==>  
                                                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

189            if (!rst_ni) st_q <= StReset;
               -1-  
               ==>
190            else st_q <= st_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

194            if (!rst_ni) begin
               -1-  
195              time_limit_q  <= 'h0;
                 ==>
196              index_limit_q <= 'h0;
197              prog_pend_q   <= 'h0;
198              mem_rd_q      <= 'h0;
199            end else begin
200              time_limit_q  <= time_limit_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

210            if (!rst_ni) begin
               -1-  
211              rd_data_q <= '0;
                 ==>
212            end else if (mem_rd_q) begin
                        -2-  
213              rd_data_q <= rd_data_d;
                 ==>
214            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

221            if (!rst_ni) begin
               -1-  
222              rd_part_q <= flash_ctrl_pkg::FlashPartData;
                 ==>
223              info_sel_q <= '0;
224            end else if (mem_rd_d) begin
                        -2-  
225              rd_part_q <= cmd_q.part;
                 ==>
226              info_sel_q <= cmd_q.info_sel;
227            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

236            if (!rst_ni) begin
               -1-  
237              time_cnt  <= 'h0;
                 ==>
238              index_cnt <= 'h0;
239            end else begin
240              if (time_cnt_inc) time_cnt <= time_cnt + 1'b1;
                 -2-  
                 ==>
241              else if (time_cnt_set1) time_cnt <= 32'h1;
                      -3-  
                 ==>
242              else if (time_cnt_clr) time_cnt <= 32'h0;
                      -4-  
                 ==>
                 MISSING_ELSE
                 ==>
243        
244              if (index_cnt_inc) index_cnt <= index_cnt + 1'b1;
                 -5-  
                 ==>
245              else if (index_cnt_clr) index_cnt <= 32'h0;
                      -6-  
                 ==>
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	-	Not Covered
0	0	0	1	-	-	Covered	T1,T2,T3
0	0	0	0	-	-	Covered	T1,T2,T3
0	-	-	-	1	-	Covered	T1,T2,T3
0	-	-	-	0	1	Covered	T1,T2,T3
0	-	-	-	0	0	Covered	T1,T2,T3

271            unique case (st_q)
                      -1-  
272              StReset: begin
273                init_busy_o = 1'b1;
274                if (init_i && flash_power_ready_h_i && !flash_power_down_h_i) begin
                   -2-  
275                  st_d = StInit;
                     ==>
276                end
                   MISSING_ELSE
                   ==>
277              end
278        
279              // Emulate flash initilaization with a wait timer
280              StInit: begin
281                init_busy_o = 1'h1;
282                if (index_cnt < InitCycles) begin
                   -3-  
283                  st_d = StInit;
                     ==>
284                  index_cnt_inc = 1'b1;
285                end else begin
286                  st_d = StIdle;
                     ==>
287                  index_cnt_clr = 1'b1;
288                end
289              end
290        
291              StIdle: begin
292                if (rd_req) begin
                   -4-  
293                  pop_cmd = 1'b1;
                     ==>
294                  mem_req = 1'b1;
295                  time_cnt_inc = 1'b1;
296                  st_d = StRead;
297                end else if (prog_req) begin
                            -5-  
298                  mem_req = 1'b1;
                     ==>
299                  prog_pend_d = 1'b1;
300                  st_d = StRead;
301                end else if (pg_erase_req) begin
                            -6-  
302                  st_d = StErase;
                     ==>
303                  index_limit_d = WordsPerPage;
304                  time_limit_d = EraseLatency;
305                end else if (bk_erase_req) begin
                            -7-  
306                  st_d = StErase;
                     ==>
307                  index_limit_d = WordsPerBank;
308                  time_limit_d = BkEraseCycles;
309                end
                   MISSING_ELSE
                   ==>
310              end
311        
312              StRead: begin
313                if (time_cnt < ReadLatency) begin
                   -8-  
314                  time_cnt_inc = 1'b1;
                     ==>
315        
316                end else if (!prog_pend_q) begin
                            -9-  
317                  done_o = 1'b1;
318        
319                  // if another request already pending
320                  if (rd_req) begin
                     -10-  
321                    pop_cmd = 1'b1;
                       ==>
322                    mem_req = 1'b1;
323                    time_cnt_set1 = 1'b1;
324                    st_d = StRead;
325                  end else begin
326                    time_cnt_clr = 1'b1;
                       ==>
327                    st_d = StIdle;
328                  end
329        
330                end else if (prog_pend_q) begin
                            -11-  
331                  // this is the read performed before a program operation
332                  prog_pend_d = 1'b0;
                     ==>
333                  time_cnt_clr = 1'b1;
334                  st_d = StProg;
335                end
                   MISSING_ELSE
                   ==>
336              end
337        
338              StProg: begin
339                // if data is already 0, cannot program to 1 without erase
340                mem_wdata = cmd_q.prog_data & rd_data_q;
341                if (time_cnt < ProgLatency) begin
                   -12-  
342                  mem_req = 1'b1;
                     ==>
343                  mem_wr = 1'b1;
344                  time_cnt_inc = 1'b1;
345                end else begin
346                  st_d = StIdle;
                     ==>
347                  pop_cmd = 1'b1;
348                  done_o = cmd_q.prog_last;
349                  time_cnt_clr = 1'b1;
350                end
351              end
352        
353              StErase: begin
354                // Actual erasing of the page
355                if (erase_suspend_req_i) begin
                   -13-  
356                  st_d = StErSuspend;
                     ==>
357                end else if (index_cnt < index_limit_q || time_cnt < time_limit_q) begin
                            -14-  
358                  mem_req = 1'b1;
                     ==>
359                  mem_wr = 1'b1;
360                  mem_wdata = {DataWidth{1'b1}};
361                  time_cnt_inc = (time_cnt < time_limit_q);
362                  index_cnt_inc = (index_cnt < index_limit_q);
363                end else begin
364                  st_d = StIdle;
                     ==>
365                  pop_cmd = 1'b1;
366                  done_o = 1'b1;
367                  time_cnt_clr = 1'b1;
368                  index_cnt_clr = 1'b1;
369                end
370              end // case: StErase
371        
372              // The done can actually be signaled back in `StErase`, but move it
373              // to a different state to better model the ack_o/done_o timing separation
374              StErSuspend: begin
375                 done_o = 1'b1;
                    ==>
376                 pop_cmd = 1'b1;
377                 time_cnt_clr = 1'b1;
378                 index_cnt_clr = 1'b1;
379                 st_d = StIdle;
380              end
381        
382        
383              default: begin
384                st_d = StIdle;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
StReset	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReset	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StInit	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StInit	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
StIdle	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T9,T27,T28
StIdle	-	-	0	0	0	1	-	-	-	-	-	-	-	Covered	T30,T31,T32
StIdle	-	-	0	0	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRead	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T4,T5
StRead	-	-	-	-	-	-	0	1	1	-	-	-	-	Not Covered
StRead	-	-	-	-	-	-	0	1	0	-	-	-	-	Covered	T1,T2,T3
StRead	-	-	-	-	-	-	0	0	-	1	-	-	-	Covered	T2,T4,T5
StRead	-	-	-	-	-	-	0	0	-	0	-	-	-	Not Covered
StProg	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T2,T4,T5
StProg	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T4,T5
StErase	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T67,T69,T70
StErase	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T9,T27,T28
StErase	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T9,T27,T28
StErSuspend	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T67,T69,T70
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

390            if (!flash_power_ready_h_i || flash_power_down_h_i) begin
               -1-  
391              st_d = StReset;
                 ==>
392            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank

	Line No.	Total	Covered	Percent
TOTAL		142	137	96.48
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	181	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
ALWAYS	189	3	3	100.00
ALWAYS	194	9	9	100.00
ALWAYS	210	4	4	100.00
ALWAYS	221	6	6	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	236	13	12	92.31
ALWAYS	251	86	82	95.35
CONT_ASSIGN	402	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	453	1	1	100.00

126                     
127        1/1            assign cmd_d = '{
           Tests:       T1 T2 T3 
128                         rd :       rd_i,
129                         prog:      prog_i,
130                         prog_last: prog_last_i,
131                         prog_type: prog_type_i,
132                         pg_erase:  pg_erase_i,
133                         bk_erase:  bk_erase_i,
134                         addr:      addr_i,
135                         part:      part_i,
136                         info_sel:  info_sel_i,
137                         prog_data: prog_data_i
138                       };
139                     
140                       // for read transactions, in order to reduce latency, the
141                       // command fifo is popped early (before done_o).  This is to ensure that when
142                       // the current transaction is complete, during the same cycle
143                       // a new read can be issued. As a result, the command is popped
144                       // immediately after the read is issued, rather than waiting for
145                       // the read to be completed.  The same restrictions are not necessary
146                       // for program / erase, which do not have the same performance
147                       // requirements.
148                     
149                       // when the flash is going through init, do not accept any transactions
150                       logic wvalid;
151                       logic ack;
152        1/1            assign wvalid = (rd_i | prog_i | pg_erase_i | bk_erase_i) & !init_busy_o;
           Tests:       T1 T2 T3 
153        1/1            assign ack_o = ack & !init_busy_o;
           Tests:       T1 T2 T3 
154                     
155                       prim_fifo_sync #(
156                         .Width   ($bits(cmd_payload_t)),
157                         .Pass    (0),
158                         .Depth   (2)
159                       ) u_cmd_fifo (
160                         .clk_i,
161                         .rst_ni,
162                         .clr_i   (1'b0),
163                         .wvalid_i(wvalid),
164                         .wready_o(ack),
165                         .wdata_i (cmd_d),
166                         .depth_o (),
167                         .full_o (),
168                         .rvalid_o(cmd_valid),
169                         .rready_i(pop_cmd),
170                         .rdata_o (cmd_q),
171                         .err_o   ()
172                       );
173                     
174                       logic rd_req, prog_req, pg_erase_req, bk_erase_req;
175        1/1            assign rd_req = cmd_valid & cmd_q.rd;
           Tests:       T1 T2 T3 
176        1/1            assign prog_req = cmd_valid & cmd_q.prog;
           Tests:       T1 T2 T3 
177        1/1            assign pg_erase_req = cmd_valid & cmd_q.pg_erase;
           Tests:       T1 T2 T3 
178        1/1            assign bk_erase_req = cmd_valid & cmd_q.bk_erase;
           Tests:       T1 T2 T3 
179                     
180                       // for read / program operations, the index cnt should be 0
181        1/1            assign mem_rd_d = mem_req & ~mem_wr;
           Tests:       T1 T2 T3 
182        1/1            assign mem_addr = cmd_q.addr + index_cnt[AddrW-1:0];
           Tests:       T1 T2 T3 
183        1/1            assign mem_part = cmd_q.part;
           Tests:       T1 T2 T3 
184        1/1            assign mem_bk_erase = cmd_q.bk_erase;
           Tests:       T1 T2 T3 
185                     
186        1/1            assign mem_info_sel = cmd_q.info_sel;
           Tests:       T1 T2 T3 
187                     
188                       always_ff @(posedge clk_i or negedge rst_ni) begin
189        2/2              if (!rst_ni) st_q <= StReset;
           Tests:       T1 T2 T3  | T1 T2 T3 
190        1/1              else st_q <= st_d;
           Tests:       T1 T2 T3 
191                       end
192                     
193                       always_ff @(posedge clk_i or negedge rst_ni) begin
194        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
195        1/1                time_limit_q  <= 'h0;
           Tests:       T1 T2 T3 
196        1/1                index_limit_q <= 'h0;
           Tests:       T1 T2 T3 
197        1/1                prog_pend_q   <= 'h0;
           Tests:       T1 T2 T3 
198        1/1                mem_rd_q      <= 'h0;
           Tests:       T1 T2 T3 
199                         end else begin
200        1/1                time_limit_q  <= time_limit_d;
           Tests:       T1 T2 T3 
201        1/1                index_limit_q <= index_limit_d;
           Tests:       T1 T2 T3 
202        1/1                prog_pend_q   <= prog_pend_d;
           Tests:       T1 T2 T3 
203        1/1                mem_rd_q      <= mem_rd_d;
           Tests:       T1 T2 T3 
204                         end
205                       end
206                     
207                       // latch read data from emulated memories the cycle after a read
208                       logic [DataWidth-1:0] rd_data_q, rd_data_d;
209                       always_ff @(posedge clk_i or negedge rst_ni) begin
210        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
211        1/1                rd_data_q <= '0;
           Tests:       T1 T2 T3 
212        1/1              end else if (mem_rd_q) begin
           Tests:       T1 T2 T3 
213        1/1                rd_data_q <= rd_data_d;
           Tests:       T4 T16 T8 
214                         end
                        MISSING_ELSE
215                       end
216                     
217                       // latch partiton being read since the command fifo is popped early
218                       flash_ctrl_pkg::flash_part_e rd_part_q;
219                       logic [InfoTypesWidth-1:0] info_sel_q;
220                       always_ff @(posedge clk_i or negedge rst_ni) begin
221        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
222        1/1                rd_part_q <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
223        1/1                info_sel_q <= '0;
           Tests:       T1 T2 T3 
224        1/1              end else if (mem_rd_d) begin
           Tests:       T1 T2 T3 
225        1/1                rd_part_q <= cmd_q.part;
           Tests:       T4 T16 T8 
226        1/1                info_sel_q <= cmd_q.info_sel;
           Tests:       T4 T16 T8 
227                         end
                        MISSING_ELSE
228                       end
229                     
230                       // if read cycle is only 1, we can expose the unlatched data directly
231        1/1            assign rd_data_o = ReadLatency == 1 ? rd_data_d : rd_data_q;
           Tests:       T1 T2 T3 
232                     
233                       // prog_pend_q is necessary to emulate flash behavior that a bit written to 0 cannot be written
234                       // back to 1 without an erase
235                       always_ff @(posedge clk_i or negedge rst_ni) begin
236        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
237        1/1                time_cnt  <= 'h0;
           Tests:       T1 T2 T3 
238        1/1                index_cnt <= 'h0;
           Tests:       T1 T2 T3 
239                         end else begin
240        2/2                if (time_cnt_inc) time_cnt <= time_cnt + 1'b1;
           Tests:       T1 T2 T3  | T4 T16 T8 
241        1/2     ==>        else if (time_cnt_set1) time_cnt <= 32'h1;
           Tests:       T1 T2 T3 
242        2/2                else if (time_cnt_clr) time_cnt <= 32'h0;
           Tests:       T1 T2 T3  | T4 T16 T8 
                        MISSING_ELSE
243                     
244        2/2                if (index_cnt_inc) index_cnt <= index_cnt + 1'b1;
           Tests:       T1 T2 T3  | T1 T2 T3 
245        2/2                else if (index_cnt_clr) index_cnt <= 32'h0;
           Tests:       T1 T2 T3  | T1 T2 T3 
                        MISSING_ELSE
246                         end
247                       end
248                     
249                       always_comb begin
250                         // state
251        1/1              st_d             = st_q;
           Tests:       T1 T2 T3 
252                     
253                         // internally consumed signals
254        1/1              index_limit_d    = index_limit_q;
           Tests:       T1 T2 T3 
255        1/1              time_limit_d     = time_limit_q;
           Tests:       T1 T2 T3 
256        1/1              prog_pend_d      = prog_pend_q;
           Tests:       T1 T2 T3 
257        1/1              mem_req          = '0;
           Tests:       T1 T2 T3 
258        1/1              mem_wr           = '0;
           Tests:       T1 T2 T3 
259        1/1              mem_wdata        = '0;
           Tests:       T1 T2 T3 
260        1/1              time_cnt_inc     = '0;
           Tests:       T1 T2 T3 
261        1/1              time_cnt_clr     = '0;
           Tests:       T1 T2 T3 
262        1/1              time_cnt_set1    = '0;
           Tests:       T1 T2 T3 
263        1/1              index_cnt_inc    = '0;
           Tests:       T1 T2 T3 
264        1/1              index_cnt_clr    = '0;
           Tests:       T1 T2 T3 
265                     
266                         // i/o
267        1/1              init_busy_o      = '0;
           Tests:       T1 T2 T3 
268        1/1              pop_cmd          = '0;
           Tests:       T1 T2 T3 
269        1/1              done_o           = '0;
           Tests:       T1 T2 T3 
270                     
271        1/1              unique case (st_q)
           Tests:       T1 T2 T3 
272                           StReset: begin
273        1/1                  init_busy_o = 1'b1;
           Tests:       T1 T2 T3 
274        1/1                  if (init_i && flash_power_ready_h_i && !flash_power_down_h_i) begin
           Tests:       T1 T2 T3 
275        1/1                    st_d = StInit;
           Tests:       T1 T2 T3 
276                             end
                        MISSING_ELSE
277                           end
278                     
279                           // Emulate flash initilaization with a wait timer
280                           StInit: begin
281        1/1                  init_busy_o = 1'h1;
           Tests:       T1 T2 T3 
282        1/1                  if (index_cnt < InitCycles) begin
           Tests:       T1 T2 T3 
283        1/1                    st_d = StInit;
           Tests:       T1 T2 T3 
284        1/1                    index_cnt_inc = 1'b1;
           Tests:       T1 T2 T3 
285                             end else begin
286        1/1                    st_d = StIdle;
           Tests:       T1 T2 T3 
287        1/1                    index_cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
288                             end
289                           end
290                     
291                           StIdle: begin
292        1/1                  if (rd_req) begin
           Tests:       T1 T2 T3 
293        1/1                    pop_cmd = 1'b1;
           Tests:       T16 T8 T17 
294        1/1                    mem_req = 1'b1;
           Tests:       T16 T8 T17 
295        1/1                    time_cnt_inc = 1'b1;
           Tests:       T16 T8 T17 
296        1/1                    st_d = StRead;
           Tests:       T16 T8 T17 
297        1/1                  end else if (prog_req) begin
           Tests:       T1 T2 T3 
298        1/1                    mem_req = 1'b1;
           Tests:       T4 T33 T34 
299        1/1                    prog_pend_d = 1'b1;
           Tests:       T4 T33 T34 
300        1/1                    st_d = StRead;
           Tests:       T4 T33 T34 
301        1/1                  end else if (pg_erase_req) begin
           Tests:       T1 T2 T3 
302        1/1                    st_d = StErase;
           Tests:       T27 T28 T35 
303        1/1                    index_limit_d = WordsPerPage;
           Tests:       T27 T28 T35 
304        1/1                    time_limit_d = EraseLatency;
           Tests:       T27 T28 T35 
305        1/1                  end else if (bk_erase_req) begin
           Tests:       T1 T2 T3 
306        1/1                    st_d = StErase;
           Tests:       T29 T31 T32 
307        1/1                    index_limit_d = WordsPerBank;
           Tests:       T29 T31 T32 
308        1/1                    time_limit_d = BkEraseCycles;
           Tests:       T29 T31 T32 
309                             end
                        MISSING_ELSE
310                           end
311                     
312                           StRead: begin
313        1/1                  if (time_cnt < ReadLatency) begin
           Tests:       T4 T16 T8 
314        1/1                    time_cnt_inc = 1'b1;
           Tests:       T4 T33 T34 
315                     
316        1/1                  end else if (!prog_pend_q) begin
           Tests:       T4 T16 T8 
317        1/1                    done_o = 1'b1;
           Tests:       T16 T8 T17 
318                     
319                               // if another request already pending
320        1/1                    if (rd_req) begin
           Tests:       T16 T8 T17 
321        0/1     ==>              pop_cmd = 1'b1;
322        0/1     ==>              mem_req = 1'b1;
323        0/1     ==>              time_cnt_set1 = 1'b1;
324        0/1     ==>              st_d = StRead;
325                               end else begin
326        1/1                      time_cnt_clr = 1'b1;
           Tests:       T16 T8 T17 
327        1/1                      st_d = StIdle;
           Tests:       T16 T8 T17 
328                               end
329                     
330        1/1                  end else if (prog_pend_q) begin
           Tests:       T4 T33 T34 
331                               // this is the read performed before a program operation
332        1/1                    prog_pend_d = 1'b0;
           Tests:       T4 T33 T34 
333        1/1                    time_cnt_clr = 1'b1;
           Tests:       T4 T33 T34 
334        1/1                    st_d = StProg;
           Tests:       T4 T33 T34 
335                             end
                   ==>  MISSING_ELSE
336                           end
337                     
338                           StProg: begin
339                             // if data is already 0, cannot program to 1 without erase
340        1/1                  mem_wdata = cmd_q.prog_data & rd_data_q;
           Tests:       T4 T33 T34 
341        1/1                  if (time_cnt < ProgLatency) begin
           Tests:       T4 T33 T34 
342        1/1                    mem_req = 1'b1;
           Tests:       T4 T33 T34 
343        1/1                    mem_wr = 1'b1;
           Tests:       T4 T33 T34 
344        1/1                    time_cnt_inc = 1'b1;
           Tests:       T4 T33 T34 
345                             end else begin
346        1/1                    st_d = StIdle;
           Tests:       T4 T33 T34 
347        1/1                    pop_cmd = 1'b1;
           Tests:       T4 T33 T34 
348        1/1                    done_o = cmd_q.prog_last;
           Tests:       T4 T33 T34 
349        1/1                    time_cnt_clr = 1'b1;
           Tests:       T4 T33 T34 
350                             end
351                           end
352                     
353                           StErase: begin
354                             // Actual erasing of the page
355        1/1                  if (erase_suspend_req_i) begin
           Tests:       T27 T28 T35 
356        1/1                    st_d = StErSuspend;
           Tests:       T35 T68 T71 
357        1/1                  end else if (index_cnt < index_limit_q || time_cnt < time_limit_q) begin
           Tests:       T27 T28 T35 
358        1/1                    mem_req = 1'b1;
           Tests:       T27 T28 T35 
359        1/1                    mem_wr = 1'b1;
           Tests:       T27 T28 T35 
360        1/1                    mem_wdata = {DataWidth{1'b1}};
           Tests:       T27 T28 T35 
361        1/1                    time_cnt_inc = (time_cnt < time_limit_q);
           Tests:       T27 T28 T35 
362        1/1                    index_cnt_inc = (index_cnt < index_limit_q);
           Tests:       T27 T28 T35 
363                             end else begin
364        1/1                    st_d = StIdle;
           Tests:       T27 T28 T35 
365        1/1                    pop_cmd = 1'b1;
           Tests:       T27 T28 T35 
366        1/1                    done_o = 1'b1;
           Tests:       T27 T28 T35 
367        1/1                    time_cnt_clr = 1'b1;
           Tests:       T27 T28 T35 
368        1/1                    index_cnt_clr = 1'b1;
           Tests:       T27 T28 T35 
369                             end
370                           end // case: StErase
371                     
372                           // The done can actually be signaled back in `StErase`, but move it
373                           // to a different state to better model the ack_o/done_o timing separation
374                           StErSuspend: begin
375        1/1                   done_o = 1'b1;
           Tests:       T35 T68 T71 
376        1/1                   pop_cmd = 1'b1;
           Tests:       T35 T68 T71 
377        1/1                   time_cnt_clr = 1'b1;
           Tests:       T35 T68 T71 
378        1/1                   index_cnt_clr = 1'b1;
           Tests:       T35 T68 T71 
379        1/1                   st_d = StIdle;
           Tests:       T35 T68 T71 
380                           end
381                     
382                     
383                           default: begin
384                             st_d = StIdle;
385                           end
386                     
387                         endcase // unique case (st_q)
388                     
389                         // Emulate power down and power loss behavior
390        1/1              if (!flash_power_ready_h_i || flash_power_down_h_i) begin
           Tests:       T1 T2 T3 
391        1/1                st_d = StReset;
           Tests:       T1 T2 T3 
392                         end
                        MISSING_ELSE
393                     
394                       end // always_comb
395                     
396                       logic [DataWidth-1:0] rd_data_main, rd_data_info;
397                       logic [InfoTypes-1:0][DataWidth-1:0] rd_nom_data_info;
398                     
399                       // data memory is requested whenver it's a transaction targetted at the data partition
400                       // OR if it's a bank erase
401                       logic data_mem_req;
402        1/1            assign data_mem_req = mem_req &
           Tests:       T1 T2 T3 
403                                             (mem_part == flash_ctrl_pkg::FlashPartData |
404                                              mem_bk_erase);
405                     
406                       prim_ram_1p #(
407                         .Width(DataWidth),
408                         .Depth(WordsPerBank),
409                         .DataBitsPerMask(DataWidth)
410                       ) u_mem (
411                         .clk_i,
412                         .req_i    (data_mem_req),
413                         .write_i  (mem_wr),
414                         .addr_i   (mem_addr),
415                         .wdata_i  (mem_wdata),
416                         .wmask_i  ({DataWidth{1'b1}}),
417                         .rdata_o  (rd_data_main),
418                         .cfg_i    ('0)
419                       );
420                     
421                       for (genvar info_type = 0; info_type < InfoTypes; info_type++) begin : gen_info_types
422                     
423                         // when info partitions are selected for bank erase, all info types are erased.
424                         // if NOT bank erase, then only the selected info partition is erased
425                         logic info_mem_req;
426        3/3              assign info_mem_req = mem_req &
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
427                                               (mem_part == flash_ctrl_pkg::FlashPartInfo) &
428                                               ((mem_info_sel == info_type) | mem_bk_erase);
429                     
430                         prim_ram_1p #(
431                           .Width(DataWidth),
432                           .Depth(WordsPerInfoBank),
433                           .DataBitsPerMask(DataWidth)
434                         ) u_info_mem (
435                           .clk_i,
436                           .req_i    (info_mem_req),
437                           .write_i  (mem_wr),
438                           .addr_i   (mem_addr[0 +: InfoAddrW]),
439                           .wdata_i  (mem_wdata),
440                           .wmask_i  ({DataWidth{1'b1}}),
441                           .rdata_o  (rd_nom_data_info[info_type]),
442                           .cfg_i    ('0)
443                         );
444                       end
445                     
446        1/1            assign rd_data_info = rd_nom_data_info[info_sel_q];
           Tests:       T1 T2 T3 
447        1/1            assign rd_data_d    = rd_part_q == flash_ctrl_pkg::FlashPartData ? rd_data_main : rd_data_info;
           Tests:       T1 T2 T3 
448                     
449                       flash_ctrl_pkg::flash_prog_e unused_prog_type;
450        1/1            assign unused_prog_type = cmd_q.prog_type;
           Tests:       T1 T2 T3 
451                     
452                       logic unused_he;
453        1/1            assign unused_he = he_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank

	Total	Covered	Percent
Conditions	84	78	92.86
Logical	84	78	92.86
Non-Logical	0	0
Event	0	0

 LINE       152
 EXPRESSION ((rd_i | prog_i | pg_erase_i | bk_erase_i) & ((!init_busy_o)))
             --------------------1--------------------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T68,T71,T88
1	1	Covered	T4,T16,T8

 LINE       152
 SUB-EXPRESSION (rd_i | prog_i | pg_erase_i | bk_erase_i)
                 --1-   ---2--   -----3----   -----4----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T29,T31,T32
0	0	1	0	Covered	T27,T28,T35
0	1	0	0	Covered	T4,T33,T34
1	0	0	0	Covered	T16,T8,T17

 LINE       153
 EXPRESSION (ack & ((!init_busy_o)))
             -1-   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T33,T36
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       175
 EXPRESSION (cmd_valid & cmd_q.rd)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T33,T34
1	1	Covered	T16,T8,T17

 LINE       176
 EXPRESSION (cmd_valid & cmd_q.prog)
             ----1----   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T8,T17
1	1	Covered	T4,T33,T34

 LINE       177
 EXPRESSION (cmd_valid & cmd_q.pg_erase)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T16,T8
1	1	Covered	T27,T28,T35

 LINE       178
 EXPRESSION (cmd_valid & cmd_q.bk_erase)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T16,T8
1	1	Covered	T29,T31,T32

 LINE       181
 EXPRESSION (mem_req & ((~mem_wr)))
             ---1---   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T33,T34
1	1	Covered	T4,T16,T8

 LINE       231
 EXPRESSION ((ReadLatency == 1) ? rd_data_d : rd_data_q)
             ---------1--------

-1-	Status	Tests
0	Covered	T49,T41,T79
1	Covered	T1,T2,T3

 LINE       231
 SUB-EXPRESSION (ReadLatency == 1)
                ---------1--------

-1-	Status	Tests
0	Covered	T49,T41,T79
1	Covered	T1,T2,T3

 LINE       274
 EXPRESSION (init_i && flash_power_ready_h_i && ((!flash_power_down_h_i)))
             ---1--    ----------2----------    ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Covered	T35,T67,T68
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       357
 EXPRESSION ((index_cnt < index_limit_q) || (time_cnt < time_limit_q))
             -------------1-------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T35
0	1	Not Covered
1	0	Covered	T27,T28,T35

 LINE       390
 EXPRESSION (((!flash_power_ready_h_i)) || flash_power_down_h_i)
             -------------1------------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T35,T67,T68

 LINE       402
 EXPRESSION (mem_req & ((mem_part == FlashPartData) | mem_bk_erase))
             ---1---   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T27,T28,T92
1	1	Covered	T4,T16,T8

 LINE       402
 SUB-EXPRESSION ((mem_part == FlashPartData) | mem_bk_erase)
                 -------------1-------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T92
0	1	Covered	T32,T81,T93
1	0	Covered	T1,T2,T3

 LINE       402
 SUB-EXPRESSION (mem_part == FlashPartData)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 0) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T28,T92,T94
1	0	1	Covered	T4,T16,T8
1	1	0	Covered	T39,T94,T95
1	1	1	Covered	T27,T28,T92

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T27,T28,T92

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 0) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T27,T36,T52
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 0)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 1) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T32,T81,T96
1	0	1	Covered	T52,T74,T29
1	1	0	Covered	T27,T28,T92
1	1	1	Covered	T32,T81,T97

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T27,T28,T92

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 1) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T31,T32
1	0	Covered	T52,T74,T61

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T52,T74,T61

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 2) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T39,T95,T32
1	0	1	Covered	T27,T36,T52
1	1	0	Covered	T27,T28,T92
1	1	1	Covered	T39,T94,T95

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T27,T28,T92

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 2) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T31,T32
1	0	Covered	T27,T36,T52

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 2)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T27,T36,T52

 LINE       447
 EXPRESSION ((rd_part_q == FlashPartData) ? rd_data_main : rd_data_info)
             --------------1-------------

-1-	Status	Tests
0	Covered	T27,T28,T92
1	Covered	T1,T2,T3

 LINE       447
 SUB-EXPRESSION (rd_part_q == FlashPartData)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank

Summary for FSM :: st_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	16	15	93.75
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StErSuspend	356	Covered	T35,T68,T71
StErase	302	Covered	T27,T28,T35
StIdle	286	Covered	T1,T2,T3
StInit	275	Covered	T1,T2,T3
StProg	334	Covered	T4,T33,T34
StRead	296	Covered	T4,T16,T8
StReset	391	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StErSuspend->StIdle	379	Covered	T35,T69,T70
StErSuspend->StReset	391	Covered	T68,T71,T88
StErase->StErSuspend	356	Covered	T35,T68,T71
StErase->StIdle	364	Covered	T27,T28,T35
StErase->StReset	391	Covered	T35,T67,T68
StIdle->StErase	302	Covered	T27,T28,T35
StIdle->StRead	296	Covered	T4,T16,T8
StIdle->StReset	391	Covered	T1,T4,T59
StInit->StIdle	286	Covered	T1,T2,T3
StInit->StReset	391	Not Covered
StProg->StIdle	346	Covered	T4,T33,T34
StProg->StReset	391	Covered	T35,T67,T68
StRead->StIdle	327	Covered	T16,T8,T17
StRead->StProg	334	Covered	T4,T33,T34
StRead->StReset	391	Covered	T87,T71
StReset->StInit	275	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank

	Line No.	Total	Covered	Percent
Branches		45	41	91.11
TERNARY	231	2	2	100.00
TERNARY	447	2	2	100.00
IF	189	2	2	100.00
IF	194	2	2	100.00
IF	210	3	3	100.00
IF	221	3	3	100.00
IF	236	8	7	87.50
CASE	271	21	18	85.71
IF	390	2	2	100.00

231          assign rd_data_o = ReadLatency == 1 ? rd_data_d : rd_data_q;
                                                 -1-  
                                                 ==>  
                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T49,T41,T79

447          assign rd_data_d    = rd_part_q == flash_ctrl_pkg::FlashPartData ? rd_data_main : rd_data_info;
                                                                              -1-  
                                                                              ==>  
                                                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T27,T28,T92

189            if (!rst_ni) st_q <= StReset;
               -1-  
               ==>
190            else st_q <= st_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

194            if (!rst_ni) begin
               -1-  
195              time_limit_q  <= 'h0;
                 ==>
196              index_limit_q <= 'h0;
197              prog_pend_q   <= 'h0;
198              mem_rd_q      <= 'h0;
199            end else begin
200              time_limit_q  <= time_limit_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

210            if (!rst_ni) begin
               -1-  
211              rd_data_q <= '0;
                 ==>
212            end else if (mem_rd_q) begin
                        -2-  
213              rd_data_q <= rd_data_d;
                 ==>
214            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T16,T8
0	0	Covered	T1,T2,T3

221            if (!rst_ni) begin
               -1-  
222              rd_part_q <= flash_ctrl_pkg::FlashPartData;
                 ==>
223              info_sel_q <= '0;
224            end else if (mem_rd_d) begin
                        -2-  
225              rd_part_q <= cmd_q.part;
                 ==>
226              info_sel_q <= cmd_q.info_sel;
227            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T16,T8
0	0	Covered	T1,T2,T3

236            if (!rst_ni) begin
               -1-  
237              time_cnt  <= 'h0;
                 ==>
238              index_cnt <= 'h0;
239            end else begin
240              if (time_cnt_inc) time_cnt <= time_cnt + 1'b1;
                 -2-  
                 ==>
241              else if (time_cnt_set1) time_cnt <= 32'h1;
                      -3-  
                 ==>
242              else if (time_cnt_clr) time_cnt <= 32'h0;
                      -4-  
                 ==>
                 MISSING_ELSE
                 ==>
243        
244              if (index_cnt_inc) index_cnt <= index_cnt + 1'b1;
                 -5-  
                 ==>
245              else if (index_cnt_clr) index_cnt <= 32'h0;
                      -6-  
                 ==>
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T4,T16,T8
0	0	1	-	-	-	Not Covered
0	0	0	1	-	-	Covered	T4,T16,T8
0	0	0	0	-	-	Covered	T1,T2,T3
0	-	-	-	1	-	Covered	T1,T2,T3
0	-	-	-	0	1	Covered	T1,T2,T3
0	-	-	-	0	0	Covered	T1,T2,T3

271            unique case (st_q)
                      -1-  
272              StReset: begin
273                init_busy_o = 1'b1;
274                if (init_i && flash_power_ready_h_i && !flash_power_down_h_i) begin
                   -2-  
275                  st_d = StInit;
                     ==>
276                end
                   MISSING_ELSE
                   ==>
277              end
278        
279              // Emulate flash initilaization with a wait timer
280              StInit: begin
281                init_busy_o = 1'h1;
282                if (index_cnt < InitCycles) begin
                   -3-  
283                  st_d = StInit;
                     ==>
284                  index_cnt_inc = 1'b1;
285                end else begin
286                  st_d = StIdle;
                     ==>
287                  index_cnt_clr = 1'b1;
288                end
289              end
290        
291              StIdle: begin
292                if (rd_req) begin
                   -4-  
293                  pop_cmd = 1'b1;
                     ==>
294                  mem_req = 1'b1;
295                  time_cnt_inc = 1'b1;
296                  st_d = StRead;
297                end else if (prog_req) begin
                            -5-  
298                  mem_req = 1'b1;
                     ==>
299                  prog_pend_d = 1'b1;
300                  st_d = StRead;
301                end else if (pg_erase_req) begin
                            -6-  
302                  st_d = StErase;
                     ==>
303                  index_limit_d = WordsPerPage;
304                  time_limit_d = EraseLatency;
305                end else if (bk_erase_req) begin
                            -7-  
306                  st_d = StErase;
                     ==>
307                  index_limit_d = WordsPerBank;
308                  time_limit_d = BkEraseCycles;
309                end
                   MISSING_ELSE
                   ==>
310              end
311        
312              StRead: begin
313                if (time_cnt < ReadLatency) begin
                   -8-  
314                  time_cnt_inc = 1'b1;
                     ==>
315        
316                end else if (!prog_pend_q) begin
                            -9-  
317                  done_o = 1'b1;
318        
319                  // if another request already pending
320                  if (rd_req) begin
                     -10-  
321                    pop_cmd = 1'b1;
                       ==>
322                    mem_req = 1'b1;
323                    time_cnt_set1 = 1'b1;
324                    st_d = StRead;
325                  end else begin
326                    time_cnt_clr = 1'b1;
                       ==>
327                    st_d = StIdle;
328                  end
329        
330                end else if (prog_pend_q) begin
                            -11-  
331                  // this is the read performed before a program operation
332                  prog_pend_d = 1'b0;
                     ==>
333                  time_cnt_clr = 1'b1;
334                  st_d = StProg;
335                end
                   MISSING_ELSE
                   ==>
336              end
337        
338              StProg: begin
339                // if data is already 0, cannot program to 1 without erase
340                mem_wdata = cmd_q.prog_data & rd_data_q;
341                if (time_cnt < ProgLatency) begin
                   -12-  
342                  mem_req = 1'b1;
                     ==>
343                  mem_wr = 1'b1;
344                  time_cnt_inc = 1'b1;
345                end else begin
346                  st_d = StIdle;
                     ==>
347                  pop_cmd = 1'b1;
348                  done_o = cmd_q.prog_last;
349                  time_cnt_clr = 1'b1;
350                end
351              end
352        
353              StErase: begin
354                // Actual erasing of the page
355                if (erase_suspend_req_i) begin
                   -13-  
356                  st_d = StErSuspend;
                     ==>
357                end else if (index_cnt < index_limit_q || time_cnt < time_limit_q) begin
                            -14-  
358                  mem_req = 1'b1;
                     ==>
359                  mem_wr = 1'b1;
360                  mem_wdata = {DataWidth{1'b1}};
361                  time_cnt_inc = (time_cnt < time_limit_q);
362                  index_cnt_inc = (index_cnt < index_limit_q);
363                end else begin
364                  st_d = StIdle;
                     ==>
365                  pop_cmd = 1'b1;
366                  done_o = 1'b1;
367                  time_cnt_clr = 1'b1;
368                  index_cnt_clr = 1'b1;
369                end
370              end // case: StErase
371        
372              // The done can actually be signaled back in `StErase`, but move it
373              // to a different state to better model the ack_o/done_o timing separation
374              StErSuspend: begin
375                 done_o = 1'b1;
                    ==>
376                 pop_cmd = 1'b1;
377                 time_cnt_clr = 1'b1;
378                 index_cnt_clr = 1'b1;
379                 st_d = StIdle;
380              end
381        
382        
383              default: begin
384                st_d = StIdle;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
StReset	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReset	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StInit	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StInit	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T16,T8,T17
StIdle	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T33,T34
StIdle	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T27,T28,T35
StIdle	-	-	0	0	0	1	-	-	-	-	-	-	-	Covered	T29,T31,T32
StIdle	-	-	0	0	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRead	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T33,T34
StRead	-	-	-	-	-	-	0	1	1	-	-	-	-	Not Covered
StRead	-	-	-	-	-	-	0	1	0	-	-	-	-	Covered	T16,T8,T17
StRead	-	-	-	-	-	-	0	0	-	1	-	-	-	Covered	T4,T33,T34
StRead	-	-	-	-	-	-	0	0	-	0	-	-	-	Not Covered
StProg	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T33,T34
StProg	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T4,T33,T34
StErase	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T35,T68,T71
StErase	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T27,T28,T35
StErase	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T27,T28,T35
StErSuspend	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T35,T68,T71
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

390            if (!flash_power_ready_h_i || flash_power_down_h_i) begin
               -1-  
391              st_d = StReset;
                 ==>
392            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3