Line Coverage for Module :
flash_ctrl_phy_cov_if
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 18 | 18 | 100.00 |
| CONT_ASSIGN | 24 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| ALWAYS | 32 | 8 | 8 | 100.00 |
| ALWAYS | 43 | 4 | 4 | 100.00 |
| ALWAYS | 56 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 63 | 1 | 1 | 100.00 |
23 logic any_req;
24 1/1 assign any_req = rd_req || prog_req || pg_erase_req || bk_erase_req;
Tests: T1 T2 T3
25 logic any_vld_req;
26 1/1 assign any_vld_req = any_req && ack;
Tests: T1 T2 T3
27
28 // Decode current command
29 typedef enum logic[1:0] {READ, PROG, ERASE, NONE} cmd_e;
30 cmd_e cur_cmd;
31 always_comb begin
32 1/1 cur_cmd = NONE;
Tests: T1 T2 T3
33 1/1 if (any_vld_req) begin
Tests: T1 T2 T3
34 2/2 if (rd_req) cur_cmd = READ;
Tests: T1 T2 T3 | T1 T2 T3
35 2/2 else if (prog_req) cur_cmd = PROG;
Tests: T2 T4 T5 | T2 T4 T5
36 2/2 else if (pg_erase_req || bk_erase_req) cur_cmd = ERASE;
Tests: T9 T27 T28 | T9 T27 T28
==> MISSING_ELSE
37 end
MISSING_ELSE
38 end
39
40 // previous command
41 cmd_e prv_cmd_q;
42 always @(posedge clk_i) begin
43 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
44 1/1 prv_cmd_q <= NONE;
Tests: T1 T2 T3
45 end else begin
46 1/1 if (any_vld_req) begin
Tests: T1 T2 T3
47 1/1 prv_cmd_q <= cur_cmd;
Tests: T1 T2 T3
48 end
MISSING_ELSE
49 end
50 end
51
52 // command interval counter
53 // couter will be saturated when it hits maxium
54 bit [31:0] idle_cnt;
55 always @(posedge clk_i) begin
56 2/2 if (!rst_ni || !rd_buf_en) idle_cnt <= 0;
Tests: T1 T2 T3 | T1 T2 T3
57 1/1 else idle_cnt <= (any_vld_req)? 0 :
Tests: T1 T2 T3
58 (idle_cnt == 32'hffff_ffff)? 32'hffff_ffff : idle_cnt + 32'h1;
59 end
60
61 // back to back read sequence
62 logic b2b_read;
63 1/1 assign b2b_read = (cur_cmd == READ && prv_cmd_q == READ);
Tests: T1 T2 T3
Cond Coverage for Module :
flash_ctrl_phy_cov_if
| Total | Covered | Percent |
|---|
| Conditions | 27 | 23 | 85.19 |
| Logical | 27 | 23 | 85.19 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 24
EXPRESSION (rd_req || prog_req || pg_erase_req || bk_erase_req)
---1-- ----2--- ------3----- ------4-----
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 1 | Covered | T29,T30,T31 |
| 0 | 0 | 1 | 0 | Covered | T9,T27,T28 |
| 0 | 1 | 0 | 0 | Covered | T2,T4,T5 |
| 1 | 0 | 0 | 0 | Covered | T1,T2,T3 |
LINE 26
EXPRESSION (any_req && ack)
---1--- -2-
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T4,T5 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 36
EXPRESSION (pg_erase_req || bk_erase_req)
------1----- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Covered | T29,T30,T31 |
| 1 | 0 | Covered | T9,T27,T28 |
LINE 56
EXPRESSION (((!rst_ni)) || ((!rd_buf_en)))
-----1----- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
LINE 57
EXPRESSION (any_vld_req ? 0 : ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1))))
-----1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 57
SUB-EXPRESSION ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1)))
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 57
SUB-EXPRESSION (idle_cnt == 32'hffffffff)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 63
EXPRESSION ((cur_cmd == READ) && (prv_cmd_q == READ))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 63
SUB-EXPRESSION (cur_cmd == READ)
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 63
SUB-EXPRESSION (prv_cmd_q == READ)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
flash_ctrl_phy_cov_if
| Line No. | Total | Covered | Percent |
| Branches |
|
12 |
10 |
83.33 |
| IF |
33 |
5 |
4 |
80.00 |
| IF |
43 |
3 |
3 |
100.00 |
| IF |
56 |
4 |
3 |
75.00 |
33 if (any_vld_req) begin
-1-
34 if (rd_req) cur_cmd = READ;
-2-
==>
35 else if (prog_req) cur_cmd = PROG;
-3-
==>
36 else if (pg_erase_req || bk_erase_req) cur_cmd = ERASE;
-4-
==>
MISSING_ELSE
==>
37 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
1 |
- |
- |
Covered |
T1,T2,T3 |
| 1 |
0 |
1 |
- |
Covered |
T2,T4,T5 |
| 1 |
0 |
0 |
1 |
Covered |
T9,T27,T28 |
| 1 |
0 |
0 |
0 |
Not Covered |
|
| 0 |
- |
- |
- |
Covered |
T1,T2,T3 |
43 if (!rst_ni) begin
-1-
44 prv_cmd_q <= NONE;
==>
45 end else begin
46 if (any_vld_req) begin
-2-
47 prv_cmd_q <= cur_cmd;
==>
48 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni || !rd_buf_en) idle_cnt <= 0;
-1-
==>
57 else idle_cnt <= (any_vld_req)? 0 :
-2-
==>
58 (idle_cnt == 32'hffff_ffff)? 32'hffff_ffff : idle_cnt + 32'h1;
-3-
==>
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T2,T3,T4 |
| 0 |
0 |
1 |
Not Covered |
|
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 18 | 18 | 100.00 |
| CONT_ASSIGN | 24 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| ALWAYS | 32 | 8 | 8 | 100.00 |
| ALWAYS | 43 | 4 | 4 | 100.00 |
| ALWAYS | 56 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 63 | 1 | 1 | 100.00 |
23 logic any_req;
24 1/1 assign any_req = rd_req || prog_req || pg_erase_req || bk_erase_req;
Tests: T1 T2 T3
25 logic any_vld_req;
26 1/1 assign any_vld_req = any_req && ack;
Tests: T1 T2 T3
27
28 // Decode current command
29 typedef enum logic[1:0] {READ, PROG, ERASE, NONE} cmd_e;
30 cmd_e cur_cmd;
31 always_comb begin
32 1/1 cur_cmd = NONE;
Tests: T1 T2 T3
33 1/1 if (any_vld_req) begin
Tests: T1 T2 T3
34 2/2 if (rd_req) cur_cmd = READ;
Tests: T1 T2 T3 | T1 T2 T3
35 2/2 else if (prog_req) cur_cmd = PROG;
Tests: T2 T4 T5 | T2 T4 T5
36 2/2 else if (pg_erase_req || bk_erase_req) cur_cmd = ERASE;
Tests: T9 T27 T28 | T9 T27 T28
==> MISSING_ELSE
37 end
MISSING_ELSE
38 end
39
40 // previous command
41 cmd_e prv_cmd_q;
42 always @(posedge clk_i) begin
43 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
44 1/1 prv_cmd_q <= NONE;
Tests: T1 T2 T3
45 end else begin
46 1/1 if (any_vld_req) begin
Tests: T1 T2 T3
47 1/1 prv_cmd_q <= cur_cmd;
Tests: T1 T2 T3
48 end
MISSING_ELSE
49 end
50 end
51
52 // command interval counter
53 // couter will be saturated when it hits maxium
54 bit [31:0] idle_cnt;
55 always @(posedge clk_i) begin
56 2/2 if (!rst_ni || !rd_buf_en) idle_cnt <= 0;
Tests: T1 T2 T3 | T1 T2 T3
57 1/1 else idle_cnt <= (any_vld_req)? 0 :
Tests: T1 T2 T3
58 (idle_cnt == 32'hffff_ffff)? 32'hffff_ffff : idle_cnt + 32'h1;
59 end
60
61 // back to back read sequence
62 logic b2b_read;
63 1/1 assign b2b_read = (cur_cmd == READ && prv_cmd_q == READ);
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if
| Total | Covered | Percent |
|---|
| Conditions | 27 | 23 | 85.19 |
| Logical | 27 | 23 | 85.19 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 24
EXPRESSION (rd_req || prog_req || pg_erase_req || bk_erase_req)
---1-- ----2--- ------3----- ------4-----
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 1 | Covered | T30,T31,T32 |
| 0 | 0 | 1 | 0 | Covered | T9,T27,T28 |
| 0 | 1 | 0 | 0 | Covered | T2,T4,T5 |
| 1 | 0 | 0 | 0 | Covered | T1,T2,T3 |
LINE 26
EXPRESSION (any_req && ack)
---1--- -2-
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T5,T9 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 36
EXPRESSION (pg_erase_req || bk_erase_req)
------1----- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Covered | T30,T31,T32 |
| 1 | 0 | Covered | T9,T27,T28 |
LINE 56
EXPRESSION (((!rst_ni)) || ((!rd_buf_en)))
-----1----- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
LINE 57
EXPRESSION (any_vld_req ? 0 : ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1))))
-----1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 57
SUB-EXPRESSION ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1)))
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 57
SUB-EXPRESSION (idle_cnt == 32'hffffffff)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 63
EXPRESSION ((cur_cmd == READ) && (prv_cmd_q == READ))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 63
SUB-EXPRESSION (cur_cmd == READ)
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 63
SUB-EXPRESSION (prv_cmd_q == READ)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if
| Line No. | Total | Covered | Percent |
| Branches |
|
12 |
10 |
83.33 |
| IF |
33 |
5 |
4 |
80.00 |
| IF |
43 |
3 |
3 |
100.00 |
| IF |
56 |
4 |
3 |
75.00 |
33 if (any_vld_req) begin
-1-
34 if (rd_req) cur_cmd = READ;
-2-
==>
35 else if (prog_req) cur_cmd = PROG;
-3-
==>
36 else if (pg_erase_req || bk_erase_req) cur_cmd = ERASE;
-4-
==>
MISSING_ELSE
==>
37 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
1 |
- |
- |
Covered |
T1,T2,T3 |
| 1 |
0 |
1 |
- |
Covered |
T2,T4,T5 |
| 1 |
0 |
0 |
1 |
Covered |
T9,T27,T28 |
| 1 |
0 |
0 |
0 |
Not Covered |
|
| 0 |
- |
- |
- |
Covered |
T1,T2,T3 |
43 if (!rst_ni) begin
-1-
44 prv_cmd_q <= NONE;
==>
45 end else begin
46 if (any_vld_req) begin
-2-
47 prv_cmd_q <= cur_cmd;
==>
48 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni || !rd_buf_en) idle_cnt <= 0;
-1-
==>
57 else idle_cnt <= (any_vld_req)? 0 :
-2-
==>
58 (idle_cnt == 32'hffff_ffff)? 32'hffff_ffff : idle_cnt + 32'h1;
-3-
==>
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T2,T3,T4 |
| 0 |
0 |
1 |
Not Covered |
|
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 18 | 18 | 100.00 |
| CONT_ASSIGN | 24 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| ALWAYS | 32 | 8 | 8 | 100.00 |
| ALWAYS | 43 | 4 | 4 | 100.00 |
| ALWAYS | 56 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 63 | 1 | 1 | 100.00 |
23 logic any_req;
24 1/1 assign any_req = rd_req || prog_req || pg_erase_req || bk_erase_req;
Tests: T1 T2 T3
25 logic any_vld_req;
26 1/1 assign any_vld_req = any_req && ack;
Tests: T1 T2 T3
27
28 // Decode current command
29 typedef enum logic[1:0] {READ, PROG, ERASE, NONE} cmd_e;
30 cmd_e cur_cmd;
31 always_comb begin
32 1/1 cur_cmd = NONE;
Tests: T1 T2 T3
33 1/1 if (any_vld_req) begin
Tests: T1 T2 T3
34 2/2 if (rd_req) cur_cmd = READ;
Tests: T4 T16 T8 | T16 T8 T17
35 2/2 else if (prog_req) cur_cmd = PROG;
Tests: T4 T33 T34 | T4 T33 T34
36 2/2 else if (pg_erase_req || bk_erase_req) cur_cmd = ERASE;
Tests: T27 T28 T35 | T27 T28 T35
==> MISSING_ELSE
37 end
MISSING_ELSE
38 end
39
40 // previous command
41 cmd_e prv_cmd_q;
42 always @(posedge clk_i) begin
43 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
44 1/1 prv_cmd_q <= NONE;
Tests: T1 T2 T3
45 end else begin
46 1/1 if (any_vld_req) begin
Tests: T1 T2 T3
47 1/1 prv_cmd_q <= cur_cmd;
Tests: T4 T16 T8
48 end
MISSING_ELSE
49 end
50 end
51
52 // command interval counter
53 // couter will be saturated when it hits maxium
54 bit [31:0] idle_cnt;
55 always @(posedge clk_i) begin
56 2/2 if (!rst_ni || !rd_buf_en) idle_cnt <= 0;
Tests: T1 T2 T3 | T1 T2 T3
57 1/1 else idle_cnt <= (any_vld_req)? 0 :
Tests: T1 T2 T3
58 (idle_cnt == 32'hffff_ffff)? 32'hffff_ffff : idle_cnt + 32'h1;
59 end
60
61 // back to back read sequence
62 logic b2b_read;
63 1/1 assign b2b_read = (cur_cmd == READ && prv_cmd_q == READ);
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if
| Total | Covered | Percent |
|---|
| Conditions | 27 | 23 | 85.19 |
| Logical | 27 | 23 | 85.19 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 24
EXPRESSION (rd_req || prog_req || pg_erase_req || bk_erase_req)
---1-- ----2--- ------3----- ------4-----
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 1 | Covered | T29,T31,T32 |
| 0 | 0 | 1 | 0 | Covered | T27,T28,T35 |
| 0 | 1 | 0 | 0 | Covered | T4,T33,T34 |
| 1 | 0 | 0 | 0 | Covered | T16,T8,T17 |
LINE 26
EXPRESSION (any_req && ack)
---1--- -2-
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T33,T36 |
| 1 | 1 | Covered | T4,T16,T8 |
LINE 36
EXPRESSION (pg_erase_req || bk_erase_req)
------1----- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Covered | T29,T31,T32 |
| 1 | 0 | Covered | T27,T28,T35 |
LINE 56
EXPRESSION (((!rst_ni)) || ((!rd_buf_en)))
-----1----- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
LINE 57
EXPRESSION (any_vld_req ? 0 : ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1))))
-----1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T16,T8 |
LINE 57
SUB-EXPRESSION ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1)))
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 57
SUB-EXPRESSION (idle_cnt == 32'hffffffff)
-------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 63
EXPRESSION ((cur_cmd == READ) && (prv_cmd_q == READ))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T16,T8,T17 |
| 1 | 0 | Covered | T16,T8,T17 |
| 1 | 1 | Covered | T16,T8,T17 |
LINE 63
SUB-EXPRESSION (cur_cmd == READ)
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T16,T8,T17 |
LINE 63
SUB-EXPRESSION (prv_cmd_q == READ)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T16,T8,T17 |
Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if
| Line No. | Total | Covered | Percent |
| Branches |
|
12 |
10 |
83.33 |
| IF |
33 |
5 |
4 |
80.00 |
| IF |
43 |
3 |
3 |
100.00 |
| IF |
56 |
4 |
3 |
75.00 |
33 if (any_vld_req) begin
-1-
34 if (rd_req) cur_cmd = READ;
-2-
==>
35 else if (prog_req) cur_cmd = PROG;
-3-
==>
36 else if (pg_erase_req || bk_erase_req) cur_cmd = ERASE;
-4-
==>
MISSING_ELSE
==>
37 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
1 |
- |
- |
Covered |
T16,T8,T17 |
| 1 |
0 |
1 |
- |
Covered |
T4,T33,T34 |
| 1 |
0 |
0 |
1 |
Covered |
T27,T28,T35 |
| 1 |
0 |
0 |
0 |
Not Covered |
|
| 0 |
- |
- |
- |
Covered |
T1,T2,T3 |
43 if (!rst_ni) begin
-1-
44 prv_cmd_q <= NONE;
==>
45 end else begin
46 if (any_vld_req) begin
-2-
47 prv_cmd_q <= cur_cmd;
==>
48 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T4,T16,T8 |
| 0 |
0 |
Covered |
T1,T2,T3 |
56 if (!rst_ni || !rd_buf_en) idle_cnt <= 0;
-1-
==>
57 else idle_cnt <= (any_vld_req)? 0 :
-2-
==>
58 (idle_cnt == 32'hffff_ffff)? 32'hffff_ffff : idle_cnt + 32'h1;
-3-
==>
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T4,T16,T8 |
| 0 |
0 |
1 |
Not Covered |
|
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |