Unified Coverage Report :: Module :: prim_secded_hamming_76_68_enc

Module : prim_secded_hamming_76_68_enc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_76_68_enc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_enc	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_enc	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_enc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.04	100.00	93.85		100.00	96.36	100.00	gen_prog_data.u_prog

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_enc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.35	100.00	95.38		100.00	96.36	100.00	gen_prog_data.u_prog

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_secded_hamming_76_68_enc

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00

12                        always_comb begin : p_encode
13         1/1              data_o = 76'(data_i);
           Tests:       T1 T2 T3 
14         1/1              data_o[68] = ^(data_o & 76'h00AAB55555556AAAD5B);
           Tests:       T1 T2 T3 
15         1/1              data_o[69] = ^(data_o & 76'h00CCD9999999B33366D);
           Tests:       T1 T2 T3 
16         1/1              data_o[70] = ^(data_o & 76'h000F1E1E1E1E3C3C78E);
           Tests:       T1 T2 T3 
17         1/1              data_o[71] = ^(data_o & 76'h00F01FE01FE03FC07F0);
           Tests:       T1 T2 T3 
18         1/1              data_o[72] = ^(data_o & 76'h00001FFFE0003FFF800);
           Tests:       T1 T2 T3 
19         1/1              data_o[73] = ^(data_o & 76'h00001FFFFFFFC000000);
           Tests:       T1 T2 T3 
20         1/1              data_o[74] = ^(data_o & 76'h00FFE00000000000000);
           Tests:       T1 T2 T3 
21         1/1              data_o[75] = ^(data_o & 76'h7FFFFFFFFFFFFFFFFFF);
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_enc

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00

12                        always_comb begin : p_encode
13         1/1              data_o = 76'(data_i);
           Tests:       T1 T2 T3 
14         1/1              data_o[68] = ^(data_o & 76'h00AAB55555556AAAD5B);
           Tests:       T1 T2 T3 
15         1/1              data_o[69] = ^(data_o & 76'h00CCD9999999B33366D);
           Tests:       T1 T2 T3 
16         1/1              data_o[70] = ^(data_o & 76'h000F1E1E1E1E3C3C78E);
           Tests:       T1 T2 T3 
17         1/1              data_o[71] = ^(data_o & 76'h00F01FE01FE03FC07F0);
           Tests:       T1 T2 T3 
18         1/1              data_o[72] = ^(data_o & 76'h00001FFFE0003FFF800);
           Tests:       T1 T2 T3 
19         1/1              data_o[73] = ^(data_o & 76'h00001FFFFFFFC000000);
           Tests:       T1 T2 T3 
20         1/1              data_o[74] = ^(data_o & 76'h00FFE00000000000000);
           Tests:       T1 T2 T3 
21         1/1              data_o[75] = ^(data_o & 76'h7FFFFFFFFFFFFFFFFFF);
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_enc

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
ALWAYS	13	9	9	100.00

12                        always_comb begin : p_encode
13         1/1              data_o = 76'(data_i);
           Tests:       T1 T2 T3 
14         1/1              data_o[68] = ^(data_o & 76'h00AAB55555556AAAD5B);
           Tests:       T1 T2 T3 
15         1/1              data_o[69] = ^(data_o & 76'h00CCD9999999B33366D);
           Tests:       T1 T2 T3 
16         1/1              data_o[70] = ^(data_o & 76'h000F1E1E1E1E3C3C78E);
           Tests:       T1 T2 T3 
17         1/1              data_o[71] = ^(data_o & 76'h00F01FE01FE03FC07F0);
           Tests:       T1 T2 T3 
18         1/1              data_o[72] = ^(data_o & 76'h00001FFFE0003FFF800);
           Tests:       T1 T2 T3 
19         1/1              data_o[73] = ^(data_o & 76'h00001FFFFFFFC000000);
           Tests:       T1 T2 T3 
20         1/1              data_o[74] = ^(data_o & 76'h00FFE00000000000000);
           Tests:       T1 T2 T3 
21         1/1              data_o[75] = ^(data_o & 76'h7FFFFFFFFFFFFFFFFFF);
           Tests:       T1 T2 T3