Unified Coverage Report :: Module :: flash_phy_prog

Module : flash_phy_prog

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.35	100.00	95.38		100.00	96.36	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog	98.04	100.00	93.85		100.00	96.36	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog	98.35	100.00	95.38		100.00	96.36	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.04	100.00	93.85		100.00	96.36	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.85	100.00	100.00	96.49	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	97.75	87.74		100.00	93.48	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	100.00	100.00		100.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.35	100.00	95.38		100.00	96.36	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.81	100.00	95.38	95.00	100.00	96.49	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.76	96.63	85.85		100.00	91.30	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	97.50	100.00		95.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

110                       // selects empty data or real data
111        1/1            assign pack_data  = (data_sel == Actual) ? data_i[BusWidth-1:0] : {BusWidth{1'b1}};
           Tests:       T1 T2 T3 
112                     
113                       logic data_intg_ok;
114                       logic data_err;
115                     
116                       // use the tlul integrity module directly for bus integrity
117                       // SEC_CM: MEM.BUS.INTEGRITY
118                       tlul_data_integ_dec u_data_intg_chk (
119                         .data_intg_i(data_i),
120                         .data_err_o(data_err)
121                       );
122        1/1            assign data_intg_ok = ~data_err;
           Tests:       T1 T2 T3 
123                     
124                       logic data_invalid_q, data_invalid_d;
125                       // hold on integrity failure indication until reset
126        1/1            assign data_invalid_d = data_invalid_q |
           Tests:       T1 T2 T3 
127                                               (pack_valid & ~data_intg_ok);
128                     
129                       always_ff @(posedge clk_i or negedge rst_ni) begin
130        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
131        1/1                data_invalid_q <= '0;
           Tests:       T1 T2 T3 
132                         end else begin
133        1/1                data_invalid_q <= data_invalid_d;
           Tests:       T1 T2 T3 
134                         end
135                       end
136                     
137                       // indication to upper layer presence of error
138        1/1            assign intg_err_o = data_invalid_q;
           Tests:       T1 T2 T3 
139                     
140                       // if integrity failure is seen, fake communication with flash
141                       // and simply terminate
142                       logic ack, done;
143        1/1            assign ack = ack_i | data_invalid_q;
           Tests:       T1 T2 T3 
144        1/1            assign done = done_i | data_invalid_q;
           Tests:       T1 T2 T3 
145                     
146                       // next idx will be aligned
147        1/1            assign idx_sub_one = idx - 1'b1;
           Tests:       T1 T2 T3 
148        1/1            assign align_next = (idx > '0) ? (idx_sub_one == sel_i) : 1'b0;
           Tests:       T1 T2 T3 
149                     
150                       always_ff @(posedge clk_i or negedge rst_ni) begin
151        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
152        1/1                idx <= '0;
           Tests:       T1 T2 T3 
153        1/1              end else if (pack_valid && idx == MaxIdx) begin
           Tests:       T1 T2 T3 
154                           // when a flash word is packed full, return index to 0
155        1/1                idx <= '0;
           Tests:       T1 T2 T4 
156        1/1              end else if (pack_valid) begin
           Tests:       T1 T2 T3 
157                           // increment otherwise
158        1/1                idx <= idx + 1'b1;
           Tests:       T1 T2 T4 
159                         end
                        MISSING_ELSE
160                       end
161                     
162                     
163                       // SEC_CM: PHY_PROG.FSM.SPARSE
164        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle):
164.1                   `ifdef SIMULATION                                   
164.2                       prim_sparse_fsm_flop #(                           
164.3                         .StateEnumT(state_e),                            
164.4                         .Width($bits(state_e)),                          
164.5                         .ResetValue($bits(state_e)'(StIdle)),          
164.6                         .EnableAlertTriggerSVA(1), 
164.7                         .CustomForceName("state_q")          
164.8                       ) u_state_regs (                                        
164.9                         .clk_i   ( clk_i   ),                           
164.10                        .rst_ni  ( rst_ni ),                           
164.11                        .state_i ( state_d     ),                           
164.12                        .state_o (         )                            
164.13                      );                                                
164.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
164.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
164.16     1/1                state_q <= StIdle;                                
           Tests:       T1 T2 T3 
164.17                      end else begin                                    
164.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
164.19                      end                                               
164.20                    end  
164.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
164.22                      else begin                                                                           
164.23                        `ifdef UVM                                                                               
164.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
164.25                                              "../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv", 164, "", 1);                                
164.26                  `else                                                                                    
164.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
164.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
164.29                  `endif                                                              
164.30                      end 
164.31                    `else                                               
164.32                      prim_sparse_fsm_flop #(                           
164.33                        .StateEnumT(state_e),                            
164.34                        .Width($bits(state_e)),                          
164.35                        .ResetValue($bits(state_e)'(StIdle)),          
164.36                        .EnableAlertTriggerSVA(1)  
164.37                      ) u_state_regs (                                        
164.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
164.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
164.40                        .state_i ( state_d     ),                           
164.41                        .state_o ( state_q     )                            
164.42                      );                                                
164.43                    `endif165                     
166                       // If the first beat of an incoming transaction is not aligned to word boundary (for example
167                       // if each flash word is 4 bus words wide, and the first word to program starts at index 1),
168                       // the fsm pre-packs the flash word with empty words until the supplied index.
169                       // Once at the index, real data supplied from the flash controller is packed until the last
170                       // beat of data.  At the last beat of data, if it is not also aligned (index 3 in this example),
171                       // more empty words are packed at the end to fill out the word.
172                       //
173                       always_comb begin
174        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
175                     
176        1/1              pack_valid = 1'b0;
           Tests:       T1 T2 T3 
177        1/1              data_sel = Filler;
           Tests:       T1 T2 T3 
178        1/1              plain_ecc_en = 1'b0;
           Tests:       T1 T2 T3 
179        1/1              req_o = 1'b0;
           Tests:       T1 T2 T3 
180        1/1              ack_o = 1'b0;
           Tests:       T1 T2 T3 
181        1/1              last_o = 1'b0;
           Tests:       T1 T2 T3 
182        1/1              calc_req_o = 1'b0;
           Tests:       T1 T2 T3 
183        1/1              scramble_req_o = 1'b0;
           Tests:       T1 T2 T3 
184        1/1              fsm_err_o = 1'b0;
           Tests:       T1 T2 T3 
185                     
186        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
187                           StIdle: begin
188                             // if first beat of a transaction is not aligned, prepack with empty bits
189        1/1                  if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) begin
           Tests:       T1 T2 T3 
190                               // only disable during idle state to ensure program is able to gracefully complete
191                               // this is important as we do not want to accidentally disturb any electrical procedure
192                               // internal to the flash macro
193        1/1                    state_d = StDisabled;
           Tests:       T4 T5 T6 
194        1/1                  end else if (req_i && |sel_i) begin
           Tests:       T1 T2 T3 
195        1/1                    state_d = StPrePack;
           Tests:       T78 T24 T35 
196        1/1                  end else if (req_i) begin
           Tests:       T1 T2 T3 
197        1/1                    state_d = StPackData;
           Tests:       T1 T2 T4 
198                             end
                        MISSING_ELSE
199                           end
200                     
201                           StPrePack: begin
202                             // pack until currently supplied data
203        1/1                  pack_valid = (idx < sel_i);
           Tests:       T78 T24 T35 
204        1/1                  if (idx == align_next) begin
           Tests:       T78 T24 T35 
205        1/1                    state_d = StPackData;
           Tests:       T78 T24 T35 
206                             end
                   ==>  MISSING_ELSE
207                           end
208                     
209                           StPackData: begin
210        1/1                  pack_valid = req_i;
           Tests:       T1 T2 T4 
211        1/1                  data_sel = Actual;
           Tests:       T1 T2 T4 
212                     
213        1/1                  if (req_i && idx == MaxIdx) begin
           Tests:       T1 T2 T4 
214                               // last beat of a flash word
215        1/1                    state_d = StCalcPlainEcc;
           Tests:       T1 T2 T4 
216        1/1                  end else if (req_i && last_i) begin
           Tests:       T1 T2 T4 
217                               // last beat is not aligned with the last entry of flash word
218        1/1                    state_d = StPostPack;
           Tests:       T78 T24 T172 
219        1/1                  end else if (req_i) begin
           Tests:       T1 T2 T4 
220        1/1                    ack_o = 1'b1;
           Tests:       T1 T2 T4 
221                             end
                        MISSING_ELSE
222                           end
223                     
224                           StPostPack: begin
225                             // supply filler data
226        1/1                  pack_valid = 1'b1;
           Tests:       T78 T24 T172 
227        1/1                  data_sel = Filler;
           Tests:       T78 T24 T172 
228                     
229                             // finish packing remaining entries
230        1/1                  if (idx == MaxIdx) begin
           Tests:       T78 T24 T172 
231        1/1                    state_d = StCalcPlainEcc;
           Tests:       T78 T24 T172 
232                             end
                   ==>  MISSING_ELSE
233                           end
234                     
235                           StCalcPlainEcc: begin
236        1/1                  plain_ecc_en = 1'b1;
           Tests:       T1 T2 T4 
237        1/1                  state_d = scramble_i ? StCalcMask : StReqFlash;
           Tests:       T1 T2 T4 
238                           end
239                     
240                           StCalcMask: begin
241        1/1                  calc_req_o = 1'b1;
           Tests:       T1 T4 T5 
242                     
243        1/1                  if (calc_ack_i) begin
           Tests:       T1 T4 T5 
244        1/1                    state_d = StScrambleData;
           Tests:       T1 T4 T5 
245                             end
                        MISSING_ELSE
246                           end
247                     
248                           StScrambleData: begin
249        1/1                  scramble_req_o = 1'b1;
           Tests:       T1 T4 T5 
250                     
251        1/1                  if (scramble_ack_i) begin
           Tests:       T1 T4 T5 
252        1/1                    state_d = StCalcEcc;
           Tests:       T1 T4 T5 
253                             end
                        MISSING_ELSE
254                           end
255                     
256                           StCalcEcc: begin
257        1/1                  state_d = StReqFlash;
           Tests:       T1 T4 T5 
258                           end
259                     
260                           StReqFlash: begin
261                             // only request flash if data integrity was valid
262        1/1                  req_o = ~data_invalid_q;
           Tests:       T2 T4 T5 
263        1/1                  last_o = last_i;
           Tests:       T2 T4 T5 
264                     
265                             // if this is the last beat of the program burst
266                             //   - wait for done
267                             // if this is NOT the last beat
268                             //   - ack the upstream request and accept more beats
269        1/1                  if (last_i) begin
           Tests:       T2 T4 T5 
270        1/1                    state_d = ack ? StWaitFlash : StReqFlash;
           Tests:       T2 T5 T9 
271                             end else begin
272        1/1                    ack_o = ack;
           Tests:       T2 T4 T5 
273        1/1                    state_d = ack ? StIdle : StReqFlash;
           Tests:       T2 T4 T5 
274                             end
275                           end
276                     
277                           StWaitFlash: begin
278        1/1                  if (done) begin
           Tests:       T2 T5 T9 
279        1/1                    ack_o = 1'b1;
           Tests:       T2 T5 T9 
280        1/1                    state_d = StIdle;
           Tests:       T2 T5 T9 
281                             end
                        MISSING_ELSE
282                           end
283                     
284                           StDisabled: begin
285        1/1                  state_d = StDisabled;
           Tests:       T4 T5 T6 
286                           end
287                     
288                           default: begin
289                             fsm_err_o = 1'b1;
290                           end
291                     
292                         endcase // unique case (state_q)
293                     
294                       end
295                     
296                       logic [DataWidth-1:0] mask_q;
297                     
298                       always_ff @(posedge clk_i or negedge rst_ni) begin
299        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
300        1/1                packed_data <= '0;
           Tests:       T1 T2 T3 
301        1/1                mask_q <= '0;
           Tests:       T1 T2 T3 
302        1/1              end else if (req_o && ack) begin
           Tests:       T1 T2 T3 
303        1/1                packed_data <= '0;
           Tests:       T2 T4 T5 
304        1/1              end else if (calc_req_o && calc_ack_i) begin
           Tests:       T1 T2 T3 
305        1/1                packed_data <= packed_data ^ mask_i;
           Tests:       T1 T4 T5 
306        1/1                mask_q <= mask_i;
           Tests:       T1 T4 T5 
307        1/1              end else if (scramble_req_o && scramble_ack_i) begin
           Tests:       T1 T2 T3 
308        1/1                packed_data <= scrambled_data_i[DataWidth-1:0] ^ mask_q;
           Tests:       T1 T4 T5 
309        1/1              end else if (pack_valid) begin
           Tests:       T1 T2 T3 
310        1/1                packed_data[idx] <= pack_data;
           Tests:       T1 T2 T4 
311                         end
                        MISSING_ELSE
312                       end
313                     
314        1/1            assign block_data_o = packed_data;
           Tests:       T1 T2 T3 
315                     
316                       // ECC handling
317                       localparam int PlainDataEccWidth = DataWidth + 8;
318                     
319                       logic [FullDataWidth-1:0] ecc_data;
320                       logic [PlainDataEccWidth-1:0] plain_data_w_ecc;
321                       logic [PlainIntgWidth-1:0] plain_data_ecc;
322                       always_ff @(posedge clk_i or negedge rst_ni) begin
323        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
324        1/1                plain_data_ecc <= '1;
           Tests:       T1 T2 T3 
325        1/1              end else if (plain_ecc_en) begin
           Tests:       T1 T2 T3 
326        1/1                plain_data_ecc <= plain_data_w_ecc[DataWidth +: PlainIntgWidth];
           Tests:       T1 T2 T4 
327                         end
                        MISSING_ELSE
328                       end
329                     
330                       logic [PlainDataWidth-1:0] ecc_data_in;
331        1/1            assign ecc_data_in = {plain_data_ecc, packed_data};
           Tests:       T1 T2 T3 
332                     
333                       // reliability ECC calculation
334                       prim_secded_hamming_76_68_enc u_enc (
335                         .data_i(ecc_data_in),
336                         .data_o(ecc_data)
337                       );
338                     
339                       // integrity ECC calculation
340                       // This instance can technically be merged with the instance above, but is
341                       // kept separate for the sake of convenience
342                       // The plain data ecc is calculated continuously from packed data (which changes
343                       // from packed data to masked/scrambled data based on software configuration).
344                       // The actual plain data ECC is explicitly captured during this process when
345                       // it is required.
346                       prim_secded_hamming_72_64_enc u_plain_enc (
347                         .data_i(packed_data),
348                         .data_o(plain_data_w_ecc)
349                       );
350                     
351                       logic unused_data;
352        1/1            assign unused_data = |plain_data_w_ecc;
           Tests:       T1 T2 T3 
353                     
354                       // pad the remaining bits with '1' if ecc is not used.
355        1/1            assign data_o = ecc_i ? ecc_data : {{EccWidth{1'b1}}, ecc_data_in};
           Tests:       T1 T2 T3 
356                     
357                       /////////////////////////////////
358                       // Assertions
359                       /////////////////////////////////
360                     
361                     `ifdef INC_ASSERT
362                       logic txn_done;
363                       logic [15:0] done_cnt_d, done_cnt_q;
364                     
365        1/1            assign txn_done = req_i && ack_o && last_i;
           Tests:       T1 T2 T3 
366        1/1            assign done_cnt_d = txn_done ? '0 : (done ? done_cnt_q + 16'h1 : done_cnt_q);
           Tests:       T1 T2 T3 
367                     
368                       always_ff @(posedge clk_i or negedge rst_ni) begin
369        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
370        1/1                done_cnt_q <= '0;
           Tests:       T1 T2 T3 
371                         end else begin
372        1/1                done_cnt_q <= done_cnt_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : flash_phy_prog

	Total	Covered	Percent
Conditions	65	62	95.38
Logical	65	62	95.38
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T142,T7
1	0	Covered	T4,T142,T7

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T4,T142,T7

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T18
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T142,T7
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T78,T24,T172

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T78,T24,T35

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T78,T24,T35

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T78,T24,T172

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Not Covered
1	Covered	T78,T24,T172

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T2,T4,T9
1	Covered	T1,T4,T5

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T2,T5,T9
1	Covered	T2,T5,T9

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T4,T5

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T2,T5,T9

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T9

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : flash_phy_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T1,T4,T5
StCalcMask	237	Covered	T1,T4,T5
StCalcPlainEcc	215	Covered	T1,T2,T4
StDisabled	193	Covered	T4,T5,T6
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T2,T4
StPostPack	218	Covered	T78,T24,T172
StPrePack	195	Covered	T78,T24,T35
StReqFlash	237	Covered	T2,T4,T5
StScrambleData	244	Covered	T1,T4,T5
StWaitFlash	270	Covered	T2,T5,T9

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T4,T5,T11
StCalcMask->StScrambleData	244	Covered	T1,T4,T5
StCalcPlainEcc->StCalcMask	237	Covered	T1,T4,T5
StCalcPlainEcc->StReqFlash	237	Covered	T2,T4,T9
StIdle->StDisabled	193	Covered	T4,T5,T6
StIdle->StPackData	197	Covered	T1,T2,T4
StIdle->StPrePack	195	Covered	T78,T24,T35
StPackData->StCalcPlainEcc	215	Covered	T1,T2,T4
StPackData->StPostPack	218	Covered	T78,T24,T172
StPostPack->StCalcPlainEcc	231	Covered	T78,T24,T172
StPrePack->StPackData	205	Covered	T78,T24,T35
StReqFlash->StIdle	273	Covered	T2,T4,T5
StReqFlash->StWaitFlash	270	Covered	T2,T5,T9
StScrambleData->StCalcEcc	252	Covered	T1,T4,T5
StWaitFlash->StIdle	280	Covered	T2,T5,T9

---

Branch Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
Branches		55	53	96.36
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	25	92.59
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

111          assign pack_data  = (data_sel == Actual) ? data_i[BusWidth-1:0] : {BusWidth{1'b1}};
                                                      -1-  
                                                      ==>  
                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

148          assign align_next = (idx > '0) ? (idx_sub_one == sel_i) : 1'b0;
                                            -1-  
                                            ==>  
                                            ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

355          assign data_o = ecc_i ? ecc_data : {{EccWidth{1'b1}}, ecc_data_in};
                                   -1-  
                                   ==>  
                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

366          assign done_cnt_d = txn_done ? '0 : (done ? done_cnt_q + 16'h1 : done_cnt_q);
                                          -1-          -2-   
                                          ==>          ==>   
                                                       ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T9
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

130            if (!rst_ni) begin
               -1-  
131              data_invalid_q <= '0;
                 ==>
132            end else begin
133              data_invalid_q <= data_invalid_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

151            if (!rst_ni) begin
               -1-  
152              idx <= '0;
                 ==>
153            end else if (pack_valid && idx == MaxIdx) begin
                        -2-  
154              // when a flash word is packed full, return index to 0
155              idx <= '0;
                 ==>
156            end else if (pack_valid) begin
                        -3-  
157              // increment otherwise
158              idx <= idx + 1'b1;
                 ==>
159            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

164          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle)
             -1-                                                                      
             ==>                                                                      
             ==>                                                                      

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

186            unique case (state_q)
                      -1-  
187              StIdle: begin
188                // if first beat of a transaction is not aligned, prepack with empty bits
189                if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) begin
                   -2-  
190                  // only disable during idle state to ensure program is able to gracefully complete
191                  // this is important as we do not want to accidentally disturb any electrical procedure
192                  // internal to the flash macro
193                  state_d = StDisabled;
                     ==>
194                end else if (req_i && |sel_i) begin
                            -3-  
195                  state_d = StPrePack;
                     ==>
196                end else if (req_i) begin
                            -4-  
197                  state_d = StPackData;
                     ==>
198                end
                   MISSING_ELSE
                   ==>
199              end
200        
201              StPrePack: begin
202                // pack until currently supplied data
203                pack_valid = (idx < sel_i);
204                if (idx == align_next) begin
                   -5-  
205                  state_d = StPackData;
                     ==>
206                end
                   MISSING_ELSE
                   ==>
207              end
208        
209              StPackData: begin
210                pack_valid = req_i;
211                data_sel = Actual;
212        
213                if (req_i && idx == MaxIdx) begin
                   -6-  
214                  // last beat of a flash word
215                  state_d = StCalcPlainEcc;
                     ==>
216                end else if (req_i && last_i) begin
                            -7-  
217                  // last beat is not aligned with the last entry of flash word
218                  state_d = StPostPack;
                     ==>
219                end else if (req_i) begin
                            -8-  
220                  ack_o = 1'b1;
                     ==>
221                end
                   MISSING_ELSE
                   ==>
222              end
223        
224              StPostPack: begin
225                // supply filler data
226                pack_valid = 1'b1;
227                data_sel = Filler;
228        
229                // finish packing remaining entries
230                if (idx == MaxIdx) begin
                   -9-  
231                  state_d = StCalcPlainEcc;
                     ==>
232                end
                   MISSING_ELSE
                   ==>
233              end
234        
235              StCalcPlainEcc: begin
236                plain_ecc_en = 1'b1;
237                state_d = scramble_i ? StCalcMask : StReqFlash;
                                        -10-  
                                        ==>  
                                        ==>  
238              end
239        
240              StCalcMask: begin
241                calc_req_o = 1'b1;
242        
243                if (calc_ack_i) begin
                   -11-  
244                  state_d = StScrambleData;
                     ==>
245                end
                   MISSING_ELSE
                   ==>
246              end
247        
248              StScrambleData: begin
249                scramble_req_o = 1'b1;
250        
251                if (scramble_ack_i) begin
                   -12-  
252                  state_d = StCalcEcc;
                     ==>
253                end
                   MISSING_ELSE
                   ==>
254              end
255        
256              StCalcEcc: begin
257                state_d = StReqFlash;
                   ==>
258              end
259        
260              StReqFlash: begin
261                // only request flash if data integrity was valid
262                req_o = ~data_invalid_q;
263                last_o = last_i;
264        
265                // if this is the last beat of the program burst
266                //   - wait for done
267                // if this is NOT the last beat
268                //   - ack the upstream request and accept more beats
269                if (last_i) begin
                   -13-  
270                  state_d = ack ? StWaitFlash : StReqFlash;
                                   -14-  
                                   ==>  
                                   ==>  
271                end else begin
272                  ack_o = ack;
273                  state_d = ack ? StIdle : StReqFlash;
                                   -15-  
                                   ==>  
                                   ==>  
274                end
275              end
276        
277              StWaitFlash: begin
278                if (done) begin
                   -16-  
279                  ack_o = 1'b1;
                     ==>
280                  state_d = StIdle;
281                end
                   MISSING_ELSE
                   ==>
282              end
283        
284              StDisabled: begin
285                state_d = StDisabled;
                   ==>
286              end
287        
288              default: begin
289                fsm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T78,T24,T35
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T78,T24,T35
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T78,T24,T172
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T78,T24,T172
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T4,T5
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T4,T9
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T4,T5
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T4,T5
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T4,T5
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T4,T5
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T2,T5,T9
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T2,T5,T9
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T2,T4,T5
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T2,T4,T5
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T5,T9
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T5,T9
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

299            if (!rst_ni) begin
               -1-  
300              packed_data <= '0;
                 ==>
301              mask_q <= '0;
302            end else if (req_o && ack) begin
                        -2-  
303              packed_data <= '0;
                 ==>
304            end else if (calc_req_o && calc_ack_i) begin
                        -3-  
305              packed_data <= packed_data ^ mask_i;
                 ==>
306              mask_q <= mask_i;
307            end else if (scramble_req_o && scramble_ack_i) begin
                        -4-  
308              packed_data <= scrambled_data_i[DataWidth-1:0] ^ mask_q;
                 ==>
309            end else if (pack_valid) begin
                        -5-  
310              packed_data[idx] <= pack_data;
                 ==>
311            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T2,T4,T5
0	0	1	-	-	Covered	T1,T4,T5
0	0	0	1	-	Covered	T1,T4,T5
0	0	0	0	1	Covered	T1,T2,T4
0	0	0	0	0	Covered	T1,T2,T3

323            if (!rst_ni) begin
               -1-  
324              plain_data_ecc <= '1;
                 ==>
325            end else if (plain_ecc_en) begin
                        -2-  
326              plain_data_ecc <= plain_data_w_ecc[DataWidth +: PlainIntgWidth];
                 ==>
327            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

369            if (!rst_ni) begin
               -1-  
370              done_cnt_q <= '0;
                 ==>
371            end else begin
372              done_cnt_q <= done_cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	665750786	2244075	0	0
PostPackRule_A	665750786	1229	0	0
PrePackRule_A	665750786	921	0	0
WidthCheck_A	2052	2052	0	0
u_state_regs_A	665750786	664017318	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665750786	2244075	0	0
T2	3694	14	0	0
T3	2283	0	0	0
T4	4375	0	0	0
T5	1250	1	0	0
T6	873	0	0	0
T8	51282	0	0	0
T9	0	1	0	0
T15	949	0	0	0
T16	1834	0	0	0
T17	1845	0	0	0
T19	84564	15	0	0
T20	1105	0	0	0
T24	0	3	0	0
T27	7017	0	0	0
T28	0	100	0	0
T33	1654	1	0	0
T34	2997	3	0	0
T35	0	32	0	0
T36	30072	143	0	0
T37	207944	1321	0	0
T51	0	213	0	0
T58	0	1	0	0
T64	6270	0	0	0
T66	1241	0	0	0
T78	2116	1	0	0
T84	0	205	0	0
T120	5764	0	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665750786	1229	0	0
T23	1309	0	0	0
T24	6340	3	0	0
T28	419268	0	0	0
T29	0	3	0	0
T30	0	2	0	0
T31	0	2	0	0
T35	0	30	0	0
T42	233638	0	0	0
T51	128822	0	0	0
T56	22894	0	0	0
T58	4560	0	0	0
T65	2786	0	0	0
T67	0	33	0	0
T68	0	35	0	0
T78	2116	1	0	0
T107	13918	0	0	0
T142	221130	0	0	0
T172	1231	1	0	0
T178	0	2	0	0
T236	0	5	0	0
T243	0	3	0	0
T244	0	2	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665750786	921	0	0
T23	1309	0	0	0
T24	6340	2	0	0
T28	419268	0	0	0
T29	0	3	0	0
T30	0	3	0	0
T31	0	1	0	0
T35	0	28	0	0
T42	233638	0	0	0
T51	128822	0	0	0
T56	22894	0	0	0
T58	4560	0	0	0
T65	2786	0	0	0
T67	0	29	0	0
T68	0	26	0	0
T78	2116	1	0	0
T95	0	10	0	0
T107	13918	0	0	0
T142	221130	0	0	0
T172	1231	0	0	0
T178	0	3	0	0
T236	0	4	0	0
T243	0	3	0	0
T244	0	2	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2052	2052	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T8	2	2	0	0
T15	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	665750786	664017318	0	0
T1	2950	2722	0	0
T2	7388	7200	0	0
T3	4566	4388	0	0
T4	8750	7704	0	0
T5	2500	2302	0	0
T6	1746	1552	0	0
T8	102564	102464	0	0
T15	1898	1772	0	0
T16	3668	3490	0	0
T17	3690	3492	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

110                       // selects empty data or real data
111        1/1            assign pack_data  = (data_sel == Actual) ? data_i[BusWidth-1:0] : {BusWidth{1'b1}};
           Tests:       T1 T2 T3 
112                     
113                       logic data_intg_ok;
114                       logic data_err;
115                     
116                       // use the tlul integrity module directly for bus integrity
117                       // SEC_CM: MEM.BUS.INTEGRITY
118                       tlul_data_integ_dec u_data_intg_chk (
119                         .data_intg_i(data_i),
120                         .data_err_o(data_err)
121                       );
122        1/1            assign data_intg_ok = ~data_err;
           Tests:       T1 T2 T3 
123                     
124                       logic data_invalid_q, data_invalid_d;
125                       // hold on integrity failure indication until reset
126        1/1            assign data_invalid_d = data_invalid_q |
           Tests:       T1 T2 T3 
127                                               (pack_valid & ~data_intg_ok);
128                     
129                       always_ff @(posedge clk_i or negedge rst_ni) begin
130        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
131        1/1                data_invalid_q <= '0;
           Tests:       T1 T2 T3 
132                         end else begin
133        1/1                data_invalid_q <= data_invalid_d;
           Tests:       T1 T2 T3 
134                         end
135                       end
136                     
137                       // indication to upper layer presence of error
138        1/1            assign intg_err_o = data_invalid_q;
           Tests:       T1 T2 T3 
139                     
140                       // if integrity failure is seen, fake communication with flash
141                       // and simply terminate
142                       logic ack, done;
143        1/1            assign ack = ack_i | data_invalid_q;
           Tests:       T1 T2 T3 
144        1/1            assign done = done_i | data_invalid_q;
           Tests:       T1 T2 T3 
145                     
146                       // next idx will be aligned
147        1/1            assign idx_sub_one = idx - 1'b1;
           Tests:       T1 T2 T3 
148        1/1            assign align_next = (idx > '0) ? (idx_sub_one == sel_i) : 1'b0;
           Tests:       T1 T2 T3 
149                     
150                       always_ff @(posedge clk_i or negedge rst_ni) begin
151        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
152        1/1                idx <= '0;
           Tests:       T1 T2 T3 
153        1/1              end else if (pack_valid && idx == MaxIdx) begin
           Tests:       T1 T2 T3 
154                           // when a flash word is packed full, return index to 0
155        1/1                idx <= '0;
           Tests:       T1 T2 T4 
156        1/1              end else if (pack_valid) begin
           Tests:       T1 T2 T3 
157                           // increment otherwise
158        1/1                idx <= idx + 1'b1;
           Tests:       T1 T2 T4 
159                         end
                        MISSING_ELSE
160                       end
161                     
162                     
163                       // SEC_CM: PHY_PROG.FSM.SPARSE
164        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle):
164.1                   `ifdef SIMULATION                                   
164.2                       prim_sparse_fsm_flop #(                           
164.3                         .StateEnumT(state_e),                            
164.4                         .Width($bits(state_e)),                          
164.5                         .ResetValue($bits(state_e)'(StIdle)),          
164.6                         .EnableAlertTriggerSVA(1), 
164.7                         .CustomForceName("state_q")          
164.8                       ) u_state_regs (                                        
164.9                         .clk_i   ( clk_i   ),                           
164.10                        .rst_ni  ( rst_ni ),                           
164.11                        .state_i ( state_d     ),                           
164.12                        .state_o (         )                            
164.13                      );                                                
164.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
164.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
164.16     1/1                state_q <= StIdle;                                
           Tests:       T1 T2 T3 
164.17                      end else begin                                    
164.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
164.19                      end                                               
164.20                    end  
164.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
164.22                      else begin                                                                           
164.23                        `ifdef UVM                                                                               
164.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
164.25                                              "../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv", 164, "", 1);                                
164.26                  `else                                                                                    
164.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
164.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
164.29                  `endif                                                              
164.30                      end 
164.31                    `else                                               
164.32                      prim_sparse_fsm_flop #(                           
164.33                        .StateEnumT(state_e),                            
164.34                        .Width($bits(state_e)),                          
164.35                        .ResetValue($bits(state_e)'(StIdle)),          
164.36                        .EnableAlertTriggerSVA(1)  
164.37                      ) u_state_regs (                                        
164.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
164.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
164.40                        .state_i ( state_d     ),                           
164.41                        .state_o ( state_q     )                            
164.42                      );                                                
164.43                    `endif165                     
166                       // If the first beat of an incoming transaction is not aligned to word boundary (for example
167                       // if each flash word is 4 bus words wide, and the first word to program starts at index 1),
168                       // the fsm pre-packs the flash word with empty words until the supplied index.
169                       // Once at the index, real data supplied from the flash controller is packed until the last
170                       // beat of data.  At the last beat of data, if it is not also aligned (index 3 in this example),
171                       // more empty words are packed at the end to fill out the word.
172                       //
173                       always_comb begin
174        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
175                     
176        1/1              pack_valid = 1'b0;
           Tests:       T1 T2 T3 
177        1/1              data_sel = Filler;
           Tests:       T1 T2 T3 
178        1/1              plain_ecc_en = 1'b0;
           Tests:       T1 T2 T3 
179        1/1              req_o = 1'b0;
           Tests:       T1 T2 T3 
180        1/1              ack_o = 1'b0;
           Tests:       T1 T2 T3 
181        1/1              last_o = 1'b0;
           Tests:       T1 T2 T3 
182        1/1              calc_req_o = 1'b0;
           Tests:       T1 T2 T3 
183        1/1              scramble_req_o = 1'b0;
           Tests:       T1 T2 T3 
184        1/1              fsm_err_o = 1'b0;
           Tests:       T1 T2 T3 
185                     
186        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
187                           StIdle: begin
188                             // if first beat of a transaction is not aligned, prepack with empty bits
189        1/1                  if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) begin
           Tests:       T1 T2 T3 
190                               // only disable during idle state to ensure program is able to gracefully complete
191                               // this is important as we do not want to accidentally disturb any electrical procedure
192                               // internal to the flash macro
193        1/1                    state_d = StDisabled;
           Tests:       T4 T5 T6 
194        1/1                  end else if (req_i && |sel_i) begin
           Tests:       T1 T2 T3 
195        1/1                    state_d = StPrePack;
           Tests:       T24 T35 T67 
196        1/1                  end else if (req_i) begin
           Tests:       T1 T2 T3 
197        1/1                    state_d = StPackData;
           Tests:       T1 T2 T4 
198                             end
                        MISSING_ELSE
199                           end
200                     
201                           StPrePack: begin
202                             // pack until currently supplied data
203        1/1                  pack_valid = (idx < sel_i);
           Tests:       T24 T35 T67 
204        1/1                  if (idx == align_next) begin
           Tests:       T24 T35 T67 
205        1/1                    state_d = StPackData;
           Tests:       T24 T35 T67 
206                             end
                   ==>  MISSING_ELSE
207                           end
208                     
209                           StPackData: begin
210        1/1                  pack_valid = req_i;
           Tests:       T1 T2 T4 
211        1/1                  data_sel = Actual;
           Tests:       T1 T2 T4 
212                     
213        1/1                  if (req_i && idx == MaxIdx) begin
           Tests:       T1 T2 T4 
214                               // last beat of a flash word
215        1/1                    state_d = StCalcPlainEcc;
           Tests:       T1 T2 T4 
216        1/1                  end else if (req_i && last_i) begin
           Tests:       T1 T2 T4 
217                               // last beat is not aligned with the last entry of flash word
218        1/1                    state_d = StPostPack;
           Tests:       T24 T172 T35 
219        1/1                  end else if (req_i) begin
           Tests:       T1 T2 T4 
220        1/1                    ack_o = 1'b1;
           Tests:       T1 T2 T4 
221                             end
                        MISSING_ELSE
222                           end
223                     
224                           StPostPack: begin
225                             // supply filler data
226        1/1                  pack_valid = 1'b1;
           Tests:       T24 T172 T35 
227        1/1                  data_sel = Filler;
           Tests:       T24 T172 T35 
228                     
229                             // finish packing remaining entries
230        1/1                  if (idx == MaxIdx) begin
           Tests:       T24 T172 T35 
231        1/1                    state_d = StCalcPlainEcc;
           Tests:       T24 T172 T35 
232                             end
                   ==>  MISSING_ELSE
233                           end
234                     
235                           StCalcPlainEcc: begin
236        1/1                  plain_ecc_en = 1'b1;
           Tests:       T1 T2 T4 
237        1/1                  state_d = scramble_i ? StCalcMask : StReqFlash;
           Tests:       T1 T2 T4 
238                           end
239                     
240                           StCalcMask: begin
241        1/1                  calc_req_o = 1'b1;
           Tests:       T1 T4 T5 
242                     
243        1/1                  if (calc_ack_i) begin
           Tests:       T1 T4 T5 
244        1/1                    state_d = StScrambleData;
           Tests:       T1 T4 T5 
245                             end
                        MISSING_ELSE
246                           end
247                     
248                           StScrambleData: begin
249        1/1                  scramble_req_o = 1'b1;
           Tests:       T1 T4 T5 
250                     
251        1/1                  if (scramble_ack_i) begin
           Tests:       T1 T4 T5 
252        1/1                    state_d = StCalcEcc;
           Tests:       T1 T4 T5 
253                             end
                        MISSING_ELSE
254                           end
255                     
256                           StCalcEcc: begin
257        1/1                  state_d = StReqFlash;
           Tests:       T1 T4 T5 
258                           end
259                     
260                           StReqFlash: begin
261                             // only request flash if data integrity was valid
262        1/1                  req_o = ~data_invalid_q;
           Tests:       T2 T4 T5 
263        1/1                  last_o = last_i;
           Tests:       T2 T4 T5 
264                     
265                             // if this is the last beat of the program burst
266                             //   - wait for done
267                             // if this is NOT the last beat
268                             //   - ack the upstream request and accept more beats
269        1/1                  if (last_i) begin
           Tests:       T2 T4 T5 
270        1/1                    state_d = ack ? StWaitFlash : StReqFlash;
           Tests:       T2 T5 T9 
271                             end else begin
272        1/1                    ack_o = ack;
           Tests:       T2 T4 T5 
273        1/1                    state_d = ack ? StIdle : StReqFlash;
           Tests:       T2 T4 T5 
274                             end
275                           end
276                     
277                           StWaitFlash: begin
278        1/1                  if (done) begin
           Tests:       T2 T5 T9 
279        1/1                    ack_o = 1'b1;
           Tests:       T2 T5 T9 
280        1/1                    state_d = StIdle;
           Tests:       T2 T5 T9 
281                             end
                        MISSING_ELSE
282                           end
283                     
284                           StDisabled: begin
285        1/1                  state_d = StDisabled;
           Tests:       T4 T5 T6 
286                           end
287                     
288                           default: begin
289                             fsm_err_o = 1'b1;
290                           end
291                     
292                         endcase // unique case (state_q)
293                     
294                       end
295                     
296                       logic [DataWidth-1:0] mask_q;
297                     
298                       always_ff @(posedge clk_i or negedge rst_ni) begin
299        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
300        1/1                packed_data <= '0;
           Tests:       T1 T2 T3 
301        1/1                mask_q <= '0;
           Tests:       T1 T2 T3 
302        1/1              end else if (req_o && ack) begin
           Tests:       T1 T2 T3 
303        1/1                packed_data <= '0;
           Tests:       T2 T4 T5 
304        1/1              end else if (calc_req_o && calc_ack_i) begin
           Tests:       T1 T2 T3 
305        1/1                packed_data <= packed_data ^ mask_i;
           Tests:       T1 T4 T5 
306        1/1                mask_q <= mask_i;
           Tests:       T1 T4 T5 
307        1/1              end else if (scramble_req_o && scramble_ack_i) begin
           Tests:       T1 T2 T3 
308        1/1                packed_data <= scrambled_data_i[DataWidth-1:0] ^ mask_q;
           Tests:       T1 T4 T5 
309        1/1              end else if (pack_valid) begin
           Tests:       T1 T2 T3 
310        1/1                packed_data[idx] <= pack_data;
           Tests:       T1 T2 T4 
311                         end
                        MISSING_ELSE
312                       end
313                     
314        1/1            assign block_data_o = packed_data;
           Tests:       T1 T2 T3 
315                     
316                       // ECC handling
317                       localparam int PlainDataEccWidth = DataWidth + 8;
318                     
319                       logic [FullDataWidth-1:0] ecc_data;
320                       logic [PlainDataEccWidth-1:0] plain_data_w_ecc;
321                       logic [PlainIntgWidth-1:0] plain_data_ecc;
322                       always_ff @(posedge clk_i or negedge rst_ni) begin
323        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
324        1/1                plain_data_ecc <= '1;
           Tests:       T1 T2 T3 
325        1/1              end else if (plain_ecc_en) begin
           Tests:       T1 T2 T3 
326        1/1                plain_data_ecc <= plain_data_w_ecc[DataWidth +: PlainIntgWidth];
           Tests:       T1 T2 T4 
327                         end
                        MISSING_ELSE
328                       end
329                     
330                       logic [PlainDataWidth-1:0] ecc_data_in;
331        1/1            assign ecc_data_in = {plain_data_ecc, packed_data};
           Tests:       T1 T2 T3 
332                     
333                       // reliability ECC calculation
334                       prim_secded_hamming_76_68_enc u_enc (
335                         .data_i(ecc_data_in),
336                         .data_o(ecc_data)
337                       );
338                     
339                       // integrity ECC calculation
340                       // This instance can technically be merged with the instance above, but is
341                       // kept separate for the sake of convenience
342                       // The plain data ecc is calculated continuously from packed data (which changes
343                       // from packed data to masked/scrambled data based on software configuration).
344                       // The actual plain data ECC is explicitly captured during this process when
345                       // it is required.
346                       prim_secded_hamming_72_64_enc u_plain_enc (
347                         .data_i(packed_data),
348                         .data_o(plain_data_w_ecc)
349                       );
350                     
351                       logic unused_data;
352        1/1            assign unused_data = |plain_data_w_ecc;
           Tests:       T1 T2 T3 
353                     
354                       // pad the remaining bits with '1' if ecc is not used.
355        1/1            assign data_o = ecc_i ? ecc_data : {{EccWidth{1'b1}}, ecc_data_in};
           Tests:       T1 T2 T3 
356                     
357                       /////////////////////////////////
358                       // Assertions
359                       /////////////////////////////////
360                     
361                     `ifdef INC_ASSERT
362                       logic txn_done;
363                       logic [15:0] done_cnt_d, done_cnt_q;
364                     
365        1/1            assign txn_done = req_i && ack_o && last_i;
           Tests:       T1 T2 T3 
366        1/1            assign done_cnt_d = txn_done ? '0 : (done ? done_cnt_q + 16'h1 : done_cnt_q);
           Tests:       T1 T2 T3 
367                     
368                       always_ff @(posedge clk_i or negedge rst_ni) begin
369        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
370        1/1                done_cnt_q <= '0;
           Tests:       T1 T2 T3 
371                         end else begin
372        1/1                done_cnt_q <= done_cnt_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	61	93.85
Logical	65	61	93.85
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T142,T7
1	0	Covered	T4,T142,T7

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T4,T142,T7

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T142,T7
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T24,T172,T35

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T24,T35,T67

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T24,T35,T67

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T9
1	0	Covered	T1,T2,T4
1	1	Covered	T24,T172,T35

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Not Covered
1	Covered	T24,T172,T35

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T2,T9,T34
1	Covered	T1,T4,T5

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T2,T5,T9
1	Covered	T2,T5,T9

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T2,T5,T9
1	Covered	T2,T4,T5

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T9
1	1	Covered	T2,T4,T5

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T5,T9
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T2,T5,T9

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T9

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T1,T4,T5
StCalcMask	237	Covered	T1,T4,T5
StCalcPlainEcc	215	Covered	T1,T2,T4
StDisabled	193	Covered	T4,T5,T6
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T2,T4
StPostPack	218	Covered	T24,T172,T35
StPrePack	195	Covered	T24,T35,T67
StReqFlash	237	Covered	T2,T4,T5
StScrambleData	244	Covered	T1,T4,T5
StWaitFlash	270	Covered	T2,T5,T9

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T4,T5,T11
StCalcMask->StScrambleData	244	Covered	T1,T4,T5
StCalcPlainEcc->StCalcMask	237	Covered	T1,T4,T5
StCalcPlainEcc->StReqFlash	237	Covered	T2,T9,T34
StIdle->StDisabled	193	Covered	T4,T5,T6
StIdle->StPackData	197	Covered	T1,T2,T4
StIdle->StPrePack	195	Covered	T24,T35,T67
StPackData->StCalcPlainEcc	215	Covered	T1,T2,T4
StPackData->StPostPack	218	Covered	T24,T172,T35
StPostPack->StCalcPlainEcc	231	Covered	T24,T172,T35
StPrePack->StPackData	205	Covered	T24,T35,T67
StReqFlash->StIdle	273	Covered	T2,T4,T5
StReqFlash->StWaitFlash	270	Covered	T2,T5,T9
StScrambleData->StCalcEcc	252	Covered	T1,T4,T5
StWaitFlash->StIdle	280	Covered	T2,T5,T9

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	53	96.36
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	25	92.59
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

111          assign pack_data  = (data_sel == Actual) ? data_i[BusWidth-1:0] : {BusWidth{1'b1}};
                                                      -1-  
                                                      ==>  
                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

148          assign align_next = (idx > '0) ? (idx_sub_one == sel_i) : 1'b0;
                                            -1-  
                                            ==>  
                                            ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

355          assign data_o = ecc_i ? ecc_data : {{EccWidth{1'b1}}, ecc_data_in};
                                   -1-  
                                   ==>  
                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

366          assign done_cnt_d = txn_done ? '0 : (done ? done_cnt_q + 16'h1 : done_cnt_q);
                                          -1-          -2-   
                                          ==>          ==>   
                                                       ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T9
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

130            if (!rst_ni) begin
               -1-  
131              data_invalid_q <= '0;
                 ==>
132            end else begin
133              data_invalid_q <= data_invalid_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

151            if (!rst_ni) begin
               -1-  
152              idx <= '0;
                 ==>
153            end else if (pack_valid && idx == MaxIdx) begin
                        -2-  
154              // when a flash word is packed full, return index to 0
155              idx <= '0;
                 ==>
156            end else if (pack_valid) begin
                        -3-  
157              // increment otherwise
158              idx <= idx + 1'b1;
                 ==>
159            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

164          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle)
             -1-                                                                      
             ==>                                                                      
             ==>                                                                      

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

186            unique case (state_q)
                      -1-  
187              StIdle: begin
188                // if first beat of a transaction is not aligned, prepack with empty bits
189                if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) begin
                   -2-  
190                  // only disable during idle state to ensure program is able to gracefully complete
191                  // this is important as we do not want to accidentally disturb any electrical procedure
192                  // internal to the flash macro
193                  state_d = StDisabled;
                     ==>
194                end else if (req_i && |sel_i) begin
                            -3-  
195                  state_d = StPrePack;
                     ==>
196                end else if (req_i) begin
                            -4-  
197                  state_d = StPackData;
                     ==>
198                end
                   MISSING_ELSE
                   ==>
199              end
200        
201              StPrePack: begin
202                // pack until currently supplied data
203                pack_valid = (idx < sel_i);
204                if (idx == align_next) begin
                   -5-  
205                  state_d = StPackData;
                     ==>
206                end
                   MISSING_ELSE
                   ==>
207              end
208        
209              StPackData: begin
210                pack_valid = req_i;
211                data_sel = Actual;
212        
213                if (req_i && idx == MaxIdx) begin
                   -6-  
214                  // last beat of a flash word
215                  state_d = StCalcPlainEcc;
                     ==>
216                end else if (req_i && last_i) begin
                            -7-  
217                  // last beat is not aligned with the last entry of flash word
218                  state_d = StPostPack;
                     ==>
219                end else if (req_i) begin
                            -8-  
220                  ack_o = 1'b1;
                     ==>
221                end
                   MISSING_ELSE
                   ==>
222              end
223        
224              StPostPack: begin
225                // supply filler data
226                pack_valid = 1'b1;
227                data_sel = Filler;
228        
229                // finish packing remaining entries
230                if (idx == MaxIdx) begin
                   -9-  
231                  state_d = StCalcPlainEcc;
                     ==>
232                end
                   MISSING_ELSE
                   ==>
233              end
234        
235              StCalcPlainEcc: begin
236                plain_ecc_en = 1'b1;
237                state_d = scramble_i ? StCalcMask : StReqFlash;
                                        -10-  
                                        ==>  
                                        ==>  
238              end
239        
240              StCalcMask: begin
241                calc_req_o = 1'b1;
242        
243                if (calc_ack_i) begin
                   -11-  
244                  state_d = StScrambleData;
                     ==>
245                end
                   MISSING_ELSE
                   ==>
246              end
247        
248              StScrambleData: begin
249                scramble_req_o = 1'b1;
250        
251                if (scramble_ack_i) begin
                   -12-  
252                  state_d = StCalcEcc;
                     ==>
253                end
                   MISSING_ELSE
                   ==>
254              end
255        
256              StCalcEcc: begin
257                state_d = StReqFlash;
                   ==>
258              end
259        
260              StReqFlash: begin
261                // only request flash if data integrity was valid
262                req_o = ~data_invalid_q;
263                last_o = last_i;
264        
265                // if this is the last beat of the program burst
266                //   - wait for done
267                // if this is NOT the last beat
268                //   - ack the upstream request and accept more beats
269                if (last_i) begin
                   -13-  
270                  state_d = ack ? StWaitFlash : StReqFlash;
                                   -14-  
                                   ==>  
                                   ==>  
271                end else begin
272                  ack_o = ack;
273                  state_d = ack ? StIdle : StReqFlash;
                                   -15-  
                                   ==>  
                                   ==>  
274                end
275              end
276        
277              StWaitFlash: begin
278                if (done) begin
                   -16-  
279                  ack_o = 1'b1;
                     ==>
280                  state_d = StIdle;
281                end
                   MISSING_ELSE
                   ==>
282              end
283        
284              StDisabled: begin
285                state_d = StDisabled;
                   ==>
286              end
287        
288              default: begin
289                fsm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T35,T67
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T35,T67
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T24,T172,T35
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T24,T172,T35
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T4,T5
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T9,T34
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T4,T5
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T4,T5
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T4,T5
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T4,T5
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T2,T5,T9
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T2,T5,T9
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T2,T4,T5
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T2,T5,T9
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T5,T9
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T5,T9
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

299            if (!rst_ni) begin
               -1-  
300              packed_data <= '0;
                 ==>
301              mask_q <= '0;
302            end else if (req_o && ack) begin
                        -2-  
303              packed_data <= '0;
                 ==>
304            end else if (calc_req_o && calc_ack_i) begin
                        -3-  
305              packed_data <= packed_data ^ mask_i;
                 ==>
306              mask_q <= mask_i;
307            end else if (scramble_req_o && scramble_ack_i) begin
                        -4-  
308              packed_data <= scrambled_data_i[DataWidth-1:0] ^ mask_q;
                 ==>
309            end else if (pack_valid) begin
                        -5-  
310              packed_data[idx] <= pack_data;
                 ==>
311            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T2,T4,T5
0	0	1	-	-	Covered	T1,T4,T5
0	0	0	1	-	Covered	T1,T4,T5
0	0	0	0	1	Covered	T1,T2,T4
0	0	0	0	0	Covered	T1,T2,T3

323            if (!rst_ni) begin
               -1-  
324              plain_data_ecc <= '1;
                 ==>
325            end else if (plain_ecc_en) begin
                        -2-  
326              plain_data_ecc <= plain_data_w_ecc[DataWidth +: PlainIntgWidth];
                 ==>
327            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

369            if (!rst_ni) begin
               -1-  
370              done_cnt_q <= '0;
                 ==>
371            end else begin
372              done_cnt_q <= done_cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	332875393	1143907	0	0
PostPackRule_A	332875393	597	0	0
PrePackRule_A	332875393	463	0	0
WidthCheck_A	1026	1026	0	0
u_state_regs_A	332875393	332008659	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	1143907	0	0
T2	3694	14	0	0
T3	2283	0	0	0
T4	4375	0	0	0
T5	1250	1	0	0
T6	873	0	0	0
T8	51282	0	0	0
T9	0	1	0	0
T15	949	0	0	0
T16	1834	0	0	0
T17	1845	0	0	0
T19	0	15	0	0
T20	1105	0	0	0
T24	0	2	0	0
T28	0	49	0	0
T34	0	2	0	0
T36	0	109	0	0
T37	0	611	0	0
T58	0	1	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	597	0	0
T24	3170	2	0	0
T28	209634	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T35	0	13	0	0
T42	116819	0	0	0
T51	64411	0	0	0
T56	11447	0	0	0
T58	2280	0	0	0
T65	1393	0	0	0
T67	0	14	0	0
T68	0	16	0	0
T107	6959	0	0	0
T142	221130	0	0	0
T172	1231	1	0	0
T178	0	2	0	0
T236	0	2	0	0
T243	0	1	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	463	0	0
T24	3170	2	0	0
T28	209634	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T35	0	14	0	0
T42	116819	0	0	0
T51	64411	0	0	0
T56	11447	0	0	0
T58	2280	0	0	0
T65	1393	0	0	0
T67	0	17	0	0
T68	0	16	0	0
T95	0	7	0	0
T107	6959	0	0	0
T142	221130	0	0	0
T172	1231	0	0	0
T178	0	3	0	0
T236	0	3	0	0
T243	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	332008659	0	0
T1	1475	1361	0	0
T2	3694	3600	0	0
T3	2283	2194	0	0
T4	4375	3852	0	0
T5	1250	1151	0	0
T6	873	776	0	0
T8	51282	51232	0	0
T15	949	886	0	0
T16	1834	1745	0	0
T17	1845	1746	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

110                       // selects empty data or real data
111        1/1            assign pack_data  = (data_sel == Actual) ? data_i[BusWidth-1:0] : {BusWidth{1'b1}};
           Tests:       T1 T2 T3 
112                     
113                       logic data_intg_ok;
114                       logic data_err;
115                     
116                       // use the tlul integrity module directly for bus integrity
117                       // SEC_CM: MEM.BUS.INTEGRITY
118                       tlul_data_integ_dec u_data_intg_chk (
119                         .data_intg_i(data_i),
120                         .data_err_o(data_err)
121                       );
122        1/1            assign data_intg_ok = ~data_err;
           Tests:       T1 T2 T3 
123                     
124                       logic data_invalid_q, data_invalid_d;
125                       // hold on integrity failure indication until reset
126        1/1            assign data_invalid_d = data_invalid_q |
           Tests:       T1 T2 T3 
127                                               (pack_valid & ~data_intg_ok);
128                     
129                       always_ff @(posedge clk_i or negedge rst_ni) begin
130        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
131        1/1                data_invalid_q <= '0;
           Tests:       T1 T2 T3 
132                         end else begin
133        1/1                data_invalid_q <= data_invalid_d;
           Tests:       T1 T2 T3 
134                         end
135                       end
136                     
137                       // indication to upper layer presence of error
138        1/1            assign intg_err_o = data_invalid_q;
           Tests:       T1 T2 T3 
139                     
140                       // if integrity failure is seen, fake communication with flash
141                       // and simply terminate
142                       logic ack, done;
143        1/1            assign ack = ack_i | data_invalid_q;
           Tests:       T1 T2 T3 
144        1/1            assign done = done_i | data_invalid_q;
           Tests:       T1 T2 T3 
145                     
146                       // next idx will be aligned
147        1/1            assign idx_sub_one = idx - 1'b1;
           Tests:       T1 T2 T3 
148        1/1            assign align_next = (idx > '0) ? (idx_sub_one == sel_i) : 1'b0;
           Tests:       T1 T2 T3 
149                     
150                       always_ff @(posedge clk_i or negedge rst_ni) begin
151        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
152        1/1                idx <= '0;
           Tests:       T1 T2 T3 
153        1/1              end else if (pack_valid && idx == MaxIdx) begin
           Tests:       T1 T2 T3 
154                           // when a flash word is packed full, return index to 0
155        1/1                idx <= '0;
           Tests:       T4 T33 T34 
156        1/1              end else if (pack_valid) begin
           Tests:       T1 T2 T3 
157                           // increment otherwise
158        1/1                idx <= idx + 1'b1;
           Tests:       T4 T33 T34 
159                         end
                        MISSING_ELSE
160                       end
161                     
162                     
163                       // SEC_CM: PHY_PROG.FSM.SPARSE
164        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle):
164.1                   `ifdef SIMULATION                                   
164.2                       prim_sparse_fsm_flop #(                           
164.3                         .StateEnumT(state_e),                            
164.4                         .Width($bits(state_e)),                          
164.5                         .ResetValue($bits(state_e)'(StIdle)),          
164.6                         .EnableAlertTriggerSVA(1), 
164.7                         .CustomForceName("state_q")          
164.8                       ) u_state_regs (                                        
164.9                         .clk_i   ( clk_i   ),                           
164.10                        .rst_ni  ( rst_ni ),                           
164.11                        .state_i ( state_d     ),                           
164.12                        .state_o (         )                            
164.13                      );                                                
164.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
164.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
164.16     1/1                state_q <= StIdle;                                
           Tests:       T1 T2 T3 
164.17                      end else begin                                    
164.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
164.19                      end                                               
164.20                    end  
164.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
164.22                      else begin                                                                           
164.23                        `ifdef UVM                                                                               
164.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
164.25                                              "../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv", 164, "", 1);                                
164.26                  `else                                                                                    
164.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
164.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
164.29                  `endif                                                              
164.30                      end 
164.31                    `else                                               
164.32                      prim_sparse_fsm_flop #(                           
164.33                        .StateEnumT(state_e),                            
164.34                        .Width($bits(state_e)),                          
164.35                        .ResetValue($bits(state_e)'(StIdle)),          
164.36                        .EnableAlertTriggerSVA(1)  
164.37                      ) u_state_regs (                                        
164.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
164.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
164.40                        .state_i ( state_d     ),                           
164.41                        .state_o ( state_q     )                            
164.42                      );                                                
164.43                    `endif165                     
166                       // If the first beat of an incoming transaction is not aligned to word boundary (for example
167                       // if each flash word is 4 bus words wide, and the first word to program starts at index 1),
168                       // the fsm pre-packs the flash word with empty words until the supplied index.
169                       // Once at the index, real data supplied from the flash controller is packed until the last
170                       // beat of data.  At the last beat of data, if it is not also aligned (index 3 in this example),
171                       // more empty words are packed at the end to fill out the word.
172                       //
173                       always_comb begin
174        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
175                     
176        1/1              pack_valid = 1'b0;
           Tests:       T1 T2 T3 
177        1/1              data_sel = Filler;
           Tests:       T1 T2 T3 
178        1/1              plain_ecc_en = 1'b0;
           Tests:       T1 T2 T3 
179        1/1              req_o = 1'b0;
           Tests:       T1 T2 T3 
180        1/1              ack_o = 1'b0;
           Tests:       T1 T2 T3 
181        1/1              last_o = 1'b0;
           Tests:       T1 T2 T3 
182        1/1              calc_req_o = 1'b0;
           Tests:       T1 T2 T3 
183        1/1              scramble_req_o = 1'b0;
           Tests:       T1 T2 T3 
184        1/1              fsm_err_o = 1'b0;
           Tests:       T1 T2 T3 
185                     
186        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
187                           StIdle: begin
188                             // if first beat of a transaction is not aligned, prepack with empty bits
189        1/1                  if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) begin
           Tests:       T1 T2 T3 
190                               // only disable during idle state to ensure program is able to gracefully complete
191                               // this is important as we do not want to accidentally disturb any electrical procedure
192                               // internal to the flash macro
193        1/1                    state_d = StDisabled;
           Tests:       T4 T5 T6 
194        1/1                  end else if (req_i && |sel_i) begin
           Tests:       T1 T2 T3 
195        1/1                    state_d = StPrePack;
           Tests:       T78 T35 T29 
196        1/1                  end else if (req_i) begin
           Tests:       T1 T2 T3 
197        1/1                    state_d = StPackData;
           Tests:       T4 T33 T34 
198                             end
                        MISSING_ELSE
199                           end
200                     
201                           StPrePack: begin
202                             // pack until currently supplied data
203        1/1                  pack_valid = (idx < sel_i);
           Tests:       T78 T35 T29 
204        1/1                  if (idx == align_next) begin
           Tests:       T78 T35 T29 
205        1/1                    state_d = StPackData;
           Tests:       T78 T35 T29 
206                             end
                   ==>  MISSING_ELSE
207                           end
208                     
209                           StPackData: begin
210        1/1                  pack_valid = req_i;
           Tests:       T4 T33 T34 
211        1/1                  data_sel = Actual;
           Tests:       T4 T33 T34 
212                     
213        1/1                  if (req_i && idx == MaxIdx) begin
           Tests:       T4 T33 T34 
214                               // last beat of a flash word
215        1/1                    state_d = StCalcPlainEcc;
           Tests:       T4 T33 T34 
216        1/1                  end else if (req_i && last_i) begin
           Tests:       T4 T33 T34 
217                               // last beat is not aligned with the last entry of flash word
218        1/1                    state_d = StPostPack;
           Tests:       T78 T24 T35 
219        1/1                  end else if (req_i) begin
           Tests:       T4 T33 T34 
220        1/1                    ack_o = 1'b1;
           Tests:       T4 T33 T34 
221                             end
                        MISSING_ELSE
222                           end
223                     
224                           StPostPack: begin
225                             // supply filler data
226        1/1                  pack_valid = 1'b1;
           Tests:       T78 T24 T35 
227        1/1                  data_sel = Filler;
           Tests:       T78 T24 T35 
228                     
229                             // finish packing remaining entries
230        1/1                  if (idx == MaxIdx) begin
           Tests:       T78 T24 T35 
231        1/1                    state_d = StCalcPlainEcc;
           Tests:       T78 T24 T35 
232                             end
                   ==>  MISSING_ELSE
233                           end
234                     
235                           StCalcPlainEcc: begin
236        1/1                  plain_ecc_en = 1'b1;
           Tests:       T4 T33 T34 
237        1/1                  state_d = scramble_i ? StCalcMask : StReqFlash;
           Tests:       T4 T33 T34 
238                           end
239                     
240                           StCalcMask: begin
241        1/1                  calc_req_o = 1'b1;
           Tests:       T4 T33 T85 
242                     
243        1/1                  if (calc_ack_i) begin
           Tests:       T4 T33 T85 
244        1/1                    state_d = StScrambleData;
           Tests:       T4 T33 T85 
245                             end
                        MISSING_ELSE
246                           end
247                     
248                           StScrambleData: begin
249        1/1                  scramble_req_o = 1'b1;
           Tests:       T4 T33 T85 
250                     
251        1/1                  if (scramble_ack_i) begin
           Tests:       T4 T33 T85 
252        1/1                    state_d = StCalcEcc;
           Tests:       T4 T33 T85 
253                             end
                        MISSING_ELSE
254                           end
255                     
256                           StCalcEcc: begin
257        1/1                  state_d = StReqFlash;
           Tests:       T4 T33 T85 
258                           end
259                     
260                           StReqFlash: begin
261                             // only request flash if data integrity was valid
262        1/1                  req_o = ~data_invalid_q;
           Tests:       T4 T33 T34 
263        1/1                  last_o = last_i;
           Tests:       T4 T33 T34 
264                     
265                             // if this is the last beat of the program burst
266                             //   - wait for done
267                             // if this is NOT the last beat
268                             //   - ack the upstream request and accept more beats
269        1/1                  if (last_i) begin
           Tests:       T4 T33 T34 
270        1/1                    state_d = ack ? StWaitFlash : StReqFlash;
           Tests:       T33 T34 T36 
271                             end else begin
272        1/1                    ack_o = ack;
           Tests:       T4 T33 T36 
273        1/1                    state_d = ack ? StIdle : StReqFlash;
           Tests:       T4 T33 T36 
274                             end
275                           end
276                     
277                           StWaitFlash: begin
278        1/1                  if (done) begin
           Tests:       T33 T34 T36 
279        1/1                    ack_o = 1'b1;
           Tests:       T33 T34 T36 
280        1/1                    state_d = StIdle;
           Tests:       T33 T34 T36 
281                             end
                        MISSING_ELSE
282                           end
283                     
284                           StDisabled: begin
285        1/1                  state_d = StDisabled;
           Tests:       T4 T5 T6 
286                           end
287                     
288                           default: begin
289                             fsm_err_o = 1'b1;
290                           end
291                     
292                         endcase // unique case (state_q)
293                     
294                       end
295                     
296                       logic [DataWidth-1:0] mask_q;
297                     
298                       always_ff @(posedge clk_i or negedge rst_ni) begin
299        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
300        1/1                packed_data <= '0;
           Tests:       T1 T2 T3 
301        1/1                mask_q <= '0;
           Tests:       T1 T2 T3 
302        1/1              end else if (req_o && ack) begin
           Tests:       T1 T2 T3 
303        1/1                packed_data <= '0;
           Tests:       T4 T33 T34 
304        1/1              end else if (calc_req_o && calc_ack_i) begin
           Tests:       T1 T2 T3 
305        1/1                packed_data <= packed_data ^ mask_i;
           Tests:       T4 T33 T85 
306        1/1                mask_q <= mask_i;
           Tests:       T4 T33 T85 
307        1/1              end else if (scramble_req_o && scramble_ack_i) begin
           Tests:       T1 T2 T3 
308        1/1                packed_data <= scrambled_data_i[DataWidth-1:0] ^ mask_q;
           Tests:       T4 T33 T85 
309        1/1              end else if (pack_valid) begin
           Tests:       T1 T2 T3 
310        1/1                packed_data[idx] <= pack_data;
           Tests:       T4 T33 T34 
311                         end
                        MISSING_ELSE
312                       end
313                     
314        1/1            assign block_data_o = packed_data;
           Tests:       T1 T2 T3 
315                     
316                       // ECC handling
317                       localparam int PlainDataEccWidth = DataWidth + 8;
318                     
319                       logic [FullDataWidth-1:0] ecc_data;
320                       logic [PlainDataEccWidth-1:0] plain_data_w_ecc;
321                       logic [PlainIntgWidth-1:0] plain_data_ecc;
322                       always_ff @(posedge clk_i or negedge rst_ni) begin
323        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
324        1/1                plain_data_ecc <= '1;
           Tests:       T1 T2 T3 
325        1/1              end else if (plain_ecc_en) begin
           Tests:       T1 T2 T3 
326        1/1                plain_data_ecc <= plain_data_w_ecc[DataWidth +: PlainIntgWidth];
           Tests:       T4 T33 T34 
327                         end
                        MISSING_ELSE
328                       end
329                     
330                       logic [PlainDataWidth-1:0] ecc_data_in;
331        1/1            assign ecc_data_in = {plain_data_ecc, packed_data};
           Tests:       T1 T2 T3 
332                     
333                       // reliability ECC calculation
334                       prim_secded_hamming_76_68_enc u_enc (
335                         .data_i(ecc_data_in),
336                         .data_o(ecc_data)
337                       );
338                     
339                       // integrity ECC calculation
340                       // This instance can technically be merged with the instance above, but is
341                       // kept separate for the sake of convenience
342                       // The plain data ecc is calculated continuously from packed data (which changes
343                       // from packed data to masked/scrambled data based on software configuration).
344                       // The actual plain data ECC is explicitly captured during this process when
345                       // it is required.
346                       prim_secded_hamming_72_64_enc u_plain_enc (
347                         .data_i(packed_data),
348                         .data_o(plain_data_w_ecc)
349                       );
350                     
351                       logic unused_data;
352        1/1            assign unused_data = |plain_data_w_ecc;
           Tests:       T1 T2 T3 
353                     
354                       // pad the remaining bits with '1' if ecc is not used.
355        1/1            assign data_o = ecc_i ? ecc_data : {{EccWidth{1'b1}}, ecc_data_in};
           Tests:       T1 T2 T3 
356                     
357                       /////////////////////////////////
358                       // Assertions
359                       /////////////////////////////////
360                     
361                     `ifdef INC_ASSERT
362                       logic txn_done;
363                       logic [15:0] done_cnt_d, done_cnt_q;
364                     
365        1/1            assign txn_done = req_i && ack_o && last_i;
           Tests:       T1 T2 T3 
366        1/1            assign done_cnt_d = txn_done ? '0 : (done ? done_cnt_q + 16'h1 : done_cnt_q);
           Tests:       T1 T2 T3 
367                     
368                       always_ff @(posedge clk_i or negedge rst_ni) begin
369        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
370        1/1                done_cnt_q <= '0;
           Tests:       T1 T2 T3 
371                         end else begin
372        1/1                done_cnt_q <= done_cnt_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	62	95.38
Logical	65	62	95.38
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T33,T34

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T33,T34

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T18
1	0	Covered	T4,T18

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T33,T34
1	1	Covered	T4,T18

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T18
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T18
1	0	Covered	T16,T8,T17

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T33,T34

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T33,T34
1	Covered	T78,T24,T35

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T33,T34
1	0	Covered	T4,T33,T34
1	1	Covered	T4,T33,T34

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T33,T34

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T33,T34
1	1	Covered	T78,T35,T29

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T78,T35,T29

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T33,T34
1	0	Covered	T4,T33,T34
1	1	Covered	T4,T33,T34

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T4,T33,T34
1	Covered	T4,T33,T34

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T33,T34
1	0	Covered	T4,T33,T34
1	1	Covered	T78,T24,T35

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Not Covered
1	Covered	T78,T24,T35

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T4,T34,T36
1	Covered	T4,T33,T85

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T33,T36,T37
1	Covered	T33,T34,T36

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T33,T36
1	Covered	T4,T33,T36

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T33,T36
1	1	Covered	T4,T33,T34

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T16,T10,T11
1	0	Covered	T4,T33,T85
1	1	Covered	T4,T33,T85

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T16,T34,T27
1	0	Covered	T4,T33,T85
1	1	Covered	T4,T33,T85

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T33,T34
1	1	0	Covered	T4,T33,T34
1	1	1	Covered	T33,T34,T36

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T33,T34,T36

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T16,T8

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T4,T33,T85
StCalcMask	237	Covered	T4,T33,T85
StCalcPlainEcc	215	Covered	T4,T33,T34
StDisabled	193	Covered	T4,T5,T6
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T4,T33,T34
StPostPack	218	Covered	T78,T24,T35
StPrePack	195	Covered	T78,T35,T29
StReqFlash	237	Covered	T4,T33,T34
StScrambleData	244	Covered	T4,T33,T85
StWaitFlash	270	Covered	T33,T34,T36

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T4,T33,T85
StCalcMask->StScrambleData	244	Covered	T4,T33,T85
StCalcPlainEcc->StCalcMask	237	Covered	T4,T33,T85
StCalcPlainEcc->StReqFlash	237	Covered	T4,T34,T36
StIdle->StDisabled	193	Covered	T4,T5,T6
StIdle->StPackData	197	Covered	T4,T33,T34
StIdle->StPrePack	195	Covered	T78,T35,T29
StPackData->StCalcPlainEcc	215	Covered	T4,T33,T34
StPackData->StPostPack	218	Covered	T78,T24,T35
StPostPack->StCalcPlainEcc	231	Covered	T78,T24,T35
StPrePack->StPackData	205	Covered	T78,T35,T29
StReqFlash->StIdle	273	Covered	T4,T33,T36
StReqFlash->StWaitFlash	270	Covered	T33,T34,T36
StScrambleData->StCalcEcc	252	Covered	T4,T33,T85
StWaitFlash->StIdle	280	Covered	T33,T34,T36

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	53	96.36
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	25	92.59
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

111          assign pack_data  = (data_sel == Actual) ? data_i[BusWidth-1:0] : {BusWidth{1'b1}};
                                                      -1-  
                                                      ==>  
                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T33,T34
0	Covered	T1,T2,T3

148          assign align_next = (idx > '0) ? (idx_sub_one == sel_i) : 1'b0;
                                            -1-  
                                            ==>  
                                            ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T33,T34
0	Covered	T1,T2,T3

355          assign data_o = ecc_i ? ecc_data : {{EccWidth{1'b1}}, ecc_data_in};
                                   -1-  
                                   ==>  
                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

366          assign done_cnt_d = txn_done ? '0 : (done ? done_cnt_q + 16'h1 : done_cnt_q);
                                          -1-          -2-   
                                          ==>          ==>   
                                                       ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T33,T34,T36
0	1	Covered	T4,T16,T8
0	0	Covered	T1,T2,T3

130            if (!rst_ni) begin
               -1-  
131              data_invalid_q <= '0;
                 ==>
132            end else begin
133              data_invalid_q <= data_invalid_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

151            if (!rst_ni) begin
               -1-  
152              idx <= '0;
                 ==>
153            end else if (pack_valid && idx == MaxIdx) begin
                        -2-  
154              // when a flash word is packed full, return index to 0
155              idx <= '0;
                 ==>
156            end else if (pack_valid) begin
                        -3-  
157              // increment otherwise
158              idx <= idx + 1'b1;
                 ==>
159            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T33,T34
0	0	1	Covered	T4,T33,T34
0	0	0	Covered	T1,T2,T3

164          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle)
             -1-                                                                      
             ==>                                                                      
             ==>                                                                      

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

186            unique case (state_q)
                      -1-  
187              StIdle: begin
188                // if first beat of a transaction is not aligned, prepack with empty bits
189                if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) begin
                   -2-  
190                  // only disable during idle state to ensure program is able to gracefully complete
191                  // this is important as we do not want to accidentally disturb any electrical procedure
192                  // internal to the flash macro
193                  state_d = StDisabled;
                     ==>
194                end else if (req_i && |sel_i) begin
                            -3-  
195                  state_d = StPrePack;
                     ==>
196                end else if (req_i) begin
                            -4-  
197                  state_d = StPackData;
                     ==>
198                end
                   MISSING_ELSE
                   ==>
199              end
200        
201              StPrePack: begin
202                // pack until currently supplied data
203                pack_valid = (idx < sel_i);
204                if (idx == align_next) begin
                   -5-  
205                  state_d = StPackData;
                     ==>
206                end
                   MISSING_ELSE
                   ==>
207              end
208        
209              StPackData: begin
210                pack_valid = req_i;
211                data_sel = Actual;
212        
213                if (req_i && idx == MaxIdx) begin
                   -6-  
214                  // last beat of a flash word
215                  state_d = StCalcPlainEcc;
                     ==>
216                end else if (req_i && last_i) begin
                            -7-  
217                  // last beat is not aligned with the last entry of flash word
218                  state_d = StPostPack;
                     ==>
219                end else if (req_i) begin
                            -8-  
220                  ack_o = 1'b1;
                     ==>
221                end
                   MISSING_ELSE
                   ==>
222              end
223        
224              StPostPack: begin
225                // supply filler data
226                pack_valid = 1'b1;
227                data_sel = Filler;
228        
229                // finish packing remaining entries
230                if (idx == MaxIdx) begin
                   -9-  
231                  state_d = StCalcPlainEcc;
                     ==>
232                end
                   MISSING_ELSE
                   ==>
233              end
234        
235              StCalcPlainEcc: begin
236                plain_ecc_en = 1'b1;
237                state_d = scramble_i ? StCalcMask : StReqFlash;
                                        -10-  
                                        ==>  
                                        ==>  
238              end
239        
240              StCalcMask: begin
241                calc_req_o = 1'b1;
242        
243                if (calc_ack_i) begin
                   -11-  
244                  state_d = StScrambleData;
                     ==>
245                end
                   MISSING_ELSE
                   ==>
246              end
247        
248              StScrambleData: begin
249                scramble_req_o = 1'b1;
250        
251                if (scramble_ack_i) begin
                   -12-  
252                  state_d = StCalcEcc;
                     ==>
253                end
                   MISSING_ELSE
                   ==>
254              end
255        
256              StCalcEcc: begin
257                state_d = StReqFlash;
                   ==>
258              end
259        
260              StReqFlash: begin
261                // only request flash if data integrity was valid
262                req_o = ~data_invalid_q;
263                last_o = last_i;
264        
265                // if this is the last beat of the program burst
266                //   - wait for done
267                // if this is NOT the last beat
268                //   - ack the upstream request and accept more beats
269                if (last_i) begin
                   -13-  
270                  state_d = ack ? StWaitFlash : StReqFlash;
                                   -14-  
                                   ==>  
                                   ==>  
271                end else begin
272                  ack_o = ack;
273                  state_d = ack ? StIdle : StReqFlash;
                                   -15-  
                                   ==>  
                                   ==>  
274                end
275              end
276        
277              StWaitFlash: begin
278                if (done) begin
                   -16-  
279                  ack_o = 1'b1;
                     ==>
280                  state_d = StIdle;
281                end
                   MISSING_ELSE
                   ==>
282              end
283        
284              StDisabled: begin
285                state_d = StDisabled;
                   ==>
286              end
287        
288              default: begin
289                fsm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T78,T35,T29
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T33,T34
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T78,T35,T29
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T33,T34
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T78,T24,T35
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T4,T33,T34
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T4,T33,T34
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T78,T24,T35
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T33,T85
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T4,T34,T36
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T4,T33,T85
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T4,T33,T85
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T4,T33,T85
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T4,T33,T85
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T33,T85
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T33,T34,T36
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T33,T36,T37
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T4,T33,T36
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T4,T33,T36
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T33,T34,T36
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T33,T34,T36
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

299            if (!rst_ni) begin
               -1-  
300              packed_data <= '0;
                 ==>
301              mask_q <= '0;
302            end else if (req_o && ack) begin
                        -2-  
303              packed_data <= '0;
                 ==>
304            end else if (calc_req_o && calc_ack_i) begin
                        -3-  
305              packed_data <= packed_data ^ mask_i;
                 ==>
306              mask_q <= mask_i;
307            end else if (scramble_req_o && scramble_ack_i) begin
                        -4-  
308              packed_data <= scrambled_data_i[DataWidth-1:0] ^ mask_q;
                 ==>
309            end else if (pack_valid) begin
                        -5-  
310              packed_data[idx] <= pack_data;
                 ==>
311            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T4,T33,T34
0	0	1	-	-	Covered	T4,T33,T85
0	0	0	1	-	Covered	T4,T33,T85
0	0	0	0	1	Covered	T4,T33,T34
0	0	0	0	0	Covered	T1,T2,T3

323            if (!rst_ni) begin
               -1-  
324              plain_data_ecc <= '1;
                 ==>
325            end else if (plain_ecc_en) begin
                        -2-  
326              plain_data_ecc <= plain_data_w_ecc[DataWidth +: PlainIntgWidth];
                 ==>
327            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T33,T34
0	0	Covered	T1,T2,T3

369            if (!rst_ni) begin
               -1-  
370              done_cnt_q <= '0;
                 ==>
371            end else begin
372              done_cnt_q <= done_cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	332875393	1100168	0	0
PostPackRule_A	332875393	632	0	0
PrePackRule_A	332875393	458	0	0
WidthCheck_A	1026	1026	0	0
u_state_regs_A	332875393	332008659	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	1100168	0	0
T19	84564	0	0	0
T24	0	1	0	0
T27	7017	0	0	0
T28	0	51	0	0
T33	1654	1	0	0
T34	2997	1	0	0
T35	0	32	0	0
T36	30072	34	0	0
T37	207944	710	0	0
T51	0	213	0	0
T64	6270	0	0	0
T66	1241	0	0	0
T78	2116	1	0	0
T84	0	205	0	0
T120	5764	0	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	632	0	0
T23	1309	0	0	0
T24	3170	1	0	0
T28	209634	0	0	0
T29	0	3	0	0
T31	0	1	0	0
T35	0	17	0	0
T42	116819	0	0	0
T51	64411	0	0	0
T56	11447	0	0	0
T58	2280	0	0	0
T65	1393	0	0	0
T67	0	19	0	0
T68	0	19	0	0
T78	2116	1	0	0
T107	6959	0	0	0
T236	0	3	0	0
T243	0	2	0	0
T244	0	2	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	458	0	0
T23	1309	0	0	0
T24	3170	0	0	0
T28	209634	0	0	0
T29	0	3	0	0
T30	0	1	0	0
T35	0	14	0	0
T42	116819	0	0	0
T51	64411	0	0	0
T56	11447	0	0	0
T58	2280	0	0	0
T65	1393	0	0	0
T67	0	12	0	0
T68	0	10	0	0
T78	2116	1	0	0
T95	0	3	0	0
T107	6959	0	0	0
T236	0	1	0	0
T243	0	2	0	0
T244	0	2	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	332875393	332008659	0	0
T1	1475	1361	0	0
T2	3694	3600	0	0
T3	2283	2194	0	0
T4	4375	3852	0	0
T5	1250	1151	0	0
T6	873	776	0	0
T8	51282	51232	0	0
T15	949	886	0	0
T16	1834	1745	0	0
T17	1845	1746	0	0