Line Coverage for Module : tlul_lc_gate
Cond Coverage for Module : tlul_lc_gate
FSM Coverage for Module : tlul_lc_gate
State, Transition and Sequence Details for FSM :: state_q
Branch Coverage for Module : tlul_lc_gate
Branches:
Branches:
Branches:
Branches:
Branches:
Assert Coverage for Module : tlul_lc_gate
Assertion Details
OutStandingOvfl_A
u_state_regs_A
| Line No. | Total | Covered | Percent | |
|---|---|---|---|---|
| TOTAL | 51 | 51 | 100.00 | |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| ALWAYS | 144 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| ALWAYS | 153 | 6 | 6 | 100.00 |
| ALWAYS | 164 | 28 | 28 | 100.00 |
| ALWAYS | 230 | 10 | 10 | 100.00 |
83 // Assign signals on the device side. 84 1/1 assign tl_h2d_o = tl_h2d_int[NumGatesPerDirection]; Tests: T1 T2 T3 85 1/1 assign tl_d2h_int[NumGatesPerDirection] = tl_d2h_i; Tests: T1 T2 T3 86 87 /////////////////////////// 88 // Host Side Interposing // 89 /////////////////////////// 90 91 // Encoding generated with: 92 // $ ./util/design/sparse-fsm-encode.py -d 5 -m 4 -n 8 \ 93 // -s 3379253306 --language=sv 94 // 95 // Hamming distance histogram: 96 // 97 // 0: -- 98 // 1: -- 99 // 2: -- 100 // 3: -- 101 // 4: -- 102 // 5: |||||||||||||||||||| (66.67%) 103 // 6: |||||||||| (33.33%) 104 // 7: -- 105 // 8: -- 106 // 107 // Minimum Hamming distance: 5 108 // Maximum Hamming distance: 6 109 // Minimum Hamming weight: 3 110 // Maximum Hamming weight: 5 111 // 112 // Encoding generated with: 113 // $ ./util/design/sparse-fsm-encode.py -d 5 -m 5 -n 9 \ 114 // -s 686407169 --language=sv 115 // 116 // Hamming distance histogram: 117 // 118 // 0: -- 119 // 1: -- 120 // 2: -- 121 // 3: -- 122 // 4: -- 123 // 5: |||||||||||||||||||| (60.00%) 124 // 6: ||||||||||||| (40.00%) 125 // 7: -- 126 // 8: -- 127 // 9: -- 128 // 129 // Minimum Hamming distance: 5 130 // Maximum Hamming distance: 6 131 // Minimum Hamming weight: 3 132 // Maximum Hamming weight: 6 133 // 134 localparam int StateWidth = 9; 135 typedef enum logic [StateWidth-1:0] { 136 StActive = 9'b100100001, 137 StOutstanding = 9'b011100111, 138 StFlush = 9'b001001100, 139 StError = 9'b010111010, 140 StErrorOutstanding = 9'b100010110 141 } state_e; 142 143 state_e state_d, state_q;144 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StError) Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StError): 144.1 `ifdef SIMULATION 144.2 prim_sparse_fsm_flop #( 144.3 .StateEnumT(state_e), 144.4 .Width($bits(state_e)), 144.5 .ResetValue($bits(state_e)'(StError)), 144.6 .EnableAlertTriggerSVA(1), 144.7 .CustomForceName("state_q") 144.8 ) u_state_regs ( 144.9 .clk_i ( clk_i ), 144.10 .rst_ni ( rst_ni ), 144.11 .state_i ( state_d ), 144.12 .state_o ( ) 144.13 ); 144.14 always_ff @(posedge clk_i or negedge rst_ni) begin 144.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3 144.16 1/1 state_q <= StError; Tests: T1 T2 T3 144.17 end else begin 144.18 1/1 state_q <= state_d; Tests: T1 T2 T3 144.19 end 144.20 end 144.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 144.22 else begin 144.23 `ifdef UVM 144.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 144.25 "../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv", 144, "", 1); 144.26 `else 144.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 144.28 `PRIM_STRINGIFY(u_state_regs_A)); 144.29 `endif 144.30 end 144.31 `else 144.32 prim_sparse_fsm_flop #( 144.33 .StateEnumT(state_e), 144.34 .Width($bits(state_e)), 144.35 .ResetValue($bits(state_e)'(StError)), 144.36 .EnableAlertTriggerSVA(1) 144.37 ) u_state_regs ( 144.38 .clk_i ( `PRIM_FLOP_CLK ), 144.39 .rst_ni ( `PRIM_FLOP_RST ), 144.40 .state_i ( state_d ), 144.41 .state_o ( state_q ) 144.42 ); 144.43 `endif145 146 logic [1:0] outstanding_txn; 147 logic a_ack; 148 logic d_ack; 149 1/1 assign a_ack = tl_h2d_i.a_valid & tl_d2h_o.a_ready; Tests: T1 T2 T3 150 1/1 assign d_ack = tl_h2d_i.d_ready & tl_d2h_o.d_valid; Tests: T1 T2 T3 151 152 always_ff @(posedge clk_i or negedge rst_ni) begin 153 1/1 if (!rst_ni) begin Tests: T1 T2 T3 154 1/1 outstanding_txn <= '0; Tests: T1 T2 T3 155 1/1 end else if (a_ack && !d_ack) begin Tests: T1 T2 T3 156 1/1 outstanding_txn <= outstanding_txn + 1'b1; Tests: T1 T2 T3 157 1/1 end else if (d_ack && !a_ack) begin Tests: T1 T2 T3 158 1/1 outstanding_txn <= outstanding_txn - 1'b1; Tests: T1 T2 T3 159 end MISSING_ELSE 160 end 161 162 logic block_cmd; 163 always_comb begin 164 1/1 block_cmd = '0; Tests: T1 T2 T3 165 1/1 state_d = state_q; Tests: T1 T2 T3 166 1/1 err_en = Off; Tests: T1 T2 T3 167 1/1 err_o = '0; Tests: T1 T2 T3 168 1/1 flush_ack_o = '0; Tests: T1 T2 T3 169 1/1 resp_pending_o = 1'b0; Tests: T1 T2 T3 170 171 1/1 unique case (state_q) Tests: T1 T2 T3 172 StActive: begin 173 1/1 if (lc_tx_test_false_loose(lc_en_i) || flush_req_i) begin Tests: T1 T2 T3 174 1/1 state_d = StOutstanding; Tests: T7 T8 T9 175 end MISSING_ELSE 176 1/1 if (outstanding_txn != '0) begin Tests: T1 T2 T3 177 1/1 resp_pending_o = 1'b1; Tests: T1 T2 T3 178 end MISSING_ELSE 179 end 180 181 StOutstanding: begin 182 1/1 block_cmd = 1'b1; Tests: T7 T8 T9 183 1/1 if (outstanding_txn == '0) begin Tests: T7 T8 T9 184 1/1 state_d = lc_tx_test_false_loose(lc_en_i) ? StError : StFlush; Tests: T7 T8 T9 185 end else begin 186 1/1 resp_pending_o = 1'b1; Tests: T8 T9 T10 187 end 188 end 189 190 StFlush: begin 191 1/1 block_cmd = 1'b1; Tests: T10 T11 192 1/1 flush_ack_o = 1'b1; Tests: T10 T11 193 1/1 if (lc_tx_test_false_loose(lc_en_i)) begin Tests: T10 T11 194 1/1 state_d = StError; Tests: T10 T11 195 1/1 end else if (!flush_req_i) begin Tests: T10 T11 196 1/1 state_d = StActive; Tests: T10 T11 197 end ==> MISSING_ELSE 198 end 199 200 StError: begin 201 1/1 err_en = On; Tests: T1 T2 T3 202 1/1 if (lc_tx_test_true_strict(lc_en_i)) begin Tests: T1 T2 T3 203 1/1 state_d = StErrorOutstanding; Tests: T1 T2 T3 204 end MISSING_ELSE 205 end 206 207 StErrorOutstanding: begin 208 1/1 err_en = On; Tests: T1 T2 T3 209 1/1 block_cmd = 1'b1; Tests: T1 T2 T3 210 1/1 if (outstanding_txn == '0) begin Tests: T1 T2 T3 211 1/1 state_d = StActive; Tests: T1 T2 T3 212 end MISSING_ELSE 213 end 214 215 default: begin 216 err_o = 1'b1; 217 err_en = On; 218 end 219 220 endcase // unique case (state_q) 221 end 222 223 224 // At the host side, we interpose the ready / valid signals so that we can return a bus error 225 // in case the lc signal is not set to ON. Note that this logic does not have to be duplicated 226 // since erroring back is considered a convenience feature so that the bus does not lock up. 227 tl_h2d_t tl_h2d_error; 228 tl_d2h_t tl_d2h_error; 229 always_comb begin 230 1/1 tl_h2d_int[0] = tl_h2d_i; Tests: T1 T2 T3 231 1/1 tl_d2h_o = tl_d2h_int[0]; Tests: T1 T2 T3 232 1/1 tl_h2d_error = '0; Tests: T1 T2 T3 233 234 1/1 if (lc_tx_test_true_loose(err_en)) begin Tests: T1 T2 T3 235 1/1 tl_h2d_error = tl_h2d_i; Tests: T1 T2 T3 236 1/1 tl_d2h_o = tl_d2h_error; Tests: T1 T2 T3 237 end MISSING_ELSE 238 239 1/1 if (block_cmd) begin Tests: T1 T2 T3 240 1/1 tl_d2h_o.a_ready = 1'b0; Tests: T1 T2 T3 241 1/1 tl_h2d_int[0].a_valid = 1'b0; Tests: T1 T2 T3 242 1/1 tl_h2d_error.a_valid = 1'b0; Tests: T1 T2 T3 243 end MISSING_ELSE
Cond Coverage for Module : tlul_lc_gate
| Total | Covered | Percent | |
|---|---|---|---|
| Conditions | 18 | 18 | 100.00 |
| Logical | 18 | 18 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 |
LINE 149
EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
--------1------- --------2-------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T12 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 150
EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
--------1------- --------2-------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T12,T13,T14 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION (a_ack && ((!d_ack)))
--1-- -----2----
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T15,T10 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (d_ack && ((!a_ack)))
--1-- -----2----
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T15,T10 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 176
EXPRESSION (outstanding_txn != '0)
-----------1-----------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
EXPRESSION (outstanding_txn == '0)
-----------1-----------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T8,T9,T10 |
| 1 | Covered | T7,T8,T9 |
LINE 210
EXPRESSION (outstanding_txn == '0)
-----------1-----------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T10,T11 |
| 1 | Covered | T1,T2,T3 |
FSM Coverage for Module : tlul_lc_gate
| Total | Covered | Percent | ||
|---|---|---|---|---|
| States | 5 | 4 | 80.00 | (Not included in score) |
| Transitions | 7 | 4 | 57.14 | |
| Sequences | 0 | 0 |
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| StActive | 196 | Covered | T1,T2,T3 |
| StError | 184 | Covered | T1,T2,T3 |
| StErrorOutstanding | 203 | Covered | T1,T2,T3 |
| StFlush | 184 | Not Covered | |
| StOutstanding | 174 | Covered | T7,T8,T9 |
| transitions | Line No. | Covered | Tests |
| StActive->StOutstanding | 174 | Covered | T7,T8,T9 |
| StError->StErrorOutstanding | 203 | Covered | T1,T2,T3 |
| StErrorOutstanding->StActive | 211 | Covered | T1,T2,T3 |
| StFlush->StActive | 196 | Not Covered | |
| StFlush->StError | 194 | Not Covered | |
| StOutstanding->StError | 184 | Covered | T7,T8,T9 |
| StOutstanding->StFlush | 184 | Not Covered |
Branch Coverage for Module : tlul_lc_gate
| Line No. | Total | Covered | Percent | |
|---|---|---|---|---|
| Branches | 24 | 23 | 95.83 | |
| IF | 144 | 2 | 2 | 100.00 |
| IF | 153 | 4 | 4 | 100.00 |
| CASE | 171 | 14 | 13 | 92.86 |
| IF | 234 | 2 | 2 | 100.00 |
| IF | 239 | 2 | 2 | 100.00 |
144 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StError) -1- ==> ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| 1 | Covered | T1,T2,T3 |
| 0 | Covered | T1,T2,T3 |
153 if (!rst_ni) begin -1- 154 outstanding_txn <= '0; ==> 155 end else if (a_ack && !d_ack) begin -2- 156 outstanding_txn <= outstanding_txn + 1'b1; ==> 157 end else if (d_ack && !a_ack) begin -3- 158 outstanding_txn <= outstanding_txn - 1'b1; ==> 159 end MISSING_ELSE ==>
Branches:
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 1 | - | - | Covered | T1,T2,T3 |
| 0 | 1 | - | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | Covered | T1,T2,T3 |
171 unique case (state_q) -1- 172 StActive: begin 173 if (lc_tx_test_false_loose(lc_en_i) || flush_req_i) begin -2- 174 state_d = StOutstanding; ==> 175 end MISSING_ELSE ==> 176 if (outstanding_txn != '0) begin -3- 177 resp_pending_o = 1'b1; ==> 178 end MISSING_ELSE ==> 179 end 180 181 StOutstanding: begin 182 block_cmd = 1'b1; 183 if (outstanding_txn == '0) begin -4- 184 state_d = lc_tx_test_false_loose(lc_en_i) ? StError : StFlush; ==> 185 end else begin 186 resp_pending_o = 1'b1; ==> 187 end 188 end 189 190 StFlush: begin 191 block_cmd = 1'b1; 192 flush_ack_o = 1'b1; 193 if (lc_tx_test_false_loose(lc_en_i)) begin -5- 194 state_d = StError; ==> 195 end else if (!flush_req_i) begin -6- 196 state_d = StActive; ==> 197 end MISSING_ELSE ==> 198 end 199 200 StError: begin 201 err_en = On; 202 if (lc_tx_test_true_strict(lc_en_i)) begin -7- 203 state_d = StErrorOutstanding; ==> 204 end MISSING_ELSE ==> 205 end 206 207 StErrorOutstanding: begin 208 err_en = On; 209 block_cmd = 1'b1; 210 if (outstanding_txn == '0) begin -8- 211 state_d = StActive; ==> 212 end MISSING_ELSE ==> 213 end 214 215 default: begin 216 err_o = 1'b1; ==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
|---|---|---|---|---|---|---|---|---|---|
| StActive | 1 | - | - | - | - | - | - | Covered | T7,T8,T9 |
| StActive | 0 | - | - | - | - | - | - | Covered | T1,T2,T3 |
| StActive | - | 1 | - | - | - | - | - | Covered | T1,T2,T3 |
| StActive | - | 0 | - | - | - | - | - | Covered | T1,T2,T3 |
| StOutstanding | - | - | 1 | - | - | - | - | Covered | T7,T8,T9 |
| StOutstanding | - | - | 0 | - | - | - | - | Covered | T8,T9,T10 |
| StFlush | - | - | - | 1 | - | - | - | Covered | T10,T11 |
| StFlush | - | - | - | 0 | 1 | - | - | Covered | T10,T11 |
| StFlush | - | - | - | 0 | 0 | - | - | Not Covered | |
| StError | - | - | - | - | - | 1 | - | Covered | T1,T2,T3 |
| StError | - | - | - | - | - | 0 | - | Covered | T7,T8,T9 |
| StErrorOutstanding | - | - | - | - | - | - | 1 | Covered | T1,T2,T3 |
| StErrorOutstanding | - | - | - | - | - | - | 0 | Covered | T10,T11 |
| default | - | - | - | - | - | - | - | Covered | T10,T11,T16 |
234 if (lc_tx_test_true_loose(err_en)) begin -1- 235 tl_h2d_error = tl_h2d_i; ==> 236 tl_d2h_o = tl_d2h_error; 237 end MISSING_ELSE ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| 1 | Covered | T1,T2,T3 |
| 0 | Covered | T1,T2,T3 |
239 if (block_cmd) begin -1- 240 tl_d2h_o.a_ready = 1'b0; ==> 241 tl_h2d_int[0].a_valid = 1'b0; 242 tl_h2d_error.a_valid = 1'b0; 243 end MISSING_ELSE ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| 1 | Covered | T1,T2,T3 |
| 0 | Covered | T1,T2,T3 |
Assert Coverage for Module : tlul_lc_gate
| Total | Attempted | Percent | Succeeded/Matched | Percent | |
|---|---|---|---|---|---|
| Assertions | 2 | 2 | 100.00 | 1 | 50.00 |
| Cover properties | 0 | 0 | 0 | ||
| Cover sequences | 0 | 0 | 0 | ||
| Total | 2 | 2 | 100.00 | 1 | 50.00 |
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
| OutStandingOvfl_A | 776511532 | 0 | 0 | 0 |
| u_state_regs_A | 776511532 | 774831282 | 0 | 0 |
OutStandingOvfl_A
| Name | Attempts | Real Successes | Failures | Incomplete |
|---|---|---|---|---|
| Total | 776511532 | 0 | 0 | 0 |
u_state_regs_A
| Name | Attempts | Real Successes | Failures | Incomplete |
|---|---|---|---|---|
| Total | 776511532 | 774831282 | 0 | 0 |
| T1 | 7812 | 7706 | 0 | 0 |
| T2 | 21696 | 21556 | 0 | 0 |
| T3 | 2448 | 2334 | 0 | 0 |
| T4 | 1780 | 1680 | 0 | 0 |
| T7 | 1944 | 1844 | 0 | 0 |
| T12 | 4004 | 3888 | 0 | 0 |
| T17 | 3088 | 2978 | 0 | 0 |
| T18 | 3900 | 3732 | 0 | 0 |
| T19 | 4606 | 4422 | 0 | 0 |
| T20 | 2946 | 2676 | 0 | 0 |
Line Coverage for Instance : tb.dut.u_prog_tl_gate
Cond Coverage for Instance : tb.dut.u_prog_tl_gate
FSM Coverage for Instance : tb.dut.u_prog_tl_gate
State, Transition and Sequence Details for FSM :: state_q
Branch Coverage for Instance : tb.dut.u_prog_tl_gate
Branches:
Branches:
Branches:
Branches:
Branches:
Assert Coverage for Instance : tb.dut.u_prog_tl_gate
Assertion Details
OutStandingOvfl_A
u_state_regs_A
| Line No. | Total | Covered | Percent | |
|---|---|---|---|---|
| TOTAL | 51 | 51 | 100.00 | |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| ALWAYS | 144 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| ALWAYS | 153 | 6 | 6 | 100.00 |
| ALWAYS | 164 | 28 | 28 | 100.00 |
| ALWAYS | 230 | 10 | 10 | 100.00 |
83 // Assign signals on the device side. 84 1/1 assign tl_h2d_o = tl_h2d_int[NumGatesPerDirection]; Tests: T1 T2 T3 85 1/1 assign tl_d2h_int[NumGatesPerDirection] = tl_d2h_i; Tests: T1 T2 T3 86 87 /////////////////////////// 88 // Host Side Interposing // 89 /////////////////////////// 90 91 // Encoding generated with: 92 // $ ./util/design/sparse-fsm-encode.py -d 5 -m 4 -n 8 \ 93 // -s 3379253306 --language=sv 94 // 95 // Hamming distance histogram: 96 // 97 // 0: -- 98 // 1: -- 99 // 2: -- 100 // 3: -- 101 // 4: -- 102 // 5: |||||||||||||||||||| (66.67%) 103 // 6: |||||||||| (33.33%) 104 // 7: -- 105 // 8: -- 106 // 107 // Minimum Hamming distance: 5 108 // Maximum Hamming distance: 6 109 // Minimum Hamming weight: 3 110 // Maximum Hamming weight: 5 111 // 112 // Encoding generated with: 113 // $ ./util/design/sparse-fsm-encode.py -d 5 -m 5 -n 9 \ 114 // -s 686407169 --language=sv 115 // 116 // Hamming distance histogram: 117 // 118 // 0: -- 119 // 1: -- 120 // 2: -- 121 // 3: -- 122 // 4: -- 123 // 5: |||||||||||||||||||| (60.00%) 124 // 6: ||||||||||||| (40.00%) 125 // 7: -- 126 // 8: -- 127 // 9: -- 128 // 129 // Minimum Hamming distance: 5 130 // Maximum Hamming distance: 6 131 // Minimum Hamming weight: 3 132 // Maximum Hamming weight: 6 133 // 134 localparam int StateWidth = 9; 135 typedef enum logic [StateWidth-1:0] { 136 StActive = 9'b100100001, 137 StOutstanding = 9'b011100111, 138 StFlush = 9'b001001100, 139 StError = 9'b010111010, 140 StErrorOutstanding = 9'b100010110 141 } state_e; 142 143 state_e state_d, state_q;
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StError): 144.1 `ifdef SIMULATION 144.2 prim_sparse_fsm_flop #( 144.3 .StateEnumT(state_e), 144.4 .Width($bits(state_e)), 144.5 .ResetValue($bits(state_e)'(StError)), 144.6 .EnableAlertTriggerSVA(1), 144.7 .CustomForceName("state_q") 144.8 ) u_state_regs ( 144.9 .clk_i ( clk_i ), 144.10 .rst_ni ( rst_ni ), 144.11 .state_i ( state_d ), 144.12 .state_o ( ) 144.13 ); 144.14 always_ff @(posedge clk_i or negedge rst_ni) begin 144.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3 144.16 1/1 state_q <= StError; Tests: T1 T2 T3 144.17 end else begin 144.18 1/1 state_q <= state_d; Tests: T1 T2 T3 144.19 end 144.20 end 144.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 144.22 else begin 144.23 `ifdef UVM 144.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 144.25 "../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv", 144, "", 1); 144.26 `else 144.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 144.28 `PRIM_STRINGIFY(u_state_regs_A)); 144.29 `endif 144.30 end 144.31 `else 144.32 prim_sparse_fsm_flop #( 144.33 .StateEnumT(state_e), 144.34 .Width($bits(state_e)), 144.35 .ResetValue($bits(state_e)'(StError)), 144.36 .EnableAlertTriggerSVA(1) 144.37 ) u_state_regs ( 144.38 .clk_i ( `PRIM_FLOP_CLK ), 144.39 .rst_ni ( `PRIM_FLOP_RST ), 144.40 .state_i ( state_d ), 144.41 .state_o ( state_q ) 144.42 ); 144.43 `endif145 146 logic [1:0] outstanding_txn; 147 logic a_ack; 148 logic d_ack; 149 1/1 assign a_ack = tl_h2d_i.a_valid & tl_d2h_o.a_ready; Tests: T1 T2 T3 150 1/1 assign d_ack = tl_h2d_i.d_ready & tl_d2h_o.d_valid; Tests: T1 T2 T3 151 152 always_ff @(posedge clk_i or negedge rst_ni) begin 153 1/1 if (!rst_ni) begin Tests: T1 T2 T3 154 1/1 outstanding_txn <= '0; Tests: T1 T2 T3 155 1/1 end else if (a_ack && !d_ack) begin Tests: T1 T2 T3 156 1/1 outstanding_txn <= outstanding_txn + 1'b1; Tests: T1 T12 T20 157 1/1 end else if (d_ack && !a_ack) begin Tests: T1 T2 T3 158 1/1 outstanding_txn <= outstanding_txn - 1'b1; Tests: T1 T12 T20 159 end MISSING_ELSE 160 end 161 162 logic block_cmd; 163 always_comb begin 164 1/1 block_cmd = '0; Tests: T1 T2 T3 165 1/1 state_d = state_q; Tests: T1 T2 T3 166 1/1 err_en = Off; Tests: T1 T2 T3 167 1/1 err_o = '0; Tests: T1 T2 T3 168 1/1 flush_ack_o = '0; Tests: T1 T2 T3 169 1/1 resp_pending_o = 1'b0; Tests: T1 T2 T3 170 171 1/1 unique case (state_q) Tests: T1 T2 T3 172 StActive: begin 173 1/1 if (lc_tx_test_false_loose(lc_en_i) || flush_req_i) begin Tests: T1 T2 T3 174 1/1 state_d = StOutstanding; Tests: T7 T8 T9 175 end MISSING_ELSE 176 1/1 if (outstanding_txn != '0) begin Tests: T1 T2 T3 177 1/1 resp_pending_o = 1'b1; Tests: T1 T12 T20 178 end MISSING_ELSE 179 end 180 181 StOutstanding: begin 182 1/1 block_cmd = 1'b1; Tests: T7 T8 T9 183 1/1 if (outstanding_txn == '0) begin Tests: T7 T8 T9 184 1/1 state_d = lc_tx_test_false_loose(lc_en_i) ? StError : StFlush; Tests: T7 T8 T9 185 end else begin 186 1/1 resp_pending_o = 1'b1; Tests: T8 T10 T21 187 end 188 end 189 190 StFlush: begin 191 1/1 block_cmd = 1'b1; Tests: T10 T11 192 1/1 flush_ack_o = 1'b1; Tests: T10 T11 193 1/1 if (lc_tx_test_false_loose(lc_en_i)) begin Tests: T10 T11 194 1/1 state_d = StError; Tests: T10 T11 195 1/1 end else if (!flush_req_i) begin Tests: T10 T11 196 1/1 state_d = StActive; Tests: T10 T11 197 end ==> MISSING_ELSE 198 end 199 200 StError: begin 201 1/1 err_en = On; Tests: T1 T2 T3 202 1/1 if (lc_tx_test_true_strict(lc_en_i)) begin Tests: T1 T2 T3 203 1/1 state_d = StErrorOutstanding; Tests: T1 T2 T3 204 end MISSING_ELSE 205 end 206 207 StErrorOutstanding: begin 208 1/1 err_en = On; Tests: T1 T2 T3 209 1/1 block_cmd = 1'b1; Tests: T1 T2 T3 210 1/1 if (outstanding_txn == '0) begin Tests: T1 T2 T3 211 1/1 state_d = StActive; Tests: T1 T2 T3 212 end MISSING_ELSE 213 end 214 215 default: begin 216 err_o = 1'b1; 217 err_en = On; 218 end 219 220 endcase // unique case (state_q) 221 end 222 223 224 // At the host side, we interpose the ready / valid signals so that we can return a bus error 225 // in case the lc signal is not set to ON. Note that this logic does not have to be duplicated 226 // since erroring back is considered a convenience feature so that the bus does not lock up. 227 tl_h2d_t tl_h2d_error; 228 tl_d2h_t tl_d2h_error; 229 always_comb begin 230 1/1 tl_h2d_int[0] = tl_h2d_i; Tests: T1 T2 T3 231 1/1 tl_d2h_o = tl_d2h_int[0]; Tests: T1 T2 T3 232 1/1 tl_h2d_error = '0; Tests: T1 T2 T3 233 234 1/1 if (lc_tx_test_true_loose(err_en)) begin Tests: T1 T2 T3 235 1/1 tl_h2d_error = tl_h2d_i; Tests: T1 T2 T3 236 1/1 tl_d2h_o = tl_d2h_error; Tests: T1 T2 T3 237 end MISSING_ELSE 238 239 1/1 if (block_cmd) begin Tests: T1 T2 T3 240 1/1 tl_d2h_o.a_ready = 1'b0; Tests: T1 T2 T3 241 1/1 tl_h2d_int[0].a_valid = 1'b0; Tests: T1 T2 T3 242 1/1 tl_h2d_error.a_valid = 1'b0; Tests: T1 T2 T3 243 end MISSING_ELSE
Cond Coverage for Instance : tb.dut.u_prog_tl_gate
| Total | Covered | Percent | |
|---|---|---|---|
| Conditions | 18 | 16 | 88.89 |
| Logical | 18 | 16 | 88.89 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 |
LINE 149
EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
--------1------- --------2-------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T12,T20 |
| 1 | 1 | Covered | T1,T12,T20 |
LINE 150
EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
--------1------- --------2-------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T12,T13,T14 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T12,T20 |
LINE 155
EXPRESSION (a_ack && ((!d_ack)))
--1-- -----2----
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T12,T20 |
LINE 157
EXPRESSION (d_ack && ((!a_ack)))
--1-- -----2----
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T12,T20 |
LINE 176
EXPRESSION (outstanding_txn != '0)
-----------1-----------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T12,T20 |
LINE 183
EXPRESSION (outstanding_txn == '0)
-----------1-----------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T8,T10,T21 |
| 1 | Covered | T7,T8,T9 |
LINE 210
EXPRESSION (outstanding_txn == '0)
-----------1-----------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T10,T11 |
| 1 | Covered | T1,T2,T3 |
FSM Coverage for Instance : tb.dut.u_prog_tl_gate
| Total | Covered | Percent | ||
|---|---|---|---|---|
| States | 5 | 4 | 80.00 | (Not included in score) |
| Transitions | 7 | 4 | 57.14 | |
| Sequences | 0 | 0 |
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| StActive | 196 | Covered | T1,T2,T3 |
| StError | 184 | Covered | T1,T2,T3 |
| StErrorOutstanding | 203 | Covered | T1,T2,T3 |
| StFlush | 184 | Not Covered | |
| StOutstanding | 174 | Covered | T7,T8,T9 |
| transitions | Line No. | Covered | Tests |
| StActive->StOutstanding | 174 | Covered | T7,T8,T9 |
| StError->StErrorOutstanding | 203 | Covered | T1,T2,T3 |
| StErrorOutstanding->StActive | 211 | Covered | T1,T2,T3 |
| StFlush->StActive | 196 | Not Covered | |
| StFlush->StError | 194 | Not Covered | |
| StOutstanding->StError | 184 | Covered | T7,T8,T9 |
| StOutstanding->StFlush | 184 | Not Covered |
Branch Coverage for Instance : tb.dut.u_prog_tl_gate
| Line No. | Total | Covered | Percent | |
|---|---|---|---|---|
| Branches | 24 | 23 | 95.83 | |
| IF | 144 | 2 | 2 | 100.00 |
| IF | 153 | 4 | 4 | 100.00 |
| CASE | 171 | 14 | 13 | 92.86 |
| IF | 234 | 2 | 2 | 100.00 |
| IF | 239 | 2 | 2 | 100.00 |
144 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StError) -1- ==> ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| 1 | Covered | T1,T2,T3 |
| 0 | Covered | T1,T2,T3 |
153 if (!rst_ni) begin -1- 154 outstanding_txn <= '0; ==> 155 end else if (a_ack && !d_ack) begin -2- 156 outstanding_txn <= outstanding_txn + 1'b1; ==> 157 end else if (d_ack && !a_ack) begin -3- 158 outstanding_txn <= outstanding_txn - 1'b1; ==> 159 end MISSING_ELSE ==>
Branches:
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 1 | - | - | Covered | T1,T2,T3 |
| 0 | 1 | - | Covered | T1,T12,T20 |
| 0 | 0 | 1 | Covered | T1,T12,T20 |
| 0 | 0 | 0 | Covered | T1,T2,T3 |
171 unique case (state_q) -1- 172 StActive: begin 173 if (lc_tx_test_false_loose(lc_en_i) || flush_req_i) begin -2- 174 state_d = StOutstanding; ==> 175 end MISSING_ELSE ==> 176 if (outstanding_txn != '0) begin -3- 177 resp_pending_o = 1'b1; ==> 178 end MISSING_ELSE ==> 179 end 180 181 StOutstanding: begin 182 block_cmd = 1'b1; 183 if (outstanding_txn == '0) begin -4- 184 state_d = lc_tx_test_false_loose(lc_en_i) ? StError : StFlush; ==> 185 end else begin 186 resp_pending_o = 1'b1; ==> 187 end 188 end 189 190 StFlush: begin 191 block_cmd = 1'b1; 192 flush_ack_o = 1'b1; 193 if (lc_tx_test_false_loose(lc_en_i)) begin -5- 194 state_d = StError; ==> 195 end else if (!flush_req_i) begin -6- 196 state_d = StActive; ==> 197 end MISSING_ELSE ==> 198 end 199 200 StError: begin 201 err_en = On; 202 if (lc_tx_test_true_strict(lc_en_i)) begin -7- 203 state_d = StErrorOutstanding; ==> 204 end MISSING_ELSE ==> 205 end 206 207 StErrorOutstanding: begin 208 err_en = On; 209 block_cmd = 1'b1; 210 if (outstanding_txn == '0) begin -8- 211 state_d = StActive; ==> 212 end MISSING_ELSE ==> 213 end 214 215 default: begin 216 err_o = 1'b1; ==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
|---|---|---|---|---|---|---|---|---|---|
| StActive | 1 | - | - | - | - | - | - | Covered | T7,T8,T9 |
| StActive | 0 | - | - | - | - | - | - | Covered | T1,T2,T3 |
| StActive | - | 1 | - | - | - | - | - | Covered | T1,T12,T20 |
| StActive | - | 0 | - | - | - | - | - | Covered | T1,T2,T3 |
| StOutstanding | - | - | 1 | - | - | - | - | Covered | T7,T8,T9 |
| StOutstanding | - | - | 0 | - | - | - | - | Covered | T8,T10,T21 |
| StFlush | - | - | - | 1 | - | - | - | Covered | T10,T11 |
| StFlush | - | - | - | 0 | 1 | - | - | Covered | T10,T11 |
| StFlush | - | - | - | 0 | 0 | - | - | Not Covered | |
| StError | - | - | - | - | - | 1 | - | Covered | T1,T2,T3 |
| StError | - | - | - | - | - | 0 | - | Covered | T7,T8,T9 |
| StErrorOutstanding | - | - | - | - | - | - | 1 | Covered | T1,T2,T3 |
| StErrorOutstanding | - | - | - | - | - | - | 0 | Covered | T10,T11 |
| default | - | - | - | - | - | - | - | Covered | T10,T11,T16 |
234 if (lc_tx_test_true_loose(err_en)) begin -1- 235 tl_h2d_error = tl_h2d_i; ==> 236 tl_d2h_o = tl_d2h_error; 237 end MISSING_ELSE ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| 1 | Covered | T1,T2,T3 |
| 0 | Covered | T1,T2,T3 |
239 if (block_cmd) begin -1- 240 tl_d2h_o.a_ready = 1'b0; ==> 241 tl_h2d_int[0].a_valid = 1'b0; 242 tl_h2d_error.a_valid = 1'b0; 243 end MISSING_ELSE ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| 1 | Covered | T1,T2,T3 |
| 0 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prog_tl_gate
| Total | Attempted | Percent | Succeeded/Matched | Percent | |
|---|---|---|---|---|---|
| Assertions | 2 | 2 | 100.00 | 1 | 50.00 |
| Cover properties | 0 | 0 | 0 | ||
| Cover sequences | 0 | 0 | 0 | ||
| Total | 2 | 2 | 100.00 | 1 | 50.00 |
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
| OutStandingOvfl_A | 388255766 | 0 | 0 | 0 |
| u_state_regs_A | 388255766 | 387415641 | 0 | 0 |
OutStandingOvfl_A
| Name | Attempts | Real Successes | Failures | Incomplete |
|---|---|---|---|---|
| Total | 388255766 | 0 | 0 | 0 |
u_state_regs_A
| Name | Attempts | Real Successes | Failures | Incomplete |
|---|---|---|---|---|
| Total | 388255766 | 387415641 | 0 | 0 |
| T1 | 3906 | 3853 | 0 | 0 |
| T2 | 10848 | 10778 | 0 | 0 |
| T3 | 1224 | 1167 | 0 | 0 |
| T4 | 890 | 840 | 0 | 0 |
| T7 | 972 | 922 | 0 | 0 |
| T12 | 2002 | 1944 | 0 | 0 |
| T17 | 1544 | 1489 | 0 | 0 |
| T18 | 1950 | 1866 | 0 | 0 |
| T19 | 2303 | 2211 | 0 | 0 |
| T20 | 1473 | 1338 | 0 | 0 |
Line Coverage for Instance : tb.dut.u_tl_gate
Cond Coverage for Instance : tb.dut.u_tl_gate
FSM Coverage for Instance : tb.dut.u_tl_gate
State, Transition and Sequence Details for FSM :: state_q
Branch Coverage for Instance : tb.dut.u_tl_gate
Branches:
Branches:
Branches:
Branches:
Branches:
Assert Coverage for Instance : tb.dut.u_tl_gate
Assertion Details
OutStandingOvfl_A
u_state_regs_A
| Line No. | Total | Covered | Percent | |
|---|---|---|---|---|
| TOTAL | 51 | 51 | 100.00 | |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| ALWAYS | 144 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| ALWAYS | 153 | 6 | 6 | 100.00 |
| ALWAYS | 164 | 28 | 28 | 100.00 |
| ALWAYS | 230 | 10 | 10 | 100.00 |
83 // Assign signals on the device side. 84 1/1 assign tl_h2d_o = tl_h2d_int[NumGatesPerDirection]; Tests: T1 T2 T3 85 1/1 assign tl_d2h_int[NumGatesPerDirection] = tl_d2h_i; Tests: T1 T2 T3 86 87 /////////////////////////// 88 // Host Side Interposing // 89 /////////////////////////// 90 91 // Encoding generated with: 92 // $ ./util/design/sparse-fsm-encode.py -d 5 -m 4 -n 8 \ 93 // -s 3379253306 --language=sv 94 // 95 // Hamming distance histogram: 96 // 97 // 0: -- 98 // 1: -- 99 // 2: -- 100 // 3: -- 101 // 4: -- 102 // 5: |||||||||||||||||||| (66.67%) 103 // 6: |||||||||| (33.33%) 104 // 7: -- 105 // 8: -- 106 // 107 // Minimum Hamming distance: 5 108 // Maximum Hamming distance: 6 109 // Minimum Hamming weight: 3 110 // Maximum Hamming weight: 5 111 // 112 // Encoding generated with: 113 // $ ./util/design/sparse-fsm-encode.py -d 5 -m 5 -n 9 \ 114 // -s 686407169 --language=sv 115 // 116 // Hamming distance histogram: 117 // 118 // 0: -- 119 // 1: -- 120 // 2: -- 121 // 3: -- 122 // 4: -- 123 // 5: |||||||||||||||||||| (60.00%) 124 // 6: ||||||||||||| (40.00%) 125 // 7: -- 126 // 8: -- 127 // 9: -- 128 // 129 // Minimum Hamming distance: 5 130 // Maximum Hamming distance: 6 131 // Minimum Hamming weight: 3 132 // Maximum Hamming weight: 6 133 // 134 localparam int StateWidth = 9; 135 typedef enum logic [StateWidth-1:0] { 136 StActive = 9'b100100001, 137 StOutstanding = 9'b011100111, 138 StFlush = 9'b001001100, 139 StError = 9'b010111010, 140 StErrorOutstanding = 9'b100010110 141 } state_e; 142 143 state_e state_d, state_q;
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StError): 144.1 `ifdef SIMULATION 144.2 prim_sparse_fsm_flop #( 144.3 .StateEnumT(state_e), 144.4 .Width($bits(state_e)), 144.5 .ResetValue($bits(state_e)'(StError)), 144.6 .EnableAlertTriggerSVA(1), 144.7 .CustomForceName("state_q") 144.8 ) u_state_regs ( 144.9 .clk_i ( clk_i ), 144.10 .rst_ni ( rst_ni ), 144.11 .state_i ( state_d ), 144.12 .state_o ( ) 144.13 ); 144.14 always_ff @(posedge clk_i or negedge rst_ni) begin 144.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3 144.16 1/1 state_q <= StError; Tests: T1 T2 T3 144.17 end else begin 144.18 1/1 state_q <= state_d; Tests: T1 T2 T3 144.19 end 144.20 end 144.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 144.22 else begin 144.23 `ifdef UVM 144.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 144.25 "../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv", 144, "", 1); 144.26 `else 144.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 144.28 `PRIM_STRINGIFY(u_state_regs_A)); 144.29 `endif 144.30 end 144.31 `else 144.32 prim_sparse_fsm_flop #( 144.33 .StateEnumT(state_e), 144.34 .Width($bits(state_e)), 144.35 .ResetValue($bits(state_e)'(StError)), 144.36 .EnableAlertTriggerSVA(1) 144.37 ) u_state_regs ( 144.38 .clk_i ( `PRIM_FLOP_CLK ), 144.39 .rst_ni ( `PRIM_FLOP_RST ), 144.40 .state_i ( state_d ), 144.41 .state_o ( state_q ) 144.42 ); 144.43 `endif145 146 logic [1:0] outstanding_txn; 147 logic a_ack; 148 logic d_ack; 149 1/1 assign a_ack = tl_h2d_i.a_valid & tl_d2h_o.a_ready; Tests: T1 T2 T3 150 1/1 assign d_ack = tl_h2d_i.d_ready & tl_d2h_o.d_valid; Tests: T1 T2 T3 151 152 always_ff @(posedge clk_i or negedge rst_ni) begin 153 1/1 if (!rst_ni) begin Tests: T1 T2 T3 154 1/1 outstanding_txn <= '0; Tests: T1 T2 T3 155 1/1 end else if (a_ack && !d_ack) begin Tests: T1 T2 T3 156 1/1 outstanding_txn <= outstanding_txn + 1'b1; Tests: T2 T3 T20 157 1/1 end else if (d_ack && !a_ack) begin Tests: T1 T2 T3 158 1/1 outstanding_txn <= outstanding_txn - 1'b1; Tests: T2 T3 T20 159 end MISSING_ELSE 160 end 161 162 logic block_cmd; 163 always_comb begin 164 1/1 block_cmd = '0; Tests: T1 T2 T3 165 1/1 state_d = state_q; Tests: T1 T2 T3 166 1/1 err_en = Off; Tests: T1 T2 T3 167 1/1 err_o = '0; Tests: T1 T2 T3 168 1/1 flush_ack_o = '0; Tests: T1 T2 T3 169 1/1 resp_pending_o = 1'b0; Tests: T1 T2 T3 170 171 1/1 unique case (state_q) Tests: T1 T2 T3 172 StActive: begin 173 1/1 if (lc_tx_test_false_loose(lc_en_i) || flush_req_i) begin Tests: T1 T2 T3 174 1/1 state_d = StOutstanding; Tests: T7 T8 T9 175 end MISSING_ELSE 176 1/1 if (outstanding_txn != '0) begin Tests: T1 T2 T3 177 1/1 resp_pending_o = 1'b1; Tests: T2 T3 T20 178 end MISSING_ELSE 179 end 180 181 StOutstanding: begin 182 1/1 block_cmd = 1'b1; Tests: T7 T8 T9 183 1/1 if (outstanding_txn == '0) begin Tests: T7 T8 T9 184 1/1 state_d = lc_tx_test_false_loose(lc_en_i) ? StError : StFlush; Tests: T7 T8 T9 185 end else begin 186 1/1 resp_pending_o = 1'b1; Tests: T9 T10 T22 187 end 188 end 189 190 StFlush: begin 191 1/1 block_cmd = 1'b1; Tests: T10 T11 192 1/1 flush_ack_o = 1'b1; Tests: T10 T11 193 1/1 if (lc_tx_test_false_loose(lc_en_i)) begin Tests: T10 T11 194 1/1 state_d = StError; Tests: T10 T11 195 1/1 end else if (!flush_req_i) begin Tests: T10 T11 196 1/1 state_d = StActive; Tests: T10 T11 197 end ==> MISSING_ELSE 198 end 199 200 StError: begin 201 1/1 err_en = On; Tests: T1 T2 T3 202 1/1 if (lc_tx_test_true_strict(lc_en_i)) begin Tests: T1 T2 T3 203 1/1 state_d = StErrorOutstanding; Tests: T1 T2 T3 204 end MISSING_ELSE 205 end 206 207 StErrorOutstanding: begin 208 1/1 err_en = On; Tests: T1 T2 T3 209 1/1 block_cmd = 1'b1; Tests: T1 T2 T3 210 1/1 if (outstanding_txn == '0) begin Tests: T1 T2 T3 211 1/1 state_d = StActive; Tests: T1 T2 T3 212 end MISSING_ELSE 213 end 214 215 default: begin 216 err_o = 1'b1; 217 err_en = On; 218 end 219 220 endcase // unique case (state_q) 221 end 222 223 224 // At the host side, we interpose the ready / valid signals so that we can return a bus error 225 // in case the lc signal is not set to ON. Note that this logic does not have to be duplicated 226 // since erroring back is considered a convenience feature so that the bus does not lock up. 227 tl_h2d_t tl_h2d_error; 228 tl_d2h_t tl_d2h_error; 229 always_comb begin 230 1/1 tl_h2d_int[0] = tl_h2d_i; Tests: T1 T2 T3 231 1/1 tl_d2h_o = tl_d2h_int[0]; Tests: T1 T2 T3 232 1/1 tl_h2d_error = '0; Tests: T1 T2 T3 233 234 1/1 if (lc_tx_test_true_loose(err_en)) begin Tests: T1 T2 T3 235 1/1 tl_h2d_error = tl_h2d_i; Tests: T1 T2 T3 236 1/1 tl_d2h_o = tl_d2h_error; Tests: T1 T2 T3 237 end MISSING_ELSE 238 239 1/1 if (block_cmd) begin Tests: T1 T2 T3 240 1/1 tl_d2h_o.a_ready = 1'b0; Tests: T1 T2 T3 241 1/1 tl_h2d_int[0].a_valid = 1'b0; Tests: T1 T2 T3 242 1/1 tl_h2d_error.a_valid = 1'b0; Tests: T1 T2 T3 243 end MISSING_ELSE
Cond Coverage for Instance : tb.dut.u_tl_gate
| Total | Covered | Percent | |
|---|---|---|---|
| Conditions | 18 | 18 | 100.00 |
| Logical | 18 | 18 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 |
LINE 149
EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
--------1------- --------2-------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T20,T23 |
| 1 | 1 | Covered | T2,T3,T20 |
LINE 150
EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
--------1------- --------2-------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T10,T24,T25 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T3,T20 |
LINE 155
EXPRESSION (a_ack && ((!d_ack)))
--1-- -----2----
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T15,T10 |
| 1 | 1 | Covered | T2,T3,T20 |
LINE 157
EXPRESSION (d_ack && ((!a_ack)))
--1-- -----2----
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T15,T10 |
| 1 | 1 | Covered | T2,T3,T20 |
LINE 176
EXPRESSION (outstanding_txn != '0)
-----------1-----------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T20 |
LINE 183
EXPRESSION (outstanding_txn == '0)
-----------1-----------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T9,T10,T22 |
| 1 | Covered | T7,T8,T9 |
LINE 210
EXPRESSION (outstanding_txn == '0)
-----------1-----------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T10,T11 |
| 1 | Covered | T1,T2,T3 |
FSM Coverage for Instance : tb.dut.u_tl_gate
| Total | Covered | Percent | ||
|---|---|---|---|---|
| States | 5 | 4 | 80.00 | (Not included in score) |
| Transitions | 7 | 4 | 57.14 | |
| Sequences | 0 | 0 |
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| StActive | 196 | Covered | T1,T2,T3 |
| StError | 184 | Covered | T1,T2,T3 |
| StErrorOutstanding | 203 | Covered | T1,T2,T3 |
| StFlush | 184 | Not Covered | |
| StOutstanding | 174 | Covered | T7,T8,T9 |
| transitions | Line No. | Covered | Tests |
| StActive->StOutstanding | 174 | Covered | T7,T8,T9 |
| StError->StErrorOutstanding | 203 | Covered | T1,T2,T3 |
| StErrorOutstanding->StActive | 211 | Covered | T1,T2,T3 |
| StFlush->StActive | 196 | Not Covered | |
| StFlush->StError | 194 | Not Covered | |
| StOutstanding->StError | 184 | Covered | T7,T8,T9 |
| StOutstanding->StFlush | 184 | Not Covered |
Branch Coverage for Instance : tb.dut.u_tl_gate
| Line No. | Total | Covered | Percent | |
|---|---|---|---|---|
| Branches | 24 | 23 | 95.83 | |
| IF | 144 | 2 | 2 | 100.00 |
| IF | 153 | 4 | 4 | 100.00 |
| CASE | 171 | 14 | 13 | 92.86 |
| IF | 234 | 2 | 2 | 100.00 |
| IF | 239 | 2 | 2 | 100.00 |
144 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StError) -1- ==> ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| 1 | Covered | T1,T2,T3 |
| 0 | Covered | T1,T2,T3 |
153 if (!rst_ni) begin -1- 154 outstanding_txn <= '0; ==> 155 end else if (a_ack && !d_ack) begin -2- 156 outstanding_txn <= outstanding_txn + 1'b1; ==> 157 end else if (d_ack && !a_ack) begin -3- 158 outstanding_txn <= outstanding_txn - 1'b1; ==> 159 end MISSING_ELSE ==>
Branches:
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 1 | - | - | Covered | T1,T2,T3 |
| 0 | 1 | - | Covered | T2,T3,T20 |
| 0 | 0 | 1 | Covered | T2,T3,T20 |
| 0 | 0 | 0 | Covered | T1,T2,T3 |
171 unique case (state_q) -1- 172 StActive: begin 173 if (lc_tx_test_false_loose(lc_en_i) || flush_req_i) begin -2- 174 state_d = StOutstanding; ==> 175 end MISSING_ELSE ==> 176 if (outstanding_txn != '0) begin -3- 177 resp_pending_o = 1'b1; ==> 178 end MISSING_ELSE ==> 179 end 180 181 StOutstanding: begin 182 block_cmd = 1'b1; 183 if (outstanding_txn == '0) begin -4- 184 state_d = lc_tx_test_false_loose(lc_en_i) ? StError : StFlush; ==> 185 end else begin 186 resp_pending_o = 1'b1; ==> 187 end 188 end 189 190 StFlush: begin 191 block_cmd = 1'b1; 192 flush_ack_o = 1'b1; 193 if (lc_tx_test_false_loose(lc_en_i)) begin -5- 194 state_d = StError; ==> 195 end else if (!flush_req_i) begin -6- 196 state_d = StActive; ==> 197 end MISSING_ELSE ==> 198 end 199 200 StError: begin 201 err_en = On; 202 if (lc_tx_test_true_strict(lc_en_i)) begin -7- 203 state_d = StErrorOutstanding; ==> 204 end MISSING_ELSE ==> 205 end 206 207 StErrorOutstanding: begin 208 err_en = On; 209 block_cmd = 1'b1; 210 if (outstanding_txn == '0) begin -8- 211 state_d = StActive; ==> 212 end MISSING_ELSE ==> 213 end 214 215 default: begin 216 err_o = 1'b1; ==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
|---|---|---|---|---|---|---|---|---|---|
| StActive | 1 | - | - | - | - | - | - | Covered | T7,T8,T9 |
| StActive | 0 | - | - | - | - | - | - | Covered | T1,T2,T3 |
| StActive | - | 1 | - | - | - | - | - | Covered | T2,T3,T20 |
| StActive | - | 0 | - | - | - | - | - | Covered | T1,T2,T3 |
| StOutstanding | - | - | 1 | - | - | - | - | Covered | T7,T8,T9 |
| StOutstanding | - | - | 0 | - | - | - | - | Covered | T9,T10,T22 |
| StFlush | - | - | - | 1 | - | - | - | Covered | T10,T11 |
| StFlush | - | - | - | 0 | 1 | - | - | Covered | T10,T11 |
| StFlush | - | - | - | 0 | 0 | - | - | Not Covered | |
| StError | - | - | - | - | - | 1 | - | Covered | T1,T2,T3 |
| StError | - | - | - | - | - | 0 | - | Covered | T7,T8,T9 |
| StErrorOutstanding | - | - | - | - | - | - | 1 | Covered | T1,T2,T3 |
| StErrorOutstanding | - | - | - | - | - | - | 0 | Covered | T10,T11 |
| default | - | - | - | - | - | - | - | Covered | T10,T11,T16 |
234 if (lc_tx_test_true_loose(err_en)) begin -1- 235 tl_h2d_error = tl_h2d_i; ==> 236 tl_d2h_o = tl_d2h_error; 237 end MISSING_ELSE ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| 1 | Covered | T1,T2,T3 |
| 0 | Covered | T1,T2,T3 |
239 if (block_cmd) begin -1- 240 tl_d2h_o.a_ready = 1'b0; ==> 241 tl_h2d_int[0].a_valid = 1'b0; 242 tl_h2d_error.a_valid = 1'b0; 243 end MISSING_ELSE ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| 1 | Covered | T1,T2,T3 |
| 0 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tl_gate
| Total | Attempted | Percent | Succeeded/Matched | Percent | |
|---|---|---|---|---|---|
| Assertions | 2 | 2 | 100.00 | 1 | 50.00 |
| Cover properties | 0 | 0 | 0 | ||
| Cover sequences | 0 | 0 | 0 | ||
| Total | 2 | 2 | 100.00 | 1 | 50.00 |
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
| OutStandingOvfl_A | 388255766 | 0 | 0 | 0 |
| u_state_regs_A | 388255766 | 387415641 | 0 | 0 |
OutStandingOvfl_A
| Name | Attempts | Real Successes | Failures | Incomplete |
|---|---|---|---|---|
| Total | 388255766 | 0 | 0 | 0 |
u_state_regs_A
| Name | Attempts | Real Successes | Failures | Incomplete |
|---|---|---|---|---|
| Total | 388255766 | 387415641 | 0 | 0 |
| T1 | 3906 | 3853 | 0 | 0 |
| T2 | 10848 | 10778 | 0 | 0 |
| T3 | 1224 | 1167 | 0 | 0 |
| T4 | 890 | 840 | 0 | 0 |
| T7 | 972 | 922 | 0 | 0 |
| T12 | 2002 | 1944 | 0 | 0 |
| T17 | 1544 | 1489 | 0 | 0 |
| T18 | 1950 | 1866 | 0 | 0 |
| T19 | 2303 | 2211 | 0 | 0 |
| T20 | 1473 | 1338 | 0 | 0 |