Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 97.92 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block] 95.83 1 100 1 64 64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] 100.00 1 100 1 64 64



Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
95.83 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 1 15 93.75


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 1 15 93.75 100 1 1 0


Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 17865 1 T111 1174 T112 1019 T69 39
full_word 3771602 1 T2 276 T3 10 T20 6


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 3789180 1 T2 276 T3 10 T20 6
auto[TlIntgErrCmd] 95 1 T266 5 T267 3 T268 1
auto[TlIntgErrData] 102 1 T266 3 T267 4 T268 6
auto[TlIntgErrBoth] 90 1 T266 1 T267 2 T268 3


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3766617 1 T2 276 T3 10 T20 6
auto[1] 22850 1 T111 1641 T112 1138 T69 57


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 1 15 93.75 1


Automatically Generated Cross Bins for cr_all

Uncovered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTNUMBER
[auto[TlIntgErrBoth]] [full_word] [auto[0]] 0 1 1


Covered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 1150 1 T111 93 T112 80 T69 2
auto[TlIntgErrNone] partial auto[1] 16446 1 T111 1081 T112 939 T69 37
auto[TlIntgErrNone] full_word auto[0] 3765346 1 T2 276 T3 10 T20 6
auto[TlIntgErrNone] full_word auto[1] 6238 1 T111 560 T112 199 T69 20
auto[TlIntgErrCmd] partial auto[0] 29 1 T266 2 T267 1 T268 1
auto[TlIntgErrCmd] partial auto[1] 59 1 T266 3 T267 2 T375 1
auto[TlIntgErrCmd] full_word auto[0] 2 1 T384 1 T381 1 - -
auto[TlIntgErrCmd] full_word auto[1] 5 1 T379 1 T378 1 T288 1
auto[TlIntgErrData] partial auto[0] 53 1 T266 2 T267 2 T268 2
auto[TlIntgErrData] partial auto[1] 42 1 T266 1 T267 2 T268 3
auto[TlIntgErrData] full_word auto[0] 5 1 T268 1 T385 1 T382 1
auto[TlIntgErrData] full_word auto[1] 2 1 T288 1 T386 1 - -
auto[TlIntgErrBoth] partial auto[0] 32 1 T268 2 T375 1 T376 1
auto[TlIntgErrBoth] partial auto[1] 54 1 T266 1 T267 2 T268 1
auto[TlIntgErrBoth] full_word auto[1] 4 1 T379 1 T378 1 T381 1


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 23761176 1 T1 1128 T2 947 T3 58
full_word 7805984 1 T1 160 T2 2474 T3 3


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 31566850 1 T1 1288 T2 3421 T3 61
auto[TlIntgErrCmd] 123 1 T266 4 T267 3 T268 1
auto[TlIntgErrData] 96 1 T266 2 T267 5 T268 4
auto[TlIntgErrBoth] 91 1 T266 4 T267 2 T268 5


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 27151201 1 T1 1125 T2 1312 T3 57
auto[1] 4415959 1 T1 163 T2 2109 T3 4


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 23055822 1 T1 1115 T2 750 T3 57
auto[TlIntgErrNone] partial auto[1] 705068 1 T1 13 T2 197 T3 1
auto[TlIntgErrNone] full_word auto[0] 4095227 1 T1 10 T2 562 T17 157
auto[TlIntgErrNone] full_word auto[1] 3710733 1 T1 150 T2 1912 T3 3
auto[TlIntgErrCmd] partial auto[0] 62 1 T266 2 T375 2 T376 3
auto[TlIntgErrCmd] partial auto[1] 51 1 T266 2 T267 3 T268 1
auto[TlIntgErrCmd] full_word auto[0] 4 1 T376 1 T378 1 T387 1
auto[TlIntgErrCmd] full_word auto[1] 6 1 T377 1 T379 1 T378 1
auto[TlIntgErrData] partial auto[0] 45 1 T266 1 T267 1 T268 3
auto[TlIntgErrData] partial auto[1] 42 1 T267 3 T268 1 T376 1
auto[TlIntgErrData] full_word auto[0] 5 1 T266 1 T375 1 T383 1
auto[TlIntgErrData] full_word auto[1] 4 1 T267 1 T384 1 T388 2
auto[TlIntgErrBoth] partial auto[0] 33 1 T266 2 T268 1 T375 1
auto[TlIntgErrBoth] partial auto[1] 53 1 T266 2 T267 2 T268 3
auto[TlIntgErrBoth] full_word auto[0] 3 1 T382 1 T387 1 T386 1
auto[TlIntgErrBoth] full_word auto[1] 2 1 T268 1 T384 1 - -

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