Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_flash_ctrl_erase

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.69 97.12 93.60 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_ctrl_erase
Line No.TotalCoveredPercent
TOTAL99100.00
CONT_ASSIGN4300
CONT_ASSIGN4611100.00
ALWAYS4933100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN5811100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6611100.00

42 logic oob_err; 43 unreachable assign oob_err = op_start_i & op_addr_oob_i; 44 45 // IO assignments 46 1/1 assign op_done_o = flash_req_o & (flash_done_i | oob_err); Tests: T1 T2 T3  47 48 always_comb begin 49 1/1 op_err_o = '0; Tests: T1 T2 T3  50 1/1 op_err_o.oob_err = op_done_o & oob_err; Tests: T1 T2 T3  51 1/1 op_err_o.mp_err = op_done_o & flash_mp_err_i; Tests: T1 T2 T3  52 end 53 54 55 // Flash Interface assignments 56 1/1 assign flash_req_o = op_start_i & ~op_addr_oob_i; Tests: T1 T2 T3  57 1/1 assign flash_op_o = op_type_i; Tests: T1 T2 T3  58 1/1 assign flash_addr_o = (op_type_i == FlashErasePage) ? Tests: T1 T2 T3  59 op_addr_i & PageAddrMask : 60 op_addr_i & BankAddrMask; 61 62 1/1 assign op_err_addr_o = flash_addr_o; Tests: T1 T2 T3  63 64 // unused bus 65 logic [WordsBitWidth-1:0] unused_addr_i; 66 1/1 assign unused_addr_i = op_addr_i[WordsBitWidth-1:0]; Tests: T1 T2 T3 

Cond Coverage for Module : flash_ctrl_erase
TotalCoveredPercent
Conditions1616100.00
Logical1616100.00
Non-Logical00
Event00

 LINE       43
 EXPRESSION (op_start_i & op_addr_oob_i)
             -----1----   ------2------
-1--2-StatusTests
01Unreachable
10CoveredT12,T23,T14
11Unreachable

 LINE       46
 EXPRESSION (flash_req_o & (flash_done_i | oob_err))
             -----1-----   ------------2-----------
-1--2-StatusTests
01CoveredT8,T27,T98
10CoveredT12,T23,T14
11CoveredT12,T23,T14

 LINE       46
 SUB-EXPRESSION (flash_done_i | oob_err)
                 ------1-----   ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT12,T23,T14

 LINE       50
 EXPRESSION (op_done_o & oob_err)
             ----1----   ---2---
-1--2-StatusTests
01Unreachable
10CoveredT12,T23,T14
11Unreachable

 LINE       51
 EXPRESSION (op_done_o & flash_mp_err_i)
             ----1----   -------2------
-1--2-StatusTests
01CoveredT8,T27,T98
10CoveredT12,T23,T14
11CoveredT23,T30,T31

 LINE       56
 EXPRESSION (op_start_i & ((~op_addr_oob_i)))
             -----1----   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11CoveredT12,T23,T14

 LINE       58
 EXPRESSION ((op_type_i == FlashErasePage) ? ((op_addr_i & PageAddrMask)) : ((op_addr_i & BankAddrMask)))
             --------------1--------------
-1-StatusTests
0CoveredT2,T17,T20
1CoveredT1,T2,T3

 LINE       58
 SUB-EXPRESSION (op_type_i == FlashErasePage)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : flash_ctrl_erase
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 58 2 2 100.00


58 assign flash_addr_o = (op_type_i == FlashErasePage) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T17,T20

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%