Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.52 100.00 88.89 91.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.52 100.00 88.89 91.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.65 100.00 92.86 93.75 100.00 gen_prim_flash_banks[0].u_prim_flash_bank


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.52 100.00 88.89 91.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.52 100.00 88.89 91.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.65 100.00 92.86 93.75 100.00 gen_prim_flash_banks[1].u_prim_flash_bank


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : flash_ctrl_phy_cov_if
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN2411100.00
CONT_ASSIGN2611100.00
ALWAYS3288100.00
ALWAYS4344100.00
ALWAYS5633100.00
CONT_ASSIGN6311100.00

23 logic any_req; 24 1/1 assign any_req = rd_req || prog_req || pg_erase_req || bk_erase_req; Tests: T1 T2 T3  25 logic any_vld_req; 26 1/1 assign any_vld_req = any_req && ack; Tests: T1 T2 T3  27 28 // Decode current command 29 typedef enum logic[1:0] {READ, PROG, ERASE, NONE} cmd_e; 30 cmd_e cur_cmd; 31 always_comb begin 32 1/1 cur_cmd = NONE; Tests: T1 T2 T3  33 1/1 if (any_vld_req) begin Tests: T1 T2 T3  34 2/2 if (rd_req) cur_cmd = READ; Tests: T1 T2 T3  | T1 T2 T3  35 2/2 else if (prog_req) cur_cmd = PROG; Tests: T1 T12 T20  | T1 T12 T20  36 2/2 else if (pg_erase_req || bk_erase_req) cur_cmd = ERASE; Tests: T12 T23 T14  | T12 T23 T14  MISSING_ELSE 37 end MISSING_ELSE 38 end 39 40 // previous command 41 cmd_e prv_cmd_q; 42 always @(posedge clk_i) begin 43 1/1 if (!rst_ni) begin Tests: T1 T2 T3  44 1/1 prv_cmd_q <= NONE; Tests: T1 T2 T3  45 end else begin 46 1/1 if (any_vld_req) begin Tests: T1 T2 T3  47 1/1 prv_cmd_q <= cur_cmd; Tests: T1 T2 T3  48 end MISSING_ELSE 49 end 50 end 51 52 // command interval counter 53 // couter will be saturated when it hits maxium 54 bit [31:0] idle_cnt; 55 always @(posedge clk_i) begin 56 2/2 if (!rst_ni || !rd_buf_en) idle_cnt <= 0; Tests: T1 T2 T3  | T1 T2 T3  57 1/1 else idle_cnt <= (any_vld_req)? 0 : Tests: T1 T2 T3  58 (idle_cnt == 32'hffff_ffff)? 32'hffff_ffff : idle_cnt + 32'h1; 59 end 60 61 // back to back read sequence 62 logic b2b_read; 63 1/1 assign b2b_read = (cur_cmd == READ && prv_cmd_q == READ); Tests: T1 T2 T3 

Cond Coverage for Module : flash_ctrl_phy_cov_if
TotalCoveredPercent
Conditions272488.89
Logical272488.89
Non-Logical00
Event00

 LINE       24
 EXPRESSION (rd_req || prog_req || pg_erase_req || bk_erase_req)
             ---1--    ----2---    ------3-----    ------4-----
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT74,T25,T65
0010CoveredT12,T23,T14
0100CoveredT1,T12,T20
1000CoveredT1,T2,T3

 LINE       26
 EXPRESSION (any_req && ack)
             ---1---    -2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T12,T14
11CoveredT1,T2,T3

 LINE       36
 EXPRESSION (pg_erase_req || bk_erase_req)
             ------1-----    ------2-----
-1--2-StatusTests
00CoveredT10,T11
01CoveredT74,T25,T65
10CoveredT12,T23,T14

 LINE       56
 EXPRESSION (((!rst_ni)) || ((!rd_buf_en)))
             -----1-----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       57
 EXPRESSION (any_vld_req ? 0 : ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1))))
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       57
 SUB-EXPRESSION ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1)))
                 -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       57
 SUB-EXPRESSION (idle_cnt == 32'hffffffff)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       63
 EXPRESSION ((cur_cmd == READ) && (prv_cmd_q == READ))
             --------1--------    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       63
 SUB-EXPRESSION (cur_cmd == READ)
                --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       63
 SUB-EXPRESSION (prv_cmd_q == READ)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : flash_ctrl_phy_cov_if
Line No.TotalCoveredPercent
Branches 12 11 91.67
IF 33 5 5 100.00
IF 43 3 3 100.00
IF 56 4 3 75.00


33 if (any_vld_req) begin -1- 34 if (rd_req) cur_cmd = READ; -2- ==> 35 else if (prog_req) cur_cmd = PROG; -3- ==> 36 else if (pg_erase_req || bk_erase_req) cur_cmd = ERASE; -4- ==> MISSING_ELSE ==> 37 end MISSING_ELSE ==>

Branches:
-1--2--3--4-StatusTests
1 1 - - Covered T1,T2,T3
1 0 1 - Covered T1,T12,T20
1 0 0 1 Covered T12,T23,T14
1 0 0 0 Covered T10,T11
0 - - - Covered T1,T2,T3


43 if (!rst_ni) begin -1- 44 prv_cmd_q <= NONE; ==> 45 end else begin 46 if (any_vld_req) begin -2- 47 prv_cmd_q <= cur_cmd; ==> 48 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


56 if (!rst_ni || !rd_buf_en) idle_cnt <= 0; -1- ==> 57 else idle_cnt <= (any_vld_req)? 0 : -2- ==> 58 (idle_cnt == 32'hffff_ffff)? 32'hffff_ffff : idle_cnt + 32'h1; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN2411100.00
CONT_ASSIGN2611100.00
ALWAYS3288100.00
ALWAYS4344100.00
ALWAYS5633100.00
CONT_ASSIGN6311100.00

23 logic any_req; 24 1/1 assign any_req = rd_req || prog_req || pg_erase_req || bk_erase_req; Tests: T1 T2 T3  25 logic any_vld_req; 26 1/1 assign any_vld_req = any_req && ack; Tests: T1 T2 T3  27 28 // Decode current command 29 typedef enum logic[1:0] {READ, PROG, ERASE, NONE} cmd_e; 30 cmd_e cur_cmd; 31 always_comb begin 32 1/1 cur_cmd = NONE; Tests: T1 T2 T3  33 1/1 if (any_vld_req) begin Tests: T1 T2 T3  34 2/2 if (rd_req) cur_cmd = READ; Tests: T1 T2 T3  | T1 T2 T3  35 2/2 else if (prog_req) cur_cmd = PROG; Tests: T12 T20 T23  | T12 T20 T13  36 2/2 else if (pg_erase_req || bk_erase_req) cur_cmd = ERASE; Tests: T12 T23 T14  | T12 T23 T14  MISSING_ELSE 37 end MISSING_ELSE 38 end 39 40 // previous command 41 cmd_e prv_cmd_q; 42 always @(posedge clk_i) begin 43 1/1 if (!rst_ni) begin Tests: T1 T2 T3  44 1/1 prv_cmd_q <= NONE; Tests: T1 T2 T3  45 end else begin 46 1/1 if (any_vld_req) begin Tests: T1 T2 T3  47 1/1 prv_cmd_q <= cur_cmd; Tests: T1 T2 T3  48 end MISSING_ELSE 49 end 50 end 51 52 // command interval counter 53 // couter will be saturated when it hits maxium 54 bit [31:0] idle_cnt; 55 always @(posedge clk_i) begin 56 2/2 if (!rst_ni || !rd_buf_en) idle_cnt <= 0; Tests: T1 T2 T3  | T1 T2 T3  57 1/1 else idle_cnt <= (any_vld_req)? 0 : Tests: T1 T2 T3  58 (idle_cnt == 32'hffff_ffff)? 32'hffff_ffff : idle_cnt + 32'h1; 59 end 60 61 // back to back read sequence 62 logic b2b_read; 63 1/1 assign b2b_read = (cur_cmd == READ && prv_cmd_q == READ); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if
TotalCoveredPercent
Conditions272488.89
Logical272488.89
Non-Logical00
Event00

 LINE       24
 EXPRESSION (rd_req || prog_req || pg_erase_req || bk_erase_req)
             ---1--    ----2---    ------3-----    ------4-----
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT25,T75,T76
0010CoveredT12,T23,T14
0100CoveredT12,T20,T13
1000CoveredT1,T2,T3

 LINE       26
 EXPRESSION (any_req && ack)
             ---1---    -2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT12,T14,T8
11CoveredT1,T2,T3

 LINE       36
 EXPRESSION (pg_erase_req || bk_erase_req)
             ------1-----    ------2-----
-1--2-StatusTests
00CoveredT10,T11
01CoveredT25,T75,T76
10CoveredT12,T23,T14

 LINE       56
 EXPRESSION (((!rst_ni)) || ((!rd_buf_en)))
             -----1-----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       57
 EXPRESSION (any_vld_req ? 0 : ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1))))
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T17

 LINE       57
 SUB-EXPRESSION ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1)))
                 -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       57
 SUB-EXPRESSION (idle_cnt == 32'hffffffff)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       63
 EXPRESSION ((cur_cmd == READ) && (prv_cmd_q == READ))
             --------1--------    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       63
 SUB-EXPRESSION (cur_cmd == READ)
                --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       63
 SUB-EXPRESSION (prv_cmd_q == READ)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if
Line No.TotalCoveredPercent
Branches 12 11 91.67
IF 33 5 5 100.00
IF 43 3 3 100.00
IF 56 4 3 75.00


33 if (any_vld_req) begin -1- 34 if (rd_req) cur_cmd = READ; -2- ==> 35 else if (prog_req) cur_cmd = PROG; -3- ==> 36 else if (pg_erase_req || bk_erase_req) cur_cmd = ERASE; -4- ==> MISSING_ELSE ==> 37 end MISSING_ELSE ==>

Branches:
-1--2--3--4-StatusTests
1 1 - - Covered T1,T2,T3
1 0 1 - Covered T12,T20,T13
1 0 0 1 Covered T12,T23,T14
1 0 0 0 Covered T10,T11
0 - - - Covered T1,T2,T3


43 if (!rst_ni) begin -1- 44 prv_cmd_q <= NONE; ==> 45 end else begin 46 if (any_vld_req) begin -2- 47 prv_cmd_q <= cur_cmd; ==> 48 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


56 if (!rst_ni || !rd_buf_en) idle_cnt <= 0; -1- ==> 57 else idle_cnt <= (any_vld_req)? 0 : -2- ==> 58 (idle_cnt == 32'hffff_ffff)? 32'hffff_ffff : idle_cnt + 32'h1; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T3,T17
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN2411100.00
CONT_ASSIGN2611100.00
ALWAYS3288100.00
ALWAYS4344100.00
ALWAYS5633100.00
CONT_ASSIGN6311100.00

23 logic any_req; 24 1/1 assign any_req = rd_req || prog_req || pg_erase_req || bk_erase_req; Tests: T1 T2 T3  25 logic any_vld_req; 26 1/1 assign any_vld_req = any_req && ack; Tests: T1 T2 T3  27 28 // Decode current command 29 typedef enum logic[1:0] {READ, PROG, ERASE, NONE} cmd_e; 30 cmd_e cur_cmd; 31 always_comb begin 32 1/1 cur_cmd = NONE; Tests: T1 T2 T3  33 1/1 if (any_vld_req) begin Tests: T1 T2 T3  34 2/2 if (rd_req) cur_cmd = READ; Tests: T1 T2 T18  | T2 T18 T20  35 2/2 else if (prog_req) cur_cmd = PROG; Tests: T1 T23 T9  | T1 T9 T51  36 2/2 else if (pg_erase_req || bk_erase_req) cur_cmd = ERASE; Tests: T23 T51 T10  | T23 T51 T10  MISSING_ELSE 37 end MISSING_ELSE 38 end 39 40 // previous command 41 cmd_e prv_cmd_q; 42 always @(posedge clk_i) begin 43 1/1 if (!rst_ni) begin Tests: T1 T2 T3  44 1/1 prv_cmd_q <= NONE; Tests: T1 T2 T3  45 end else begin 46 1/1 if (any_vld_req) begin Tests: T1 T2 T3  47 1/1 prv_cmd_q <= cur_cmd; Tests: T1 T2 T18  48 end MISSING_ELSE 49 end 50 end 51 52 // command interval counter 53 // couter will be saturated when it hits maxium 54 bit [31:0] idle_cnt; 55 always @(posedge clk_i) begin 56 2/2 if (!rst_ni || !rd_buf_en) idle_cnt <= 0; Tests: T1 T2 T3  | T1 T2 T3  57 1/1 else idle_cnt <= (any_vld_req)? 0 : Tests: T1 T2 T3  58 (idle_cnt == 32'hffff_ffff)? 32'hffff_ffff : idle_cnt + 32'h1; 59 end 60 61 // back to back read sequence 62 logic b2b_read; 63 1/1 assign b2b_read = (cur_cmd == READ && prv_cmd_q == READ); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if
TotalCoveredPercent
Conditions272488.89
Logical272488.89
Non-Logical00
Event00

 LINE       24
 EXPRESSION (rd_req || prog_req || pg_erase_req || bk_erase_req)
             ---1--    ----2---    ------3-----    ------4-----
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT74,T65,T75
0010CoveredT23,T51,T46
0100CoveredT1,T9,T51
1000CoveredT2,T18,T20

 LINE       26
 EXPRESSION (any_req && ack)
             ---1---    -2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T51,T27
11CoveredT1,T2,T18

 LINE       36
 EXPRESSION (pg_erase_req || bk_erase_req)
             ------1-----    ------2-----
-1--2-StatusTests
00CoveredT11
01CoveredT74,T65,T75
10CoveredT23,T51,T46

 LINE       56
 EXPRESSION (((!rst_ni)) || ((!rd_buf_en)))
             -----1-----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       57
 EXPRESSION (any_vld_req ? 0 : ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1))))
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T18

 LINE       57
 SUB-EXPRESSION ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1)))
                 -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       57
 SUB-EXPRESSION (idle_cnt == 32'hffffffff)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       63
 EXPRESSION ((cur_cmd == READ) && (prv_cmd_q == READ))
             --------1--------    ---------2---------
-1--2-StatusTests
01CoveredT2,T18,T20
10CoveredT2,T18,T20
11CoveredT2,T18,T20

 LINE       63
 SUB-EXPRESSION (cur_cmd == READ)
                --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T20

 LINE       63
 SUB-EXPRESSION (prv_cmd_q == READ)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T18,T20

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if
Line No.TotalCoveredPercent
Branches 12 11 91.67
IF 33 5 5 100.00
IF 43 3 3 100.00
IF 56 4 3 75.00


33 if (any_vld_req) begin -1- 34 if (rd_req) cur_cmd = READ; -2- ==> 35 else if (prog_req) cur_cmd = PROG; -3- ==> 36 else if (pg_erase_req || bk_erase_req) cur_cmd = ERASE; -4- ==> MISSING_ELSE ==> 37 end MISSING_ELSE ==>

Branches:
-1--2--3--4-StatusTests
1 1 - - Covered T2,T18,T20
1 0 1 - Covered T1,T9,T51
1 0 0 1 Covered T23,T51,T10
1 0 0 0 Covered T10,T11
0 - - - Covered T1,T2,T3


43 if (!rst_ni) begin -1- 44 prv_cmd_q <= NONE; ==> 45 end else begin 46 if (any_vld_req) begin -2- 47 prv_cmd_q <= cur_cmd; ==> 48 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T18
0 0 Covered T1,T2,T3


56 if (!rst_ni || !rd_buf_en) idle_cnt <= 0; -1- ==> 57 else idle_cnt <= (any_vld_req)? 0 : -2- ==> 58 (idle_cnt == 32'hffff_ffff)? 32'hffff_ffff : idle_cnt + 32'h1; -3- ==> ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T18
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%