Unified Coverage Report :: Module :: flash_mp_data_region_sel

Module : flash_mp_data_region_sel

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_mp.u_sw_sel	100.00	100.00	100.00			100.00
tb.dut.u_flash_mp.u_hw_sel	100.00	100.00				100.00
tb.dut.u_eflash.u_region_sel	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_flash_mp.u_sw_sel

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.64	100.00	98.56			100.00	100.00	u_flash_mp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_flash_mp.u_hw_sel

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.64	100.00	98.56			100.00	100.00	u_flash_mp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_region_sel

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.22	97.67	88.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : flash_mp_data_region_sel ( parameter Regions=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_flash_mp.u_sw_sel

SCORE	LINE
100.00	100.00

tb.dut.u_eflash.u_region_sel

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
ALWAYS	35	0	0
ALWAYS	35	3	3	100.00
ALWAYS	49	4	4	100.00

27                        // decode for software interface region
28         1/1            assign region_sel[0] = region_match[0];
           Tests:       T1 T2 T3 
29                        for (genvar i = 1; i < Regions; i++) begin: gen_region_priority
30         8/8              assign region_sel[i] = region_match[i] & ~|region_match[i-1:0];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
31                        end
32                      
33                        // check for region match
34                        always_comb begin
35         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_comps
           Tests:       T1 T2 T3 
36         1/1                region_end[i] = {1'b0, region_attrs_i[i].cfg.base} + region_attrs_i[i].cfg.size;
           Tests:       T1 T2 T3 
37                      
38                            // region matches if address within range and if the partition matches
39         1/1                region_match[i] = addr_i >= region_attrs_i[i].cfg.base &
           Tests:       T1 T2 T3 
40                                              {1'b0, addr_i} < region_end[i] &
41                                              phase_i == region_attrs_i[i].phase &
42                                              mubi4_test_true_strict(region_attrs_i[i].cfg.en) &
43                                              req_i;
44                          end
45                        end
46                      
47                        // select appropriate region configuration
48                        always_comb begin
49         1/1              sel_cfg_o = '0;
           Tests:       T1 T2 T3 
50         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_sel
           Tests:       T1 T2 T3 
51         1/1                if (region_sel[i]) begin
           Tests:       T1 T2 T3 
52         1/1                  sel_cfg_o = region_attrs_i[i].cfg;
           Tests:       T1 T2 T3 
53                            end
                        MISSING_ELSE

---

Line Coverage for Module : flash_mp_data_region_sel ( parameter Regions=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_flash_mp.u_hw_sel

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	35	0	0
ALWAYS	35	3	3	100.00
ALWAYS	49	4	4	100.00

27                        // decode for software interface region
28         1/1            assign region_sel[0] = region_match[0];
           Tests:       T1 T2 T3 
29                        for (genvar i = 1; i < Regions; i++) begin: gen_region_priority
30                          assign region_sel[i] = region_match[i] & ~|region_match[i-1:0];
31                        end
32                      
33                        // check for region match
34                        always_comb begin
35         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_comps
           Tests:       T1 T2 T3 
36         1/1                region_end[i] = {1'b0, region_attrs_i[i].cfg.base} + region_attrs_i[i].cfg.size;
           Tests:       T1 T2 T3 
37                      
38                            // region matches if address within range and if the partition matches
39         1/1                region_match[i] = addr_i >= region_attrs_i[i].cfg.base &
           Tests:       T1 T2 T3 
40                                              {1'b0, addr_i} < region_end[i] &
41                                              phase_i == region_attrs_i[i].phase &
42                                              mubi4_test_true_strict(region_attrs_i[i].cfg.en) &
43                                              req_i;
44                          end
45                        end
46                      
47                        // select appropriate region configuration
48                        always_comb begin
49         1/1              sel_cfg_o = '0;
           Tests:       T1 T2 T3 
50         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_sel
           Tests:       T1 T2 T3 
51         1/1                if (region_sel[i]) begin
           Tests:       T1 T2 T3 
52         1/1                  sel_cfg_o = region_attrs_i[i].cfg;
           Tests:       T10 T119 T116 
53                            end
                        MISSING_ELSE

---

Cond Coverage for Module : flash_mp_data_region_sel

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T25,T178,T11
1	1	Covered	T23,T13,T9

 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T25,T289
1	1	Covered	T19,T23,T64

 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T290,T231,T225
1	1	Covered	T13,T54,T39

 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T58,T25
1	1	Covered	T20,T23,T15

 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T41,T25,T150
1	1	Covered	T27,T40,T41

 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T48,T25
1	1	Covered	T23,T8,T15

 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T25,T97
1	1	Covered	T98,T39,T40

 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T19,T20
1	1	Covered	T1,T2,T17

---

Branch Coverage for Module : flash_mp_data_region_sel

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	51	2	2	100.00

51               if (region_sel[i]) begin
                 -1-  
52                 sel_cfg_o = region_attrs_i[i].cfg;
                   ==>
53               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
ALWAYS	35	0	0
ALWAYS	35	3	3	100.00
ALWAYS	49	4	4	100.00

27                        // decode for software interface region
28         1/1            assign region_sel[0] = region_match[0];
           Tests:       T1 T2 T3 
29                        for (genvar i = 1; i < Regions; i++) begin: gen_region_priority
30         8/8              assign region_sel[i] = region_match[i] & ~|region_match[i-1:0];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
31                        end
32                      
33                        // check for region match
34                        always_comb begin
35         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_comps
           Tests:       T1 T2 T3 
36         1/1                region_end[i] = {1'b0, region_attrs_i[i].cfg.base} + region_attrs_i[i].cfg.size;
           Tests:       T1 T2 T3 
37                      
38                            // region matches if address within range and if the partition matches
39         1/1                region_match[i] = addr_i >= region_attrs_i[i].cfg.base &
           Tests:       T1 T2 T3 
40                                              {1'b0, addr_i} < region_end[i] &
41                                              phase_i == region_attrs_i[i].phase &
42                                              mubi4_test_true_strict(region_attrs_i[i].cfg.en) &
43                                              req_i;
44                          end
45                        end
46                      
47                        // select appropriate region configuration
48                        always_comb begin
49         1/1              sel_cfg_o = '0;
           Tests:       T1 T2 T3 
50         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_sel
           Tests:       T1 T2 T3 
51         1/1                if (region_sel[i]) begin
           Tests:       T1 T2 T3 
52         1/1                  sel_cfg_o = region_attrs_i[i].cfg;
           Tests:       T1 T2 T17 
53                            end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T25,T178,T291
1	1	Covered	T13,T9,T27

 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T25,T231
1	1	Covered	T19,T64,T27

 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T290,T231,T225
1	1	Covered	T39,T40,T31

 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T25,T28,T231
1	1	Covered	T15,T27,T40

 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T25,T150,T231
1	1	Covered	T27,T40,T31

 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T25,T217,T84
1	1	Covered	T23,T8,T15

 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T25,T97,T231
1	1	Covered	T98,T39,T40

 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T7,T23
1	1	Covered	T1,T2,T17

---

Branch Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	51	2	2	100.00

51               if (region_sel[i]) begin
                 -1-  
52                 sel_cfg_o = region_attrs_i[i].cfg;
                   ==>
53               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T17
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_mp.u_hw_sel

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	35	0	0
ALWAYS	35	3	3	100.00
ALWAYS	49	4	4	100.00

27                        // decode for software interface region
28         1/1            assign region_sel[0] = region_match[0];
           Tests:       T1 T2 T3 
29                        for (genvar i = 1; i < Regions; i++) begin: gen_region_priority
30                          assign region_sel[i] = region_match[i] & ~|region_match[i-1:0];
31                        end
32                      
33                        // check for region match
34                        always_comb begin
35         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_comps
           Tests:       T1 T2 T3 
36         1/1                region_end[i] = {1'b0, region_attrs_i[i].cfg.base} + region_attrs_i[i].cfg.size;
           Tests:       T1 T2 T3 
37                      
38                            // region matches if address within range and if the partition matches
39         1/1                region_match[i] = addr_i >= region_attrs_i[i].cfg.base &
           Tests:       T1 T2 T3 
40                                              {1'b0, addr_i} < region_end[i] &
41                                              phase_i == region_attrs_i[i].phase &
42                                              mubi4_test_true_strict(region_attrs_i[i].cfg.en) &
43                                              req_i;
44                          end
45                        end
46                      
47                        // select appropriate region configuration
48                        always_comb begin
49         1/1              sel_cfg_o = '0;
           Tests:       T1 T2 T3 
50         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_sel
           Tests:       T1 T2 T3 
51         1/1                if (region_sel[i]) begin
           Tests:       T1 T2 T3 
52         1/1                  sel_cfg_o = region_attrs_i[i].cfg;
           Tests:       T10 T119 T116 
53                            end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_flash_mp.u_hw_sel

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	51	2	2	100.00

51               if (region_sel[i]) begin
                 -1-  
52                 sel_cfg_o = region_attrs_i[i].cfg;
                   ==>
53               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T10,T119,T116
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_region_sel

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
ALWAYS	35	0	0
ALWAYS	35	3	3	100.00
ALWAYS	49	4	4	100.00

27                        // decode for software interface region
28         1/1            assign region_sel[0] = region_match[0];
           Tests:       T1 T2 T3 
29                        for (genvar i = 1; i < Regions; i++) begin: gen_region_priority
30         8/8              assign region_sel[i] = region_match[i] & ~|region_match[i-1:0];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
31                        end
32                      
33                        // check for region match
34                        always_comb begin
35         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_comps
           Tests:       T1 T2 T3 
36         1/1                region_end[i] = {1'b0, region_attrs_i[i].cfg.base} + region_attrs_i[i].cfg.size;
           Tests:       T1 T2 T3 
37                      
38                            // region matches if address within range and if the partition matches
39         1/1                region_match[i] = addr_i >= region_attrs_i[i].cfg.base &
           Tests:       T1 T2 T3 
40                                              {1'b0, addr_i} < region_end[i] &
41                                              phase_i == region_attrs_i[i].phase &
42                                              mubi4_test_true_strict(region_attrs_i[i].cfg.en) &
43                                              req_i;
44                          end
45                        end
46                      
47                        // select appropriate region configuration
48                        always_comb begin
49         1/1              sel_cfg_o = '0;
           Tests:       T1 T2 T3 
50         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_sel
           Tests:       T1 T2 T3 
51         1/1                if (region_sel[i]) begin
           Tests:       T1 T2 T3 
52         1/1                  sel_cfg_o = region_attrs_i[i].cfg;
           Tests:       T2 T3 T20 
53                            end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.u_region_sel

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T291,T292
1	1	Covered	T23,T10,T41

 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T289,T261,T231
1	1	Covered	T23,T58,T40

 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T231,T161,T293
1	1	Covered	T13,T54,T40

 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T58,T62
1	1	Covered	T20,T23,T15

 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T41,T26,T231
1	1	Covered	T40,T41,T130

 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T48,T25
1	1	Covered	T40,T36,T99

 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T25,T100
1	1	Covered	T40,T47,T55

 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T20,T23
1	1	Covered	T2,T20,T23

---

Branch Coverage for Instance : tb.dut.u_eflash.u_region_sel

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	51	2	2	100.00

51               if (region_sel[i]) begin
                 -1-  
52                 sel_cfg_o = region_attrs_i[i].cfg;
                   ==>
53               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T20
0	Covered	T1,T2,T3