Unified Coverage Report :: Module :: prim_generic_ram_1p

Module : prim_generic_ram_1p

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_info_types[0].u_info_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_info_types[1].u_info_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_info_types[2].u_info_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_info_types[0].u_info_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_info_types[1].u_info_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_info_types[2].u_info_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1p

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

41                        logic unused_cfg;
42         0/1     ==>    assign unused_cfg = ^cfg_i;
43                      
44                        // Width of internal write mask. Note wmask_i input into the module is always assumed
45                        // to be the full bit mask
46                        localparam int MaskWidth = Width / DataBitsPerMask;
47                      
48                        logic [Width-1:0]     mem [Depth];
49                        logic [MaskWidth-1:0] wmask;
50                      
51                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
52         unreachable      assign wmask[k] = &wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
53                      
54                          // Ensure that all mask bits within a group have the same value for a write
55                          `ASSERT(MaskCheck_A, req_i && write_i |->
56                              wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
57                              clk_i, '0)
58                        end
59                      
60                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
61                        // thrown when using $readmemh system task to backdoor load an image
62                        always @(posedge clk_i) begin
63         1/1              if (req_i) begin
           Tests:       T1 T2 T3 
64         1/1                if (write_i) begin
           Tests:       T1 T2 T3 
65         1/1                  for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T12 T23 T13 
66         1/1                    if (wmask[i]) begin
           Tests:       T12 T23 T13 
67         1/1                      mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T12 T23 T13 
68                                    wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                                end
                   ==>  MISSING_ELSE
70                              end
71                            end else begin
72         1/1                  rdata_o <= mem[addr_i];
           Tests:       T1 T2 T3 
73                            end
74                          end
                        MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1p

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

63             if (req_i) begin
               -1-  
64               if (write_i) begin
                 -2-  
65                 for (int i=0; i < MaskWidth; i = i + 1) begin
                   ==>
66                   if (wmask[i]) begin
67                     mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
68                       wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                   end
70                 end
71               end else begin
72                 rdata_o <= mem[addr_i];
                   ==>
73               end
74             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T12,T23,T13
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1p

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	8456	8456	0	0
gen_wmask[0].MaskCheck_A	2147483647	164106698	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8456	8456	0	0
T1	8	8	0	0
T2	8	8	0	0
T3	8	8	0	0
T4	8	8	0	0
T7	8	8	0	0
T12	8	8	0	0
T17	8	8	0	0
T18	8	8	0	0
T19	8	8	0	0
T20	8	8	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	164106698	0	0
T8	8268	150	0	0
T9	1952	0	0	0
T13	5410	0	0	0
T14	288788	49248	0	0
T15	59020	700	0	0
T20	1473	50	0	0
T23	14598	1536	0	0
T27	225589	8900	0	0
T30	0	256	0	0
T31	0	64000	0	0
T39	0	4950	0	0
T40	0	7550	0	0
T51	324582	0	0	0
T54	5236	0	0	0
T64	2168	0	0	0
T82	1393	0	0	0
T98	0	2050	0	0
T123	851895	0	0	0
T131	96942	606	0	0
T132	0	786432	0	0
T133	0	655360	0	0
T134	0	606	0	0
T135	0	589824	0	0
T136	0	556	0	0
T137	0	606	0	0
T138	0	393216	0	0
T139	0	458752	0	0
T140	0	524288	0	0
T141	199656	0	0	0
T142	4219	0	0	0
T143	1553	0	0	0
T144	382353	0	0	0
T145	47606	0	0	0
T146	4370	0	0	0
T147	3903	0	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

41                        logic unused_cfg;
42         0/1     ==>    assign unused_cfg = ^cfg_i;
43                      
44                        // Width of internal write mask. Note wmask_i input into the module is always assumed
45                        // to be the full bit mask
46                        localparam int MaskWidth = Width / DataBitsPerMask;
47                      
48                        logic [Width-1:0]     mem [Depth];
49                        logic [MaskWidth-1:0] wmask;
50                      
51                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
52         unreachable      assign wmask[k] = &wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
53                      
54                          // Ensure that all mask bits within a group have the same value for a write
55                          `ASSERT(MaskCheck_A, req_i && write_i |->
56                              wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
57                              clk_i, '0)
58                        end
59                      
60                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
61                        // thrown when using $readmemh system task to backdoor load an image
62                        always @(posedge clk_i) begin
63         1/1              if (req_i) begin
           Tests:       T1 T2 T3 
64         1/1                if (write_i) begin
           Tests:       T2 T3 T17 
65         1/1                  for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T12 T23 T13 
66         1/1                    if (wmask[i]) begin
           Tests:       T12 T23 T13 
67         1/1                      mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T12 T23 T13 
68                                    wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                                end
                   ==>  MISSING_ELSE
70                              end
71                            end else begin
72         1/1                  rdata_o <= mem[addr_i];
           Tests:       T2 T3 T17 
73                            end
74                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

63             if (req_i) begin
               -1-  
64               if (write_i) begin
                 -2-  
65                 for (int i=0; i < MaskWidth; i = i + 1) begin
                   ==>
66                   if (wmask[i]) begin
67                     mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
68                       wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                   end
70                 end
71               end else begin
72                 rdata_o <= mem[addr_i];
                   ==>
73               end
74             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T12,T23,T13
1	0	Covered	T2,T3,T17
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1057	1057	0	0
gen_wmask[0].MaskCheck_A	388255766	58140709	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	58140709	0	0
T4	890	0	0	0
T7	972	0	0	0
T8	4134	0	0	0
T9	976	0	0	0
T10	0	9	0	0
T12	2002	506	0	0
T13	2705	50	0	0
T14	144394	0	0	0
T15	29510	0	0	0
T20	1473	0	0	0
T23	7299	1280	0	0
T27	0	55650	0	0
T39	0	17100	0	0
T40	0	5250	0	0
T51	0	25076	0	0
T64	0	400	0	0
T98	0	10500	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

41                        logic unused_cfg;
42         0/1     ==>    assign unused_cfg = ^cfg_i;
43                      
44                        // Width of internal write mask. Note wmask_i input into the module is always assumed
45                        // to be the full bit mask
46                        localparam int MaskWidth = Width / DataBitsPerMask;
47                      
48                        logic [Width-1:0]     mem [Depth];
49                        logic [MaskWidth-1:0] wmask;
50                      
51                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
52         unreachable      assign wmask[k] = &wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
53                      
54                          // Ensure that all mask bits within a group have the same value for a write
55                          `ASSERT(MaskCheck_A, req_i && write_i |->
56                              wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
57                              clk_i, '0)
58                        end
59                      
60                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
61                        // thrown when using $readmemh system task to backdoor load an image
62                        always @(posedge clk_i) begin
63         1/1              if (req_i) begin
           Tests:       T1 T2 T3 
64         1/1                if (write_i) begin
           Tests:       T1 T2 T3 
65         1/1                  for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T23 T14 T8 
66         1/1                    if (wmask[i]) begin
           Tests:       T23 T14 T8 
67         1/1                      mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T23 T14 T8 
68                                    wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                                end
                   ==>  MISSING_ELSE
70                              end
71                            end else begin
72         1/1                  rdata_o <= mem[addr_i];
           Tests:       T1 T2 T3 
73                            end
74                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

63             if (req_i) begin
               -1-  
64               if (write_i) begin
                 -2-  
65                 for (int i=0; i < MaskWidth; i = i + 1) begin
                   ==>
66                   if (wmask[i]) begin
67                     mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
68                       wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                   end
70                 end
71               end else begin
72                 rdata_o <= mem[addr_i];
                   ==>
73               end
74             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T23,T14,T8
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1057	1057	0	0
gen_wmask[0].MaskCheck_A	388255766	14486864	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	14486864	0	0
T8	4134	150	0	0
T9	976	0	0	0
T13	2705	0	0	0
T14	144394	49248	0	0
T15	29510	100	0	0
T23	7299	1536	0	0
T27	225589	8900	0	0
T30	0	256	0	0
T31	0	64000	0	0
T39	0	4950	0	0
T40	0	6200	0	0
T51	162291	0	0	0
T54	5236	0	0	0
T64	2168	0	0	0
T98	0	2050	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

41                        logic unused_cfg;
42         0/1     ==>    assign unused_cfg = ^cfg_i;
43                      
44                        // Width of internal write mask. Note wmask_i input into the module is always assumed
45                        // to be the full bit mask
46                        localparam int MaskWidth = Width / DataBitsPerMask;
47                      
48                        logic [Width-1:0]     mem [Depth];
49                        logic [MaskWidth-1:0] wmask;
50                      
51                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
52         unreachable      assign wmask[k] = &wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
53                      
54                          // Ensure that all mask bits within a group have the same value for a write
55                          `ASSERT(MaskCheck_A, req_i && write_i |->
56                              wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
57                              clk_i, '0)
58                        end
59                      
60                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
61                        // thrown when using $readmemh system task to backdoor load an image
62                        always @(posedge clk_i) begin
63         1/1              if (req_i) begin
           Tests:       T1 T2 T3 
64         1/1                if (write_i) begin
           Tests:       T10 T39 T47 
65         1/1                  for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T10 T11 T131 
66         1/1                    if (wmask[i]) begin
           Tests:       T10 T11 T131 
67         1/1                      mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T10 T11 T131 
68                                    wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                                end
                   ==>  MISSING_ELSE
70                              end
71                            end else begin
72         1/1                  rdata_o <= mem[addr_i];
           Tests:       T10 T39 T47 
73                            end
74                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

63             if (req_i) begin
               -1-  
64               if (write_i) begin
                 -2-  
65                 for (int i=0; i < MaskWidth; i = i + 1) begin
                   ==>
66                   if (wmask[i]) begin
67                     mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
68                       wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                   end
70                 end
71               end else begin
72                 rdata_o <= mem[addr_i];
                   ==>
73               end
74             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T10,T11,T131
1	0	Covered	T10,T39,T47
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1057	1057	0	0
gen_wmask[0].MaskCheck_A	388255766	4615494	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	4615494	0	0
T82	1393	0	0	0
T123	851895	0	0	0
T131	96942	606	0	0
T132	0	786432	0	0
T133	0	655360	0	0
T134	0	606	0	0
T135	0	589824	0	0
T136	0	556	0	0
T137	0	606	0	0
T138	0	393216	0	0
T139	0	458752	0	0
T140	0	524288	0	0
T141	199656	0	0	0
T142	4219	0	0	0
T143	1553	0	0	0
T144	382353	0	0	0
T145	47606	0	0	0
T146	4370	0	0	0
T147	3903	0	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

41                        logic unused_cfg;
42         0/1     ==>    assign unused_cfg = ^cfg_i;
43                      
44                        // Width of internal write mask. Note wmask_i input into the module is always assumed
45                        // to be the full bit mask
46                        localparam int MaskWidth = Width / DataBitsPerMask;
47                      
48                        logic [Width-1:0]     mem [Depth];
49                        logic [MaskWidth-1:0] wmask;
50                      
51                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
52         unreachable      assign wmask[k] = &wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
53                      
54                          // Ensure that all mask bits within a group have the same value for a write
55                          `ASSERT(MaskCheck_A, req_i && write_i |->
56                              wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
57                              clk_i, '0)
58                        end
59                      
60                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
61                        // thrown when using $readmemh system task to backdoor load an image
62                        always @(posedge clk_i) begin
63         1/1              if (req_i) begin
           Tests:       T1 T2 T3 
64         1/1                if (write_i) begin
           Tests:       T20 T15 T10 
65         1/1                  for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T20 T15 T10 
66         1/1                    if (wmask[i]) begin
           Tests:       T20 T15 T10 
67         1/1                      mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T20 T15 T10 
68                                    wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                                end
                   ==>  MISSING_ELSE
70                              end
71                            end else begin
72         1/1                  rdata_o <= mem[addr_i];
           Tests:       T20 T15 T10 
73                            end
74                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

63             if (req_i) begin
               -1-  
64               if (write_i) begin
                 -2-  
65                 for (int i=0; i < MaskWidth; i = i + 1) begin
                   ==>
66                   if (wmask[i]) begin
67                     mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
68                       wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                   end
70                 end
71               end else begin
72                 rdata_o <= mem[addr_i];
                   ==>
73               end
74             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T20,T15,T10
1	0	Covered	T20,T15,T10
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1057	1057	0	0
gen_wmask[0].MaskCheck_A	388255766	4806666	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	4806666	0	0
T4	890	0	0	0
T7	972	0	0	0
T8	4134	0	0	0
T9	976	0	0	0
T13	2705	0	0	0
T14	144394	0	0	0
T15	29510	600	0	0
T20	1473	50	0	0
T21	0	100	0	0
T23	7299	0	0	0
T28	0	550	0	0
T29	0	10500	0	0
T40	0	1350	0	0
T48	0	150	0	0
T51	162291	0	0	0
T97	0	50	0	0
T148	0	1600	0	0
T149	0	256	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

41                        logic unused_cfg;
42         0/1     ==>    assign unused_cfg = ^cfg_i;
43                      
44                        // Width of internal write mask. Note wmask_i input into the module is always assumed
45                        // to be the full bit mask
46                        localparam int MaskWidth = Width / DataBitsPerMask;
47                      
48                        logic [Width-1:0]     mem [Depth];
49                        logic [MaskWidth-1:0] wmask;
50                      
51                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
52         unreachable      assign wmask[k] = &wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
53                      
54                          // Ensure that all mask bits within a group have the same value for a write
55                          `ASSERT(MaskCheck_A, req_i && write_i |->
56                              wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
57                              clk_i, '0)
58                        end
59                      
60                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
61                        // thrown when using $readmemh system task to backdoor load an image
62                        always @(posedge clk_i) begin
63         1/1              if (req_i) begin
           Tests:       T1 T2 T3 
64         1/1                if (write_i) begin
           Tests:       T1 T2 T18 
65         1/1                  for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T1 T23 T9 
66         1/1                    if (wmask[i]) begin
           Tests:       T1 T23 T9 
67         1/1                      mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T1 T23 T9 
68                                    wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                                end
                   ==>  MISSING_ELSE
70                              end
71                            end else begin
72         1/1                  rdata_o <= mem[addr_i];
           Tests:       T1 T2 T18 
73                            end
74                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

63             if (req_i) begin
               -1-  
64               if (write_i) begin
                 -2-  
65                 for (int i=0; i < MaskWidth; i = i + 1) begin
                   ==>
66                   if (wmask[i]) begin
67                     mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
68                       wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                   end
70                 end
71               end else begin
72                 rdata_o <= mem[addr_i];
                   ==>
73               end
74             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T23,T9
1	0	Covered	T1,T2,T18
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1057	1057	0	0
gen_wmask[0].MaskCheck_A	388255766	64470364	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	64470364	0	0
T1	3906	1950	0	0
T2	10848	0	0	0
T3	1224	0	0	0
T4	890	0	0	0
T7	972	0	0	0
T9	0	50	0	0
T12	2002	0	0	0
T17	1544	0	0	0
T18	1950	0	0	0
T19	2303	0	0	0
T20	1473	0	0	0
T23	0	256	0	0
T27	0	102450	0	0
T39	0	18850	0	0
T40	0	5400	0	0
T46	0	8842	0	0
T51	0	29718	0	0
T59	0	1400	0	0
T98	0	20000	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

41                        logic unused_cfg;
42         0/1     ==>    assign unused_cfg = ^cfg_i;
43                      
44                        // Width of internal write mask. Note wmask_i input into the module is always assumed
45                        // to be the full bit mask
46                        localparam int MaskWidth = Width / DataBitsPerMask;
47                      
48                        logic [Width-1:0]     mem [Depth];
49                        logic [MaskWidth-1:0] wmask;
50                      
51                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
52         unreachable      assign wmask[k] = &wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
53                      
54                          // Ensure that all mask bits within a group have the same value for a write
55                          `ASSERT(MaskCheck_A, req_i && write_i |->
56                              wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
57                              clk_i, '0)
58                        end
59                      
60                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
61                        // thrown when using $readmemh system task to backdoor load an image
62                        always @(posedge clk_i) begin
63         1/1              if (req_i) begin
           Tests:       T1 T2 T3 
64         1/1                if (write_i) begin
           Tests:       T23 T51 T10 
65         1/1                  for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T23 T51 T10 
66         1/1                    if (wmask[i]) begin
           Tests:       T23 T51 T10 
67         1/1                      mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T23 T51 T10 
68                                    wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                                end
                   ==>  MISSING_ELSE
70                              end
71                            end else begin
72         1/1                  rdata_o <= mem[addr_i];
           Tests:       T23 T51 T10 
73                            end
74                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

63             if (req_i) begin
               -1-  
64               if (write_i) begin
                 -2-  
65                 for (int i=0; i < MaskWidth; i = i + 1) begin
                   ==>
66                   if (wmask[i]) begin
67                     mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
68                       wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                   end
70                 end
71               end else begin
72                 rdata_o <= mem[addr_i];
                   ==>
73               end
74             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T23,T51,T10
1	0	Covered	T23,T51,T10
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1057	1057	0	0
gen_wmask[0].MaskCheck_A	388255766	6582803	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	6582803	0	0
T8	4134	0	0	0
T9	976	0	0	0
T13	2705	0	0	0
T14	144394	0	0	0
T15	29510	0	0	0
T23	7299	256	0	0
T27	225589	0	0	0
T31	0	13056	0	0
T42	0	50	0	0
T51	162291	506	0	0
T54	5236	0	0	0
T64	2168	0	0	0
T76	0	327	0	0
T149	0	256	0	0
T150	0	51500	0	0
T151	0	556	0	0
T152	0	100	0	0
T153	0	653824	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

41                        logic unused_cfg;
42         0/1     ==>    assign unused_cfg = ^cfg_i;
43                      
44                        // Width of internal write mask. Note wmask_i input into the module is always assumed
45                        // to be the full bit mask
46                        localparam int MaskWidth = Width / DataBitsPerMask;
47                      
48                        logic [Width-1:0]     mem [Depth];
49                        logic [MaskWidth-1:0] wmask;
50                      
51                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
52         unreachable      assign wmask[k] = &wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
53                      
54                          // Ensure that all mask bits within a group have the same value for a write
55                          `ASSERT(MaskCheck_A, req_i && write_i |->
56                              wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
57                              clk_i, '0)
58                        end
59                      
60                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
61                        // thrown when using $readmemh system task to backdoor load an image
62                        always @(posedge clk_i) begin
63         1/1              if (req_i) begin
           Tests:       T1 T2 T3 
64         1/1                if (write_i) begin
           Tests:       T10 T153 T154 
65         1/1                  for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T10 T153 T154 
66         1/1                    if (wmask[i]) begin
           Tests:       T10 T153 T154 
67         1/1                      mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T10 T153 T154 
68                                    wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                                end
                   ==>  MISSING_ELSE
70                              end
71                            end else begin
72         1/1                  rdata_o <= mem[addr_i];
           Tests:       T10 T154 T11 
73                            end
74                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

63             if (req_i) begin
               -1-  
64               if (write_i) begin
                 -2-  
65                 for (int i=0; i < MaskWidth; i = i + 1) begin
                   ==>
66                   if (wmask[i]) begin
67                     mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
68                       wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                   end
70                 end
71               end else begin
72                 rdata_o <= mem[addr_i];
                   ==>
73               end
74             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T10,T153,T154
1	0	Covered	T10,T154,T11
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1057	1057	0	0
gen_wmask[0].MaskCheck_A	388255766	5478750	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	5478750	0	0
T49	57491	0	0	0
T132	0	327680	0	0
T133	0	327936	0	0
T135	0	458752	0	0
T138	0	327680	0	0
T153	996931	589824	0	0
T154	0	606	0	0
T155	0	655360	0	0
T156	0	65536	0	0
T157	0	12800	0	0
T158	0	12800	0	0
T159	2180	0	0	0
T160	793374	0	0	0
T161	162098	0	0	0
T162	140191	0	0	0
T163	220462	0	0	0
T164	75394	0	0	0
T165	962715	0	0	0
T166	2217	0	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

41                        logic unused_cfg;
42         0/1     ==>    assign unused_cfg = ^cfg_i;
43                      
44                        // Width of internal write mask. Note wmask_i input into the module is always assumed
45                        // to be the full bit mask
46                        localparam int MaskWidth = Width / DataBitsPerMask;
47                      
48                        logic [Width-1:0]     mem [Depth];
49                        logic [MaskWidth-1:0] wmask;
50                      
51                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
52         unreachable      assign wmask[k] = &wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
53                      
54                          // Ensure that all mask bits within a group have the same value for a write
55                          `ASSERT(MaskCheck_A, req_i && write_i |->
56                              wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
57                              clk_i, '0)
58                        end
59                      
60                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
61                        // thrown when using $readmemh system task to backdoor load an image
62                        always @(posedge clk_i) begin
63         1/1              if (req_i) begin
           Tests:       T1 T2 T3 
64         1/1                if (write_i) begin
           Tests:       T10 T167 T153 
65         1/1                  for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T10 T153 T154 
66         1/1                    if (wmask[i]) begin
           Tests:       T10 T153 T154 
67         1/1                      mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T10 T153 T154 
68                                    wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                                end
                   ==>  MISSING_ELSE
70                              end
71                            end else begin
72         1/1                  rdata_o <= mem[addr_i];
           Tests:       T10 T167 T154 
73                            end
74                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

63             if (req_i) begin
               -1-  
64               if (write_i) begin
                 -2-  
65                 for (int i=0; i < MaskWidth; i = i + 1) begin
                   ==>
66                   if (wmask[i]) begin
67                     mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
68                       wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                   end
70                 end
71               end else begin
72                 rdata_o <= mem[addr_i];
                   ==>
73               end
74             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T10,T153,T154
1	0	Covered	T10,T167,T154
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1057	1057	0	0
gen_wmask[0].MaskCheck_A	388255766	5525048	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	5525048	0	0
T49	57491	0	0	0
T153	996931	589824	0	0
T154	0	606	0	0
T155	0	655360	0	0
T159	2180	0	0	0
T160	793374	0	0	0
T161	162098	0	0	0
T162	140191	0	0	0
T163	220462	0	0	0
T164	75394	0	0	0
T165	962715	0	0	0
T166	2217	0	0	0
T168	0	256	0	0
T169	0	250	0	0
T170	0	300	0	0
T171	0	700	0	0
T172	0	1350	0	0
T173	0	350	0	0
T174	0	300	0	0