Unified Coverage Report :: Module

Line Coverage for Module : prim_subreg

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00



55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T1 T2 T3 
65         1/1            assign qe = wr_en;
           Tests:       T1 T2 T3 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T1 T2 T3

Cond Coverage for Module : prim_subreg ( parameter DW=4,SwAccess=4,RESVAL=9,Mubi=1 + DW=4,SwAccess=0,RESVAL,Mubi )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_dis

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_0_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_0_rd_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_0_prog_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_0_erase_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_0_scramble_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_0_ecc_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_0_he_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_1_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_1_rd_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_1_prog_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_1_erase_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_1_scramble_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_1_ecc_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_1_he_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_2_en_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_2_rd_en_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_2_prog_en_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_2_erase_en_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_2_scramble_en_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_2_ecc_en_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_2_he_en_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_3_en_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_3_rd_en_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_3_prog_en_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_3_erase_en_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_3_scramble_en_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_3_ecc_en_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_3_he_en_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_4_en_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_4_rd_en_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_4_prog_en_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_4_erase_en_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_4_scramble_en_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_4_ecc_en_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_4_he_en_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_5_en_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_5_rd_en_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_5_prog_en_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_5_erase_en_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_5_scramble_en_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_5_ecc_en_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_5_he_en_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_6_en_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_6_rd_en_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_6_prog_en_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_6_erase_en_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_6_scramble_en_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_6_ecc_en_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_6_he_en_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_7_en_7

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_7_rd_en_7

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_7_prog_en_7

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_7_erase_en_7

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_7_scramble_en_7

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_7_ecc_en_7

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_cfg_7_he_en_7

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_default_region_rd_en

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_default_region_prog_en

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_default_region_erase_en

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_default_region_scramble_en

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_default_region_ecc_en

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_default_region_he_en

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_rd_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_prog_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_erase_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_scramble_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_ecc_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_he_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_rd_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_prog_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_erase_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_scramble_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_ecc_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_he_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_en_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_rd_en_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_prog_en_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_erase_en_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_scramble_en_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_ecc_en_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_he_en_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_en_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_rd_en_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_prog_en_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_erase_en_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_scramble_en_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_ecc_en_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_he_en_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_en_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_rd_en_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_prog_en_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_erase_en_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_scramble_en_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_ecc_en_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_he_en_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_en_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_rd_en_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_prog_en_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_erase_en_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_scramble_en_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_ecc_en_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_he_en_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_en_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_rd_en_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_prog_en_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_erase_en_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_scramble_en_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_ecc_en_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_he_en_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_en_7

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_rd_en_7

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_prog_en_7

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_erase_en_7

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_scramble_en_7

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_ecc_en_7

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_he_en_7

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_en_8

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_rd_en_8

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_prog_en_8

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_erase_en_8

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_scramble_en_8

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_ecc_en_8

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_he_en_8

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_en_9

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_rd_en_9

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_prog_en_9

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_erase_en_9

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_scramble_en_9

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_ecc_en_9

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_he_en_9

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info1_page_cfg_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info1_page_cfg_rd_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info1_page_cfg_prog_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info1_page_cfg_erase_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info1_page_cfg_scramble_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info1_page_cfg_ecc_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info1_page_cfg_he_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_rd_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_prog_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_erase_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_scramble_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_ecc_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_he_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_rd_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_prog_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_erase_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_scramble_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_ecc_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_he_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_rd_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_prog_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_erase_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_scramble_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_ecc_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_he_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_rd_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_prog_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_erase_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_scramble_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_ecc_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_he_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_en_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_rd_en_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_prog_en_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_erase_en_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_scramble_en_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_ecc_en_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_he_en_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_en_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_rd_en_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_prog_en_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_erase_en_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_scramble_en_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_ecc_en_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_he_en_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_en_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_rd_en_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_prog_en_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_erase_en_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_scramble_en_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_ecc_en_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_he_en_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_en_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_rd_en_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_prog_en_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_erase_en_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_scramble_en_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_ecc_en_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_he_en_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_en_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_rd_en_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_prog_en_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_erase_en_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_scramble_en_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_ecc_en_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_he_en_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_en_7

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_rd_en_7

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_prog_en_7

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_erase_en_7

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_scramble_en_7

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_ecc_en_7

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_he_en_7

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_en_8

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_rd_en_8

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_prog_en_8

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_erase_en_8

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_scramble_en_8

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_ecc_en_8

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_he_en_8

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_en_9

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_rd_en_9

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_prog_en_9

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_erase_en_9

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_scramble_en_9

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_ecc_en_9

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_he_en_9

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info1_page_cfg_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info1_page_cfg_rd_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info1_page_cfg_prog_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info1_page_cfg_erase_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info1_page_cfg_scramble_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info1_page_cfg_ecc_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info1_page_cfg_he_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_rd_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_prog_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_erase_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_scramble_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_ecc_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_he_en_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_rd_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_prog_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_erase_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_scramble_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_ecc_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_he_en_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_hw_info_cfg_override_scramble_dis

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_hw_info_cfg_override_ecc_dis

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field0

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Cond Coverage for Module : prim_subreg ( parameter DW=20,SwAccess=0,RESVAL=0,Mubi=0 + DW=20,SwAccess=1,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_addr

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr13_field0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_err_addr

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_ecc_single_err_addr_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_ecc_single_err_addr_1

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T17

Cond Coverage for Module : prim_subreg ( parameter DW=1,SwAccess=1,RESVAL,Mubi=0 + DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 + DW=1,SwAccess=4,RESVAL=0,Mubi=0 + DW=1,SwAccess=5,RESVAL,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
65.24	50.00

tb.dut.u_reg_core.u_intr_state_prog_empty

SCORE	COND
65.24	50.00

tb.dut.u_reg_core.u_intr_state_prog_lvl

SCORE	COND
65.24	50.00

tb.dut.u_reg_core.u_intr_state_rd_full

SCORE	COND
65.24	50.00

tb.dut.u_reg_core.u_intr_state_rd_lvl

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_status_rd_full

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_status_rd_empty

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_status_prog_full

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_status_prog_empty

SCORE	COND
65.24	50.00

tb.dut.u_reg_core.u_status_init_wip

SCORE	COND
65.24	50.00

tb.dut.u_reg_core.u_status_initialized

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_std_fault_status_reg_intg_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_std_fault_status_prog_intg_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_std_fault_status_lcmgr_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_std_fault_status_lcmgr_intg_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_std_fault_status_arb_fsm_err

SCORE	COND
65.24	50.00

tb.dut.u_reg_core.u_std_fault_status_storage_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_std_fault_status_phy_fsm_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_std_fault_status_ctrl_cnt_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_std_fault_status_fifo_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_fault_status_op_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_fault_status_mp_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_fault_status_rd_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_fault_status_prog_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_fault_status_prog_win_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_fault_status_prog_type_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_fault_status_seed_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_fault_status_spurious_ack

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_fault_status_arb_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_fault_status_host_gnt_err

SCORE	COND
65.24	50.00

tb.dut.u_reg_core.u_phy_status_init_wip

SCORE	COND
65.24	50.00

tb.dut.u_reg_core.u_phy_status_prog_normal_avail

SCORE	COND
65.24	50.00

tb.dut.u_reg_core.u_phy_status_prog_repair_avail

SCORE	COND
60.48	50.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_intr_state_op_done

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_intr_state_corr_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_err_code_op_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_err_code_mp_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_err_code_rd_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_err_code_prog_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_err_code_prog_win_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_err_code_prog_type_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_err_code_update_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_err_code_macro_err

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field0

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field1

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field2

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field4

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field5

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field6

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field0

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_intr_enable_prog_empty

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_intr_enable_prog_lvl

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_intr_enable_rd_full

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_intr_enable_rd_lvl

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_intr_enable_op_done

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_intr_enable_corr_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_control_start

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_control_prog_sel

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_control_erase_sel

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_control_partition_sel

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_erase_suspend

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.committed_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.staged_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.shadow_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.committed_reg

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_op_status_done

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_op_status_err

SCORE	COND
65.24	50.00

tb.dut.u_reg_core.u_phy_alert_cfg_alert_ack

SCORE	COND
65.24	50.00

tb.dut.u_reg_core.u_phy_alert_cfg_alert_trig

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_fifo_rst

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field3

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field7

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field7

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field8

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr13_field1

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr14_field1

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr15_field1

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr16_field1

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr17_field1

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr18

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr19

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_init

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_prog_type_en_normal

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_prog_type_en_repair

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_region_cfg_regwen_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_region_cfg_regwen_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_region_cfg_regwen_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_region_cfg_regwen_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_region_cfg_regwen_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_region_cfg_regwen_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_region_cfg_regwen_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_region_cfg_regwen_7

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_regwen_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_regwen_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_regwen_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_regwen_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_regwen_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_regwen_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_regwen_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_regwen_7

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_regwen_8

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info0_regwen_9

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info1_regwen

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info2_regwen_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank0_info2_regwen_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_regwen_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_regwen_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_regwen_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_regwen_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_regwen_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_regwen_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_regwen_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_regwen_7

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_regwen_8

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info0_regwen_9

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info1_regwen

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info2_regwen_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank1_info2_regwen_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_bank_cfg_regwen

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_fault_status_phy_relbl_err

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_fault_status_phy_storage_err

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr0_regwen

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Cond Coverage for Module : prim_subreg ( parameter DW=8,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_1

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr1_field0

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field2

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr14_field0

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr15_field0

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr16_field0

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr17_field0

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T39,T40

Cond Coverage for Module : prim_subreg ( parameter DW=32,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_exec

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_scratch

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr8

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr9

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr10

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr11

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T52,T53

Cond Coverage for Module : prim_subreg ( parameter DW=2,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_control_op

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_control_info_sel

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field9

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field4

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field5

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field6

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T17

Cond Coverage for Module : prim_subreg ( parameter DW=10,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_0_size_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_1_size_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_2_size_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_3_size_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_4_size_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_5_size_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_6_size_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_7_size_7

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr12

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Cond Coverage for Module : prim_subreg ( parameter DW=3,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field0

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field1

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field3

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T67,T69,T115

Cond Coverage for Module : prim_subreg ( parameter DW=12,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_control_num

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T17

Cond Coverage for Module : prim_subreg ( parameter DW=5,SwAccess=0,RESVAL,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_fifo_lvl_prog

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_fifo_lvl_rd

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr1_field1

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T27,T36,T37

Cond Coverage for Module : prim_subreg ( parameter DW=9,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_0_base_0

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_1_base_1

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_2_base_2

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_3_base_3

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_4_base_4

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_5_base_5

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_6_base_6

SCORE	COND
100.00	100.00

tb.dut.u_reg_core.u_mp_region_7_base_7

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2

SCORE	COND
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Branch Coverage for Module : prim_subreg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3