Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	22265412	1		T1	290		T2	58		T3	68
full_word	7542146	1		T1	238		T2	3		T3	58

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	29807278	1		T1	528		T2	61		T3	126
auto[TlIntgErrCmd]	97	1		T265	2		T266	3		T267	2
auto[TlIntgErrData]	95	1		T265	3		T266	1		T267	3
auto[TlIntgErrBoth]	88	1		T265	5		T266	6		T267	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	25466056	1		T1	422		T2	57		T3	85
auto[1]	4341502	1		T1	106		T2	4		T3	41

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	21572482	1		T1	268		T2	56		T3	62
auto[TlIntgErrNone]	partial	auto[1]	692674	1		T1	22		T2	2		T3	6
auto[TlIntgErrNone]	full_word	auto[0]	3893440	1		T1	154		T2	1		T3	23
auto[TlIntgErrNone]	full_word	auto[1]	3648682	1		T1	84		T2	2		T3	35
auto[TlIntgErrCmd]	partial	auto[0]	42	1		T265	1		T266	3		T267	1
auto[TlIntgErrCmd]	partial	auto[1]	45	1		T265	1		T267	1		T358	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T359	1		T369	1		T364	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T362	1		T359	1		T360	1
auto[TlIntgErrData]	partial	auto[0]	49	1		T265	2		T266	1		T267	3
auto[TlIntgErrData]	partial	auto[1]	39	1		T265	1		T358	1		T361	4
auto[TlIntgErrData]	full_word	auto[0]	4	1		T368	1		T363	1		T370	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T358	1		T364	1		T371	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T265	1		T266	1		T267	2
auto[TlIntgErrBoth]	partial	auto[1]	49	1		T265	4		T266	5		T267	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T364	1		T367	1		T275	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T361	1		T365	1		T370	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	22124	1		T117	634		T67	1281		T68	75
full_word	3664362	1		T2	10		T14	524		T16	50

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3686224	1		T2	10		T14	524		T16	50
auto[TlIntgErrCmd]	97	1		T265	6		T266	2		T267	6
auto[TlIntgErrData]	85	1		T265	2		T266	3		T267	2
auto[TlIntgErrBoth]	80	1		T265	2		T266	5		T267	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3658057	1		T2	10		T14	524		T16	50
auto[1]	28429	1		T117	669		T67	1625		T68	127

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1600	1		T117	75		T67	72		T68	2
auto[TlIntgErrNone]	partial	auto[1]	20281	1		T117	559		T67	1209		T68	73
auto[TlIntgErrNone]	full_word	auto[0]	3656349	1		T2	10		T14	524		T16	50
auto[TlIntgErrNone]	full_word	auto[1]	7994	1		T117	110		T67	416		T68	54
auto[TlIntgErrCmd]	partial	auto[0]	31	1		T265	2		T266	1		T267	2
auto[TlIntgErrCmd]	partial	auto[1]	60	1		T265	4		T267	4		T358	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T362	1		T370	2		T276	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T266	1		T360	1		-	-
auto[TlIntgErrData]	partial	auto[0]	36	1		T267	1		T358	1		T361	2
auto[TlIntgErrData]	partial	auto[1]	38	1		T265	2		T266	3		T358	1
auto[TlIntgErrData]	full_word	auto[0]	6	1		T267	1		T360	1		T364	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T361	1		T359	1		T369	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1		T266	2		T267	1		T358	1
auto[TlIntgErrBoth]	partial	auto[1]	48	1		T265	1		T266	3		T267	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T369	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1		T265	1		-	-		-	-