Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T3 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T14,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T14,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T26,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T14,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T16
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T26,T27
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T14,T16

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T14,T16

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1551823080	1548668532	0	0
CheckNGreaterZero_A	4224	4224	0	0
GntImpliesReady_A	1551823080	394295856	0	0
GntImpliesValid_A	1551823080	394295856	0	0
GrantKnown_A	1551823080	1548668532	0	0
IdxKnown_A	1551823080	1548668532	0	0
IndexIsCorrect_A	1551823080	394295856	0	0
NoReadyValidNoGrant_A	1551823080	174522749	0	0
Priority_A	1551823080	418098789	0	0
ReadyAndValidImplyGrant_A	1551823080	394295856	0	0
ReqAndReadyImplyGrant_A	1551823080	394295856	0	0
ReqImpliesValid_A	1551823080	418098789	0	0
ValidKnown_A	1551823080	1548668532	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1551823080	1548668532	0	0
T1	9544	9260	0	0
T2	6476	6256	0	0
T3	10496	10116	0	0
T7	14472	14256	0	0
T8	3032	2776	0	0
T14	229896	229548	0	0
T16	11112	10712	0	0
T18	5812	5520	0	0
T19	6368	5712	0	0
T20	7620	7364	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4224	4224	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T14	4	4	0	0
T16	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1551823080	394295856	0	0
T1	9544	356	0	0
T2	6476	84	0	0
T3	10496	1106	0	0
T7	14472	4444	0	0
T8	3032	196	0	0
T14	229896	2618	0	0
T15	0	17848	0	0
T16	11112	1640	0	0
T18	5812	356	0	0
T19	6368	132	0	0
T20	7620	356	0	0
T26	0	18	0	0
T27	0	1648	0	0
T28	0	170	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1551823080	394295856	0	0
T1	9544	356	0	0
T2	6476	84	0	0
T3	10496	1106	0	0
T7	14472	4444	0	0
T8	3032	196	0	0
T14	229896	2618	0	0
T15	0	17848	0	0
T16	11112	1640	0	0
T18	5812	356	0	0
T19	6368	132	0	0
T20	7620	356	0	0
T26	0	18	0	0
T27	0	1648	0	0
T28	0	170	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1551823080	1548668532	0	0
T1	9544	9260	0	0
T2	6476	6256	0	0
T3	10496	10116	0	0
T7	14472	14256	0	0
T8	3032	2776	0	0
T14	229896	229548	0	0
T16	11112	10712	0	0
T18	5812	5520	0	0
T19	6368	5712	0	0
T20	7620	7364	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1551823080	1548668532	0	0
T1	9544	9260	0	0
T2	6476	6256	0	0
T3	10496	10116	0	0
T7	14472	14256	0	0
T8	3032	2776	0	0
T14	229896	229548	0	0
T16	11112	10712	0	0
T18	5812	5520	0	0
T19	6368	5712	0	0
T20	7620	7364	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1551823080	394295856	0	0
T1	9544	356	0	0
T2	6476	84	0	0
T3	10496	1106	0	0
T7	14472	4444	0	0
T8	3032	196	0	0
T14	229896	2618	0	0
T15	0	17848	0	0
T16	11112	1640	0	0
T18	5812	356	0	0
T19	6368	132	0	0
T20	7620	356	0	0
T26	0	18	0	0
T27	0	1648	0	0
T28	0	170	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1551823080	174522749	0	0
T1	9544	696	0	0
T2	6476	286	0	0
T3	10496	316	0	0
T7	14472	256	0	0
T8	3032	256	0	0
T14	229896	4100	0	0
T15	0	72	0	0
T16	11112	388	0	0
T18	5812	986	0	0
T19	6368	512	0	0
T20	7620	992	0	0
T22	0	4152	0	0
T26	0	40	0	0
T27	0	210	0	0
T28	0	110	0	0
T59	0	2454	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1551823080	418098789	0	0
T1	9544	356	0	0
T2	6476	84	0	0
T3	10496	1106	0	0
T7	14472	4444	0	0
T8	3032	196	0	0
T14	229896	2618	0	0
T15	0	17848	0	0
T16	11112	1644	0	0
T18	5812	356	0	0
T19	6368	132	0	0
T20	7620	356	0	0
T26	0	18	0	0
T27	0	1648	0	0
T28	0	170	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1551823080	394295856	0	0
T1	9544	356	0	0
T2	6476	84	0	0
T3	10496	1106	0	0
T7	14472	4444	0	0
T8	3032	196	0	0
T14	229896	2618	0	0
T15	0	17848	0	0
T16	11112	1640	0	0
T18	5812	356	0	0
T19	6368	132	0	0
T20	7620	356	0	0
T26	0	18	0	0
T27	0	1648	0	0
T28	0	170	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1551823080	394295856	0	0
T1	9544	356	0	0
T2	6476	84	0	0
T3	10496	1106	0	0
T7	14472	4444	0	0
T8	3032	196	0	0
T14	229896	2618	0	0
T15	0	17848	0	0
T16	11112	1640	0	0
T18	5812	356	0	0
T19	6368	132	0	0
T20	7620	356	0	0
T26	0	18	0	0
T27	0	1648	0	0
T28	0	170	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1551823080	418098789	0	0
T1	9544	356	0	0
T2	6476	84	0	0
T3	10496	1106	0	0
T7	14472	4444	0	0
T8	3032	196	0	0
T14	229896	2618	0	0
T15	0	17848	0	0
T16	11112	1644	0	0
T18	5812	356	0	0
T19	6368	132	0	0
T20	7620	356	0	0
T26	0	18	0	0
T27	0	1648	0	0
T28	0	170	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1551823080	1548668532	0	0
T1	9544	9260	0	0
T2	6476	6256	0	0
T3	10496	10116	0	0
T7	14472	14256	0	0
T8	3032	2776	0	0
T14	229896	229548	0	0
T16	11112	10712	0	0
T18	5812	5520	0	0
T19	6368	5712	0	0
T20	7620	7364	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T3 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T14,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T14,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T26,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T14,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T16
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T26,T27
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T14,T16

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T14,T16

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	387955770	387167133	0	0
CheckNGreaterZero_A	1056	1056	0	0
GntImpliesReady_A	387955770	102790195	0	0
GntImpliesValid_A	387955770	102790195	0	0
GrantKnown_A	387955770	387167133	0	0
IdxKnown_A	387955770	387167133	0	0
IndexIsCorrect_A	387955770	102790195	0	0
NoReadyValidNoGrant_A	387955770	45604699	0	0
Priority_A	387955770	108893154	0	0
ReadyAndValidImplyGrant_A	387955770	102790195	0	0
ReqAndReadyImplyGrant_A	387955770	102790195	0	0
ReqImpliesValid_A	387955770	108893154	0	0
ValidKnown_A	387955770	387167133	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	387167133	0	0
T1	2386	2315	0	0
T2	1619	1564	0	0
T3	2624	2529	0	0
T7	3618	3564	0	0
T8	758	694	0	0
T14	57474	57387	0	0
T16	2778	2678	0	0
T18	1453	1380	0	0
T19	1592	1428	0	0
T20	1905	1841	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1056	1056	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	102790195	0	0
T1	2386	32	0	0
T2	1619	42	0	0
T3	2624	553	0	0
T7	3618	32	0	0
T8	758	98	0	0
T14	57474	703	0	0
T16	2778	820	0	0
T18	1453	32	0	0
T19	1592	64	0	0
T20	1905	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	102790195	0	0
T1	2386	32	0	0
T2	1619	42	0	0
T3	2624	553	0	0
T7	3618	32	0	0
T8	758	98	0	0
T14	57474	703	0	0
T16	2778	820	0	0
T18	1453	32	0	0
T19	1592	64	0	0
T20	1905	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	387167133	0	0
T1	2386	2315	0	0
T2	1619	1564	0	0
T3	2624	2529	0	0
T7	3618	3564	0	0
T8	758	694	0	0
T14	57474	57387	0	0
T16	2778	2678	0	0
T18	1453	1380	0	0
T19	1592	1428	0	0
T20	1905	1841	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	387167133	0	0
T1	2386	2315	0	0
T2	1619	1564	0	0
T3	2624	2529	0	0
T7	3618	3564	0	0
T8	758	694	0	0
T14	57474	57387	0	0
T16	2778	2678	0	0
T18	1453	1380	0	0
T19	1592	1428	0	0
T20	1905	1841	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	102790195	0	0
T1	2386	32	0	0
T2	1619	42	0	0
T3	2624	553	0	0
T7	3618	32	0	0
T8	758	98	0	0
T14	57474	703	0	0
T16	2778	820	0	0
T18	1453	32	0	0
T19	1592	64	0	0
T20	1905	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	45604699	0	0
T1	2386	128	0	0
T2	1619	143	0	0
T3	2624	158	0	0
T7	3618	128	0	0
T8	758	128	0	0
T14	57474	1136	0	0
T16	2778	194	0	0
T18	1453	128	0	0
T19	1592	256	0	0
T20	1905	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	108893154	0	0
T1	2386	32	0	0
T2	1619	42	0	0
T3	2624	553	0	0
T7	3618	32	0	0
T8	758	98	0	0
T14	57474	703	0	0
T16	2778	822	0	0
T18	1453	32	0	0
T19	1592	64	0	0
T20	1905	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	102790195	0	0
T1	2386	32	0	0
T2	1619	42	0	0
T3	2624	553	0	0
T7	3618	32	0	0
T8	758	98	0	0
T14	57474	703	0	0
T16	2778	820	0	0
T18	1453	32	0	0
T19	1592	64	0	0
T20	1905	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	102790195	0	0
T1	2386	32	0	0
T2	1619	42	0	0
T3	2624	553	0	0
T7	3618	32	0	0
T8	758	98	0	0
T14	57474	703	0	0
T16	2778	820	0	0
T18	1453	32	0	0
T19	1592	64	0	0
T20	1905	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	108893154	0	0
T1	2386	32	0	0
T2	1619	42	0	0
T3	2624	553	0	0
T7	3618	32	0	0
T8	758	98	0	0
T14	57474	703	0	0
T16	2778	822	0	0
T18	1453	32	0	0
T19	1592	64	0	0
T20	1905	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	387167133	0	0
T1	2386	2315	0	0
T2	1619	1564	0	0
T3	2624	2529	0	0
T7	3618	3564	0	0
T8	758	694	0	0
T14	57474	57387	0	0
T16	2778	2678	0	0
T18	1453	1380	0	0
T19	1592	1428	0	0
T20	1905	1841	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T3 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T14,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T14,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T26,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T14,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T16
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T26,T27
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T14,T16

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T14,T16

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	387955770	387167133	0	0
CheckNGreaterZero_A	1056	1056	0	0
GntImpliesReady_A	387955770	102790090	0	0
GntImpliesValid_A	387955770	102790090	0	0
GrantKnown_A	387955770	387167133	0	0
IdxKnown_A	387955770	387167133	0	0
IndexIsCorrect_A	387955770	102790090	0	0
NoReadyValidNoGrant_A	387955770	45604724	0	0
Priority_A	387955770	108893024	0	0
ReadyAndValidImplyGrant_A	387955770	102790090	0	0
ReqAndReadyImplyGrant_A	387955770	102790090	0	0
ReqImpliesValid_A	387955770	108893024	0	0
ValidKnown_A	387955770	387167133	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	387167133	0	0
T1	2386	2315	0	0
T2	1619	1564	0	0
T3	2624	2529	0	0
T7	3618	3564	0	0
T8	758	694	0	0
T14	57474	57387	0	0
T16	2778	2678	0	0
T18	1453	1380	0	0
T19	1592	1428	0	0
T20	1905	1841	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1056	1056	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	102790090	0	0
T1	2386	32	0	0
T2	1619	42	0	0
T3	2624	553	0	0
T7	3618	32	0	0
T8	758	98	0	0
T14	57474	703	0	0
T16	2778	820	0	0
T18	1453	32	0	0
T19	1592	64	0	0
T20	1905	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	102790090	0	0
T1	2386	32	0	0
T2	1619	42	0	0
T3	2624	553	0	0
T7	3618	32	0	0
T8	758	98	0	0
T14	57474	703	0	0
T16	2778	820	0	0
T18	1453	32	0	0
T19	1592	64	0	0
T20	1905	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	387167133	0	0
T1	2386	2315	0	0
T2	1619	1564	0	0
T3	2624	2529	0	0
T7	3618	3564	0	0
T8	758	694	0	0
T14	57474	57387	0	0
T16	2778	2678	0	0
T18	1453	1380	0	0
T19	1592	1428	0	0
T20	1905	1841	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	387167133	0	0
T1	2386	2315	0	0
T2	1619	1564	0	0
T3	2624	2529	0	0
T7	3618	3564	0	0
T8	758	694	0	0
T14	57474	57387	0	0
T16	2778	2678	0	0
T18	1453	1380	0	0
T19	1592	1428	0	0
T20	1905	1841	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	102790090	0	0
T1	2386	32	0	0
T2	1619	42	0	0
T3	2624	553	0	0
T7	3618	32	0	0
T8	758	98	0	0
T14	57474	703	0	0
T16	2778	820	0	0
T18	1453	32	0	0
T19	1592	64	0	0
T20	1905	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	45604724	0	0
T1	2386	128	0	0
T2	1619	143	0	0
T3	2624	158	0	0
T7	3618	128	0	0
T8	758	128	0	0
T14	57474	1136	0	0
T16	2778	194	0	0
T18	1453	128	0	0
T19	1592	256	0	0
T20	1905	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	108893024	0	0
T1	2386	32	0	0
T2	1619	42	0	0
T3	2624	553	0	0
T7	3618	32	0	0
T8	758	98	0	0
T14	57474	703	0	0
T16	2778	822	0	0
T18	1453	32	0	0
T19	1592	64	0	0
T20	1905	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	102790090	0	0
T1	2386	32	0	0
T2	1619	42	0	0
T3	2624	553	0	0
T7	3618	32	0	0
T8	758	98	0	0
T14	57474	703	0	0
T16	2778	820	0	0
T18	1453	32	0	0
T19	1592	64	0	0
T20	1905	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	102790090	0	0
T1	2386	32	0	0
T2	1619	42	0	0
T3	2624	553	0	0
T7	3618	32	0	0
T8	758	98	0	0
T14	57474	703	0	0
T16	2778	820	0	0
T18	1453	32	0	0
T19	1592	64	0	0
T20	1905	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	108893024	0	0
T1	2386	32	0	0
T2	1619	42	0	0
T3	2624	553	0	0
T7	3618	32	0	0
T8	758	98	0	0
T14	57474	703	0	0
T16	2778	822	0	0
T18	1453	32	0	0
T19	1592	64	0	0
T20	1905	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	387167133	0	0
T1	2386	2315	0	0
T2	1619	1564	0	0
T3	2624	2529	0	0
T7	3618	3564	0	0
T8	758	694	0	0
T14	57474	57387	0	0
T16	2778	2678	0	0
T18	1453	1380	0	0
T19	1592	1428	0	0
T20	1905	1841	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T3 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T18
1	0	Covered	T14,T26,T27

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T14,T26,T27
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T14,T26,T27
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T26,T27,T28
1	0	Covered	T1,T7,T18
1	1	Covered	T14,T26,T27

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T26,T27
1	1	Covered	T1,T7,T18

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T1,T7,T18

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T26,T27

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T26,T27

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	387955770	387167133	0	0
CheckNGreaterZero_A	1056	1056	0	0
GntImpliesReady_A	387955770	94357850	0	0
GntImpliesValid_A	387955770	94357850	0	0
GrantKnown_A	387955770	387167133	0	0
IdxKnown_A	387955770	387167133	0	0
IndexIsCorrect_A	387955770	94357850	0	0
NoReadyValidNoGrant_A	387955770	41656663	0	0
Priority_A	387955770	100156370	0	0
ReadyAndValidImplyGrant_A	387955770	94357850	0	0
ReqAndReadyImplyGrant_A	387955770	94357850	0	0
ReqImpliesValid_A	387955770	100156370	0	0
ValidKnown_A	387955770	387167133	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	387167133	0	0
T1	2386	2315	0	0
T2	1619	1564	0	0
T3	2624	2529	0	0
T7	3618	3564	0	0
T8	758	694	0	0
T14	57474	57387	0	0
T16	2778	2678	0	0
T18	1453	1380	0	0
T19	1592	1428	0	0
T20	1905	1841	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1056	1056	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	94357850	0	0
T1	2386	146	0	0
T2	1619	0	0	0
T3	2624	0	0	0
T7	3618	2190	0	0
T8	758	0	0	0
T14	57474	606	0	0
T15	0	8924	0	0
T16	2778	0	0	0
T18	1453	146	0	0
T19	1592	2	0	0
T20	1905	146	0	0
T26	0	9	0	0
T27	0	824	0	0
T28	0	85	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	94357850	0	0
T1	2386	146	0	0
T2	1619	0	0	0
T3	2624	0	0	0
T7	3618	2190	0	0
T8	758	0	0	0
T14	57474	606	0	0
T15	0	8924	0	0
T16	2778	0	0	0
T18	1453	146	0	0
T19	1592	2	0	0
T20	1905	146	0	0
T26	0	9	0	0
T27	0	824	0	0
T28	0	85	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	387167133	0	0
T1	2386	2315	0	0
T2	1619	1564	0	0
T3	2624	2529	0	0
T7	3618	3564	0	0
T8	758	694	0	0
T14	57474	57387	0	0
T16	2778	2678	0	0
T18	1453	1380	0	0
T19	1592	1428	0	0
T20	1905	1841	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	387167133	0	0
T1	2386	2315	0	0
T2	1619	1564	0	0
T3	2624	2529	0	0
T7	3618	3564	0	0
T8	758	694	0	0
T14	57474	57387	0	0
T16	2778	2678	0	0
T18	1453	1380	0	0
T19	1592	1428	0	0
T20	1905	1841	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	94357850	0	0
T1	2386	146	0	0
T2	1619	0	0	0
T3	2624	0	0	0
T7	3618	2190	0	0
T8	758	0	0	0
T14	57474	606	0	0
T15	0	8924	0	0
T16	2778	0	0	0
T18	1453	146	0	0
T19	1592	2	0	0
T20	1905	146	0	0
T26	0	9	0	0
T27	0	824	0	0
T28	0	85	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	41656663	0	0
T1	2386	220	0	0
T2	1619	0	0	0
T3	2624	0	0	0
T7	3618	0	0	0
T8	758	0	0	0
T14	57474	914	0	0
T15	0	36	0	0
T16	2778	0	0	0
T18	1453	365	0	0
T19	1592	0	0	0
T20	1905	368	0	0
T22	0	2076	0	0
T26	0	20	0	0
T27	0	105	0	0
T28	0	55	0	0
T59	0	1227	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	100156370	0	0
T1	2386	146	0	0
T2	1619	0	0	0
T3	2624	0	0	0
T7	3618	2190	0	0
T8	758	0	0	0
T14	57474	606	0	0
T15	0	8924	0	0
T16	2778	0	0	0
T18	1453	146	0	0
T19	1592	2	0	0
T20	1905	146	0	0
T26	0	9	0	0
T27	0	824	0	0
T28	0	85	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	94357850	0	0
T1	2386	146	0	0
T2	1619	0	0	0
T3	2624	0	0	0
T7	3618	2190	0	0
T8	758	0	0	0
T14	57474	606	0	0
T15	0	8924	0	0
T16	2778	0	0	0
T18	1453	146	0	0
T19	1592	2	0	0
T20	1905	146	0	0
T26	0	9	0	0
T27	0	824	0	0
T28	0	85	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	94357850	0	0
T1	2386	146	0	0
T2	1619	0	0	0
T3	2624	0	0	0
T7	3618	2190	0	0
T8	758	0	0	0
T14	57474	606	0	0
T15	0	8924	0	0
T16	2778	0	0	0
T18	1453	146	0	0
T19	1592	2	0	0
T20	1905	146	0	0
T26	0	9	0	0
T27	0	824	0	0
T28	0	85	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	100156370	0	0
T1	2386	146	0	0
T2	1619	0	0	0
T3	2624	0	0	0
T7	3618	2190	0	0
T8	758	0	0	0
T14	57474	606	0	0
T15	0	8924	0	0
T16	2778	0	0	0
T18	1453	146	0	0
T19	1592	2	0	0
T20	1905	146	0	0
T26	0	9	0	0
T27	0	824	0	0
T28	0	85	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	387167133	0	0
T1	2386	2315	0	0
T2	1619	1564	0	0
T3	2624	2529	0	0
T7	3618	3564	0	0
T8	758	694	0	0
T14	57474	57387	0	0
T16	2778	2678	0	0
T18	1453	1380	0	0
T19	1592	1428	0	0
T20	1905	1841	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T3 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T18
1	0	Covered	T14,T26,T27

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T14,T26,T27
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T14,T26,T27
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T26,T27,T28
1	0	Covered	T1,T7,T18
1	1	Covered	T14,T26,T27

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T26,T27
1	1	Covered	T1,T7,T18

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T27,T28
1	1	Covered	T1,T7,T18

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T26,T27

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T26,T27

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	387955770	387167133	0	0
CheckNGreaterZero_A	1056	1056	0	0
GntImpliesReady_A	387955770	94357721	0	0
GntImpliesValid_A	387955770	94357721	0	0
GrantKnown_A	387955770	387167133	0	0
IdxKnown_A	387955770	387167133	0	0
IndexIsCorrect_A	387955770	94357721	0	0
NoReadyValidNoGrant_A	387955770	41656663	0	0
Priority_A	387955770	100156241	0	0
ReadyAndValidImplyGrant_A	387955770	94357721	0	0
ReqAndReadyImplyGrant_A	387955770	94357721	0	0
ReqImpliesValid_A	387955770	100156241	0	0
ValidKnown_A	387955770	387167133	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	387167133	0	0
T1	2386	2315	0	0
T2	1619	1564	0	0
T3	2624	2529	0	0
T7	3618	3564	0	0
T8	758	694	0	0
T14	57474	57387	0	0
T16	2778	2678	0	0
T18	1453	1380	0	0
T19	1592	1428	0	0
T20	1905	1841	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1056	1056	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	94357721	0	0
T1	2386	146	0	0
T2	1619	0	0	0
T3	2624	0	0	0
T7	3618	2190	0	0
T8	758	0	0	0
T14	57474	606	0	0
T15	0	8924	0	0
T16	2778	0	0	0
T18	1453	146	0	0
T19	1592	2	0	0
T20	1905	146	0	0
T26	0	9	0	0
T27	0	824	0	0
T28	0	85	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	94357721	0	0
T1	2386	146	0	0
T2	1619	0	0	0
T3	2624	0	0	0
T7	3618	2190	0	0
T8	758	0	0	0
T14	57474	606	0	0
T15	0	8924	0	0
T16	2778	0	0	0
T18	1453	146	0	0
T19	1592	2	0	0
T20	1905	146	0	0
T26	0	9	0	0
T27	0	824	0	0
T28	0	85	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	387167133	0	0
T1	2386	2315	0	0
T2	1619	1564	0	0
T3	2624	2529	0	0
T7	3618	3564	0	0
T8	758	694	0	0
T14	57474	57387	0	0
T16	2778	2678	0	0
T18	1453	1380	0	0
T19	1592	1428	0	0
T20	1905	1841	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	387167133	0	0
T1	2386	2315	0	0
T2	1619	1564	0	0
T3	2624	2529	0	0
T7	3618	3564	0	0
T8	758	694	0	0
T14	57474	57387	0	0
T16	2778	2678	0	0
T18	1453	1380	0	0
T19	1592	1428	0	0
T20	1905	1841	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	94357721	0	0
T1	2386	146	0	0
T2	1619	0	0	0
T3	2624	0	0	0
T7	3618	2190	0	0
T8	758	0	0	0
T14	57474	606	0	0
T15	0	8924	0	0
T16	2778	0	0	0
T18	1453	146	0	0
T19	1592	2	0	0
T20	1905	146	0	0
T26	0	9	0	0
T27	0	824	0	0
T28	0	85	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	41656663	0	0
T1	2386	220	0	0
T2	1619	0	0	0
T3	2624	0	0	0
T7	3618	0	0	0
T8	758	0	0	0
T14	57474	914	0	0
T15	0	36	0	0
T16	2778	0	0	0
T18	1453	365	0	0
T19	1592	0	0	0
T20	1905	368	0	0
T22	0	2076	0	0
T26	0	20	0	0
T27	0	105	0	0
T28	0	55	0	0
T59	0	1227	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	100156241	0	0
T1	2386	146	0	0
T2	1619	0	0	0
T3	2624	0	0	0
T7	3618	2190	0	0
T8	758	0	0	0
T14	57474	606	0	0
T15	0	8924	0	0
T16	2778	0	0	0
T18	1453	146	0	0
T19	1592	2	0	0
T20	1905	146	0	0
T26	0	9	0	0
T27	0	824	0	0
T28	0	85	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	94357721	0	0
T1	2386	146	0	0
T2	1619	0	0	0
T3	2624	0	0	0
T7	3618	2190	0	0
T8	758	0	0	0
T14	57474	606	0	0
T15	0	8924	0	0
T16	2778	0	0	0
T18	1453	146	0	0
T19	1592	2	0	0
T20	1905	146	0	0
T26	0	9	0	0
T27	0	824	0	0
T28	0	85	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	94357721	0	0
T1	2386	146	0	0
T2	1619	0	0	0
T3	2624	0	0	0
T7	3618	2190	0	0
T8	758	0	0	0
T14	57474	606	0	0
T15	0	8924	0	0
T16	2778	0	0	0
T18	1453	146	0	0
T19	1592	2	0	0
T20	1905	146	0	0
T26	0	9	0	0
T27	0	824	0	0
T28	0	85	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	100156241	0	0
T1	2386	146	0	0
T2	1619	0	0	0
T3	2624	0	0	0
T7	3618	2190	0	0
T8	758	0	0	0
T14	57474	606	0	0
T15	0	8924	0	0
T16	2778	0	0	0
T18	1453	146	0	0
T19	1592	2	0	0
T20	1905	146	0	0
T26	0	9	0	0
T27	0	824	0	0
T28	0	85	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	387167133	0	0
T1	2386	2315	0	0
T2	1619	1564	0	0
T3	2624	2529	0	0
T7	3618	3564	0	0
T8	758	694	0	0
T14	57474	57387	0	0
T16	2778	2678	0	0
T18	1453	1380	0	0
T19	1592	1428	0	0
T20	1905	1841	0	0