Unified Coverage Report :: Module :: flash_phy_rd_buffers

Module : flash_phy_rd_buffers

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.71	100.00	90.83			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.71	100.00	90.83			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.71	100.00	90.83			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.71	100.00	90.83			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.54	100.00	90.17			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.54	100.00	90.17			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.54	100.00	90.17			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.54	100.00	90.17			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : flash_phy_rd_buffers

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T11 T84 T12 
47         1/1                out_o.err <= '0;
           Tests:       T11 T84 T12 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T3 T16 T15 
50         1/1                out_o.err <= '0;
           Tests:       T3 T16 T15 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T1 T2 T3 
53         1/1                out_o.part <= part_i;
           Tests:       T1 T2 T3 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T1 T2 T3 
55         1/1                out_o.attr <= Wip;
           Tests:       T1 T2 T3 
56         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T1 T2 T3 
59         1/1                out_o.attr <= Valid;
           Tests:       T1 T2 T3 
60         1/1                out_o.err <= err_i;
           Tests:       T1 T2 T3 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Module : flash_phy_rd_buffers

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T84,T85,T86

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T16,T26

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : flash_phy_rd_buffers

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T11,T84,T12
0	0	1	-	-	Covered	T3,T16,T15
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd_buffers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	2147483647	4983865	0	0
UpdateCheck_A	2147483647	4983850	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4983865	0	0
T1	9544	74	0	0
T2	12952	5	0	0
T3	20992	10	0	0
T7	28944	0	0	0
T8	6064	0	0	0
T14	459792	688	0	0
T15	328748	42	0	0
T16	22224	39	0	0
T18	11624	73	0	0
T19	12736	0	0	0
T20	15240	74	0	0
T22	0	1222	0	0
T26	0	37	0	0
T27	0	112	0	0
T28	0	64	0	0
T59	0	899	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4983850	0	0
T1	9544	74	0	0
T2	12952	5	0	0
T3	20992	10	0	0
T7	28944	0	0	0
T8	6064	0	0	0
T14	459792	688	0	0
T15	328748	42	0	0
T16	22224	39	0	0
T18	11624	73	0	0
T19	12736	0	0	0
T20	15240	74	0	0
T22	0	1222	0	0
T26	0	37	0	0
T27	0	112	0	0
T28	0	64	0	0
T59	0	899	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T11 T84 T12 
47         1/1                out_o.err <= '0;
           Tests:       T11 T84 T12 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T3 T16 T27 
50         1/1                out_o.err <= '0;
           Tests:       T3 T16 T27 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T2 T3 T14 
53         1/1                out_o.part <= part_i;
           Tests:       T2 T3 T14 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T2 T3 T14 
55         1/1                out_o.attr <= Wip;
           Tests:       T2 T3 T14 
56         1/1                out_o.err <= '0;
           Tests:       T2 T3 T14 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T2 T3 T14 
59         1/1                out_o.attr <= Valid;
           Tests:       T2 T3 T14 
60         1/1                out_o.err <= err_i;
           Tests:       T2 T3 T14 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T84,T85,T86

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T14

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T16,T27

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T14

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T11,T84,T12
0	0	1	-	-	Covered	T3,T16,T27
0	0	0	1	-	Covered	T2,T3,T14
0	0	0	0	1	Covered	T2,T3,T14
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	387955770	671834	0	0
UpdateCheck_A	387955770	671832	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	671834	0	0
T2	1619	2	0	0
T3	2624	3	0	0
T7	3618	0	0	0
T8	758	0	0	0
T14	57474	91	0	0
T15	82187	6	0	0
T16	2778	10	0	0
T18	1453	0	0	0
T19	1592	0	0	0
T20	1905	0	0	0
T22	0	135	0	0
T26	0	7	0	0
T27	0	22	0	0
T28	0	14	0	0
T59	0	123	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	671832	0	0
T2	1619	2	0	0
T3	2624	3	0	0
T7	3618	0	0	0
T8	758	0	0	0
T14	57474	91	0	0
T15	82187	6	0	0
T16	2778	10	0	0
T18	1453	0	0	0
T19	1592	0	0	0
T20	1905	0	0	0
T22	0	135	0	0
T26	0	7	0	0
T27	0	22	0	0
T28	0	14	0	0
T59	0	123	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T11 T84 T12 
47         1/1                out_o.err <= '0;
           Tests:       T11 T84 T12 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T3 T16 T27 
50         1/1                out_o.err <= '0;
           Tests:       T3 T16 T27 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T2 T3 T14 
53         1/1                out_o.part <= part_i;
           Tests:       T2 T3 T14 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T2 T3 T14 
55         1/1                out_o.attr <= Wip;
           Tests:       T2 T3 T14 
56         1/1                out_o.err <= '0;
           Tests:       T2 T3 T14 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T2 T3 T14 
59         1/1                out_o.attr <= Valid;
           Tests:       T2 T3 T14 
60         1/1                out_o.err <= err_i;
           Tests:       T2 T3 T14 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T84,T85,T86

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T14

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T16,T27

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T14

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T11,T84,T12
0	0	1	-	-	Covered	T3,T16,T27
0	0	0	1	-	Covered	T2,T3,T14
0	0	0	0	1	Covered	T2,T3,T14
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	387955770	671448	0	0
UpdateCheck_A	387955770	671447	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	671448	0	0
T2	1619	1	0	0
T3	2624	3	0	0
T7	3618	0	0	0
T8	758	0	0	0
T14	57474	91	0	0
T15	82187	6	0	0
T16	2778	10	0	0
T18	1453	0	0	0
T19	1592	0	0	0
T20	1905	0	0	0
T22	0	134	0	0
T26	0	7	0	0
T27	0	23	0	0
T28	0	13	0	0
T59	0	122	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	671447	0	0
T2	1619	1	0	0
T3	2624	3	0	0
T7	3618	0	0	0
T8	758	0	0	0
T14	57474	91	0	0
T15	82187	6	0	0
T16	2778	10	0	0
T18	1453	0	0	0
T19	1592	0	0	0
T20	1905	0	0	0
T22	0	134	0	0
T26	0	7	0	0
T27	0	23	0	0
T28	0	13	0	0
T59	0	122	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T11 T12 T85 
47         1/1                out_o.err <= '0;
           Tests:       T11 T12 T85 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T3 T16 T26 
50         1/1                out_o.err <= '0;
           Tests:       T3 T16 T26 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T2 T3 T14 
53         1/1                out_o.part <= part_i;
           Tests:       T2 T3 T14 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T2 T3 T14 
55         1/1                out_o.attr <= Wip;
           Tests:       T2 T3 T14 
56         1/1                out_o.err <= '0;
           Tests:       T2 T3 T14 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T2 T3 T14 
59         1/1                out_o.attr <= Valid;
           Tests:       T2 T3 T14 
60         1/1                out_o.err <= err_i;
           Tests:       T2 T3 T14 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T85,T86,T87

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T14

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T16,T26

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T14

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T11,T12,T85
0	0	1	-	-	Covered	T3,T16,T26
0	0	0	1	-	Covered	T2,T3,T14
0	0	0	0	1	Covered	T2,T3,T14
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	387955770	671498	0	0
UpdateCheck_A	387955770	671497	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	671498	0	0
T2	1619	1	0	0
T3	2624	2	0	0
T7	3618	0	0	0
T8	758	0	0	0
T14	57474	90	0	0
T15	82187	6	0	0
T16	2778	10	0	0
T18	1453	0	0	0
T19	1592	0	0	0
T20	1905	0	0	0
T22	0	134	0	0
T26	0	8	0	0
T27	0	22	0	0
T28	0	12	0	0
T59	0	122	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	671497	0	0
T2	1619	1	0	0
T3	2624	2	0	0
T7	3618	0	0	0
T8	758	0	0	0
T14	57474	90	0	0
T15	82187	6	0	0
T16	2778	10	0	0
T18	1453	0	0	0
T19	1592	0	0	0
T20	1905	0	0	0
T22	0	134	0	0
T26	0	8	0	0
T27	0	22	0	0
T28	0	12	0	0
T59	0	122	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T11 T12 T85 
47         1/1                out_o.err <= '0;
           Tests:       T11 T12 T85 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T3 T16 T28 
50         1/1                out_o.err <= '0;
           Tests:       T3 T16 T28 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T2 T3 T14 
53         1/1                out_o.part <= part_i;
           Tests:       T2 T3 T14 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T2 T3 T14 
55         1/1                out_o.attr <= Wip;
           Tests:       T2 T3 T14 
56         1/1                out_o.err <= '0;
           Tests:       T2 T3 T14 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T2 T3 T14 
59         1/1                out_o.attr <= Valid;
           Tests:       T2 T3 T14 
60         1/1                out_o.err <= err_i;
           Tests:       T2 T3 T14 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T85,T86,T87

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T14

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T16,T28

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T14

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T11,T12,T85
0	0	1	-	-	Covered	T3,T16,T28
0	0	0	1	-	Covered	T2,T3,T14
0	0	0	0	1	Covered	T2,T3,T14
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	387955770	671185	0	0
UpdateCheck_A	387955770	671183	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	671185	0	0
T2	1619	1	0	0
T3	2624	2	0	0
T7	3618	0	0	0
T8	758	0	0	0
T14	57474	90	0	0
T15	82187	6	0	0
T16	2778	9	0	0
T18	1453	0	0	0
T19	1592	0	0	0
T20	1905	0	0	0
T22	0	127	0	0
T26	0	6	0	0
T27	0	20	0	0
T28	0	13	0	0
T59	0	122	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	671183	0	0
T2	1619	1	0	0
T3	2624	2	0	0
T7	3618	0	0	0
T8	758	0	0	0
T14	57474	90	0	0
T15	82187	6	0	0
T16	2778	9	0	0
T18	1453	0	0	0
T19	1592	0	0	0
T20	1905	0	0	0
T22	0	127	0	0
T26	0	6	0	0
T27	0	20	0	0
T28	0	13	0	0
T59	0	122	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T11 T12 T85 
47         1/1                out_o.err <= '0;
           Tests:       T11 T12 T85 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T27 T22 T11 
50         1/1                out_o.err <= '0;
           Tests:       T27 T22 T11 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T1 T18 T14 
53         1/1                out_o.part <= part_i;
           Tests:       T1 T18 T14 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T1 T18 T14 
55         1/1                out_o.attr <= Wip;
           Tests:       T1 T18 T14 
56         1/1                out_o.err <= '0;
           Tests:       T1 T18 T14 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T1 T18 T14 
59         1/1                out_o.attr <= Valid;
           Tests:       T1 T18 T14 
60         1/1                out_o.err <= err_i;
           Tests:       T1 T18 T14 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T85,T86,T88

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T14

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27,T22,T89

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T18,T14

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T18,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T11,T12,T85
0	0	1	-	-	Covered	T27,T22,T11
0	0	0	1	-	Covered	T1,T18,T14
0	0	0	0	1	Covered	T1,T18,T14
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	387955770	574972	0	0
UpdateCheck_A	387955770	574969	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	574972	0	0
T1	2386	19	0	0
T2	1619	0	0	0
T3	2624	0	0	0
T7	3618	0	0	0
T8	758	0	0	0
T14	57474	82	0	0
T15	0	5	0	0
T16	2778	0	0	0
T18	1453	19	0	0
T19	1592	0	0	0
T20	1905	19	0	0
T22	0	176	0	0
T26	0	3	0	0
T27	0	7	0	0
T28	0	3	0	0
T59	0	103	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	574969	0	0
T1	2386	19	0	0
T2	1619	0	0	0
T3	2624	0	0	0
T7	3618	0	0	0
T8	758	0	0	0
T14	57474	82	0	0
T15	0	5	0	0
T16	2778	0	0	0
T18	1453	19	0	0
T19	1592	0	0	0
T20	1905	19	0	0
T22	0	176	0	0
T26	0	3	0	0
T27	0	7	0	0
T28	0	3	0	0
T59	0	103	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T11 T12 T85 
47         1/1                out_o.err <= '0;
           Tests:       T11 T12 T85 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T27 T22 T11 
50         1/1                out_o.err <= '0;
           Tests:       T27 T22 T11 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T1 T18 T14 
53         1/1                out_o.part <= part_i;
           Tests:       T1 T18 T14 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T1 T18 T14 
55         1/1                out_o.attr <= Wip;
           Tests:       T1 T18 T14 
56         1/1                out_o.err <= '0;
           Tests:       T1 T18 T14 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T1 T18 T14 
59         1/1                out_o.attr <= Valid;
           Tests:       T1 T18 T14 
60         1/1                out_o.err <= err_i;
           Tests:       T1 T18 T14 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T85,T86,T88

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T14

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27,T22,T89

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T18,T14

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T18,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T11,T12,T85
0	0	1	-	-	Covered	T27,T22,T11
0	0	0	1	-	Covered	T1,T18,T14
0	0	0	0	1	Covered	T1,T18,T14
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	387955770	574611	0	0
UpdateCheck_A	387955770	574609	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	574611	0	0
T1	2386	19	0	0
T2	1619	0	0	0
T3	2624	0	0	0
T7	3618	0	0	0
T8	758	0	0	0
T14	57474	82	0	0
T15	0	4	0	0
T16	2778	0	0	0
T18	1453	18	0	0
T19	1592	0	0	0
T20	1905	19	0	0
T22	0	175	0	0
T26	0	2	0	0
T27	0	7	0	0
T28	0	3	0	0
T59	0	103	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	574609	0	0
T1	2386	19	0	0
T2	1619	0	0	0
T3	2624	0	0	0
T7	3618	0	0	0
T8	758	0	0	0
T14	57474	82	0	0
T15	0	4	0	0
T16	2778	0	0	0
T18	1453	18	0	0
T19	1592	0	0	0
T20	1905	19	0	0
T22	0	175	0	0
T26	0	2	0	0
T27	0	7	0	0
T28	0	3	0	0
T59	0	103	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T11 T12 T85 
47         1/1                out_o.err <= '0;
           Tests:       T11 T12 T85 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T27 T22 T11 
50         1/1                out_o.err <= '0;
           Tests:       T27 T22 T11 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T1 T18 T14 
53         1/1                out_o.part <= part_i;
           Tests:       T1 T18 T14 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T1 T18 T14 
55         1/1                out_o.attr <= Wip;
           Tests:       T1 T18 T14 
56         1/1                out_o.err <= '0;
           Tests:       T1 T18 T14 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T1 T18 T14 
59         1/1                out_o.attr <= Valid;
           Tests:       T1 T18 T14 
60         1/1                out_o.err <= err_i;
           Tests:       T1 T18 T14 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T85,T86,T88

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T14

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T27,T22,T89

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T18,T14

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T18,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T11,T12,T85
0	0	1	-	-	Covered	T27,T22,T11
0	0	0	1	-	Covered	T1,T18,T14
0	0	0	0	1	Covered	T1,T18,T14
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	387955770	574186	0	0
UpdateCheck_A	387955770	574184	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	574186	0	0
T1	2386	18	0	0
T2	1619	0	0	0
T3	2624	0	0	0
T7	3618	0	0	0
T8	758	0	0	0
T14	57474	81	0	0
T15	0	4	0	0
T16	2778	0	0	0
T18	1453	18	0	0
T19	1592	0	0	0
T20	1905	18	0	0
T22	0	175	0	0
T26	0	2	0	0
T27	0	6	0	0
T28	0	3	0	0
T59	0	102	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	574184	0	0
T1	2386	18	0	0
T2	1619	0	0	0
T3	2624	0	0	0
T7	3618	0	0	0
T8	758	0	0	0
T14	57474	81	0	0
T15	0	4	0	0
T16	2778	0	0	0
T18	1453	18	0	0
T19	1592	0	0	0
T20	1905	18	0	0
T22	0	175	0	0
T26	0	2	0	0
T27	0	6	0	0
T28	0	3	0	0
T59	0	102	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T11 T12 T85 
47         1/1                out_o.err <= '0;
           Tests:       T11 T12 T85 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T15 T22 T11 
50         1/1                out_o.err <= '0;
           Tests:       T15 T22 T11 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T1 T18 T14 
53         1/1                out_o.part <= part_i;
           Tests:       T1 T18 T14 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T1 T18 T14 
55         1/1                out_o.attr <= Wip;
           Tests:       T1 T18 T14 
56         1/1                out_o.err <= '0;
           Tests:       T1 T18 T14 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T1 T18 T14 
59         1/1                out_o.attr <= Valid;
           Tests:       T1 T18 T14 
60         1/1                out_o.err <= err_i;
           Tests:       T1 T18 T14 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T85,T86,T88

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T18,T14

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T22,T89

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T18,T14

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T18,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T11,T12,T85
0	0	1	-	-	Covered	T15,T22,T11
0	0	0	1	-	Covered	T1,T18,T14
0	0	0	0	1	Covered	T1,T18,T14
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	387955770	574131	0	0
UpdateCheck_A	387955770	574129	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	574131	0	0
T1	2386	18	0	0
T2	1619	0	0	0
T3	2624	0	0	0
T7	3618	0	0	0
T8	758	0	0	0
T14	57474	81	0	0
T15	0	5	0	0
T16	2778	0	0	0
T18	1453	18	0	0
T19	1592	0	0	0
T20	1905	18	0	0
T22	0	166	0	0
T26	0	2	0	0
T27	0	5	0	0
T28	0	3	0	0
T59	0	102	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387955770	574129	0	0
T1	2386	18	0	0
T2	1619	0	0	0
T3	2624	0	0	0
T7	3618	0	0	0
T8	758	0	0	0
T14	57474	81	0	0
T15	0	5	0	0
T16	2778	0	0	0
T18	1453	18	0	0
T19	1592	0	0	0
T20	1905	18	0	0
T22	0	166	0	0
T26	0	2	0	0
T27	0	5	0	0
T28	0	3	0	0
T59	0	102	0	0