Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.50 92.31 97.69 100.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.50 92.31 97.69 100.00 80.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.71 100.00 90.83 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.50 92.31 97.69 100.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.50 92.31 97.69 100.00 80.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.54 100.00 90.17 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.50 100.00 88.24 100.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.50 100.00 88.24 100.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_prim_arbiter_tree_op


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 94.12 100.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 94.12 100.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_prim_arbiter_tree_op


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.86 100.00 97.67 100.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.86 100.00 97.67 100.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.00 100.00 40.00 100.00 u_prim_arbiter_tree_calc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.86 100.00 97.67 100.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.86 100.00 97.67 100.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.00 100.00 40.00 100.00 u_prim_arbiter_tree_calc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Line Coverage for Module self-instances :
SCORELINE
92.50 92.31
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCORELINE
92.50 92.31
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

Line No.TotalCoveredPercent
TOTAL524892.31
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16300
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00

61 logic unused_req_chk; 62 unreachable assign unused_req_chk = req_chk_i; 63 64 `ASSERT_INIT(CheckNGreaterZero_A, N > 0) 65 66 // this case is basically just a bypass 67 if (N == 1) begin : gen_degenerate_case 68 69 assign valid_o = req_i[0]; 70 assign data_o = data_i[0]; 71 assign gnt_o[0] = valid_o & ready_i; 72 assign idx_o = '0; 73 74 end else begin : gen_normal_case 75 76 // align to powers of 2 for simplicity 77 // a full binary tree with N levels has 2**N + 2**N-1 nodes 78 logic [2**(IdxW+1)-2:0] req_tree; 79 logic [2**(IdxW+1)-2:0] prio_tree; 80 logic [2**(IdxW+1)-2:0] sel_tree; 81 logic [2**(IdxW+1)-2:0] mask_tree; 82 logic [2**(IdxW+1)-2:0][IdxW-1:0] idx_tree; 83 logic [2**(IdxW+1)-2:0][DW-1:0] data_tree; 84 logic [N-1:0] prio_mask_d, prio_mask_q; 85 86 for (genvar level = 0; level < IdxW+1; level++) begin : gen_tree 87 // 88 // level+1 C0 C1 <- "Base1" points to the first node on "level+1", 89 // \ / these nodes are the children of the nodes one level below 90 // level Pa <- "Base0", points to the first node on "level", 91 // these nodes are the parents of the nodes one level above 92 // 93 // hence we have the following indices for the Pa, C0, C1 nodes: 94 // Pa = 2**level - 1 + offset = Base0 + offset 95 // C0 = 2**(level+1) - 1 + 2*offset = Base1 + 2*offset 96 // C1 = 2**(level+1) - 1 + 2*offset + 1 = Base1 + 2*offset + 1 97 // 98 localparam int Base0 = (2**level)-1; 99 localparam int Base1 = (2**(level+1))-1; 100 101 for (genvar offset = 0; offset < 2**level; offset++) begin : gen_level 102 localparam int Pa = Base0 + offset; 103 localparam int C0 = Base1 + 2*offset; 104 localparam int C1 = Base1 + 2*offset + 1; 105 106 // this assigns the gated interrupt source signals, their 107 // corresponding IDs and priorities to the tree leafs 108 if (level == IdxW) begin : gen_leafs 109 if (offset < N) begin : gen_assign 110 // forward path (requests and data) 111 // all requests inputs are assigned to the request tree 112 4/4 assign req_tree[Pa] = req_i[offset]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  113 // we basically split the incoming request vector into two halves with the following 114 // priority assignment. the prio_mask_q register contains a prefix sum that has been 115 // computed using the last winning index, and hence masks out all requests at offsets 116 // lower or equal the previously granted index. hence, all higher indices are considered 117 // first in the arbitration tree nodes below, before considering the lower indices. 118 4/4 assign prio_tree[Pa] = req_i[offset] & prio_mask_q[offset]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  119 // input for the index muxes (used to compute the winner index) 120 assign idx_tree[Pa] = offset; 121 // input for the data muxes 122 0/4 ==> assign data_tree[Pa] = data_i[offset]; 123 124 // backward path (grants and prefix sum) 125 // grant if selected, ready and request asserted 126 4/4 assign gnt_o[offset] = req_i[offset] & sel_tree[Pa] & ready_i; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  127 // only update mask if there is a valid request 128 4/4 assign prio_mask_d[offset] = (|req_i) ? Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  129 mask_tree[Pa] | sel_tree[Pa] & ~ready_i : 130 prio_mask_q[offset]; 131 end else begin : gen_tie_off 132 // forward path 133 assign req_tree[Pa] = '0; 134 assign prio_tree[Pa] = '0; 135 assign idx_tree[Pa] = '0; 136 assign data_tree[Pa] = '0; 137 logic unused_sigs; 138 assign unused_sigs = ^{mask_tree[Pa], 139 sel_tree[Pa]}; 140 end 141 // this creates the node assignments 142 end else begin : gen_nodes 143 // local helper variable 144 logic sel; 145 146 // forward path (requests and data) 147 // each node looks at its two children, and selects the one with higher priority 148 3/3 assign sel = ~req_tree[C0] | ~prio_tree[C0] & prio_tree[C1]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  149 // propagate requests 150 3/3 assign req_tree[Pa] = req_tree[C0] | req_tree[C1]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  151 3/3 assign prio_tree[Pa] = prio_tree[C1] | prio_tree[C0]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  152 // data and index muxes 153 // Note: these ternaries have triggered a synthesis bug in Vivado versions older 154 // than 2020.2. If the problem resurfaces again, have a look at issue #1408. 155 3/3 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  156 3/3 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  157 158 // backward path (grants and prefix sum) 159 // this propagates the selction index back and computes a hot one mask 160 3/3 assign sel_tree[C0] = sel_tree[Pa] & ~sel; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  161 3/3 assign sel_tree[C1] = sel_tree[Pa] & sel; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  162 // this performs a prefix sum for masking the input requests in the next cycle 163 1/1(2 unreachable) assign mask_tree[C0] = mask_tree[Pa]; Tests: T1 T2 T3  164 3/3 assign mask_tree[C1] = mask_tree[Pa] | sel_tree[C0]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  165 end 166 end : gen_level 167 end : gen_tree 168 169 // the results can be found at the tree root 170 if (EnDataPort) begin : gen_data_port 171 assign data_o = data_tree[0]; 172 end else begin : gen_no_dataport 173 logic [DW-1:0] unused_data; 174 1/1 assign unused_data = data_tree[0]; Tests: T1 T2 T3  175 assign data_o = '1; 176 end 177 178 // This index is unused. 179 logic unused_prio_tree; 180 1/1 assign unused_prio_tree = prio_tree[0]; Tests: T1 T2 T3  181 182 1/1 assign idx_o = idx_tree[0]; Tests: T1 T2 T3  183 1/1 assign valid_o = req_tree[0]; Tests: T1 T2 T3  184 185 // the select tree computes a hot one signal that indicates which request is currently selected 186 assign sel_tree[0] = 1'b1; 187 // the mask tree is basically a prefix sum of the hot one select signal computed above 188 assign mask_tree[0] = 1'b0; 189 190 always_ff @(posedge clk_i or negedge rst_ni) begin : p_mask_reg 191 1/1 if (!rst_ni) begin Tests: T1 T2 T3  192 1/1 prio_mask_q <= '0; Tests: T1 T2 T3  193 end else begin 194 1/1 prio_mask_q <= prio_mask_d; Tests: T1 T2 T3 

Line Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 + N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Line Coverage for Module self-instances :
SCORELINE
97.86 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORELINE
97.86 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

SCORELINE
95.50 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORELINE
96.97 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00

61 logic unused_req_chk; 62 unreachable assign unused_req_chk = req_chk_i; 63 64 `ASSERT_INIT(CheckNGreaterZero_A, N > 0) 65 66 // this case is basically just a bypass 67 if (N == 1) begin : gen_degenerate_case 68 69 assign valid_o = req_i[0]; 70 assign data_o = data_i[0]; 71 assign gnt_o[0] = valid_o & ready_i; 72 assign idx_o = '0; 73 74 end else begin : gen_normal_case 75 76 // align to powers of 2 for simplicity 77 // a full binary tree with N levels has 2**N + 2**N-1 nodes 78 logic [2**(IdxW+1)-2:0] req_tree; 79 logic [2**(IdxW+1)-2:0] prio_tree; 80 logic [2**(IdxW+1)-2:0] sel_tree; 81 logic [2**(IdxW+1)-2:0] mask_tree; 82 logic [2**(IdxW+1)-2:0][IdxW-1:0] idx_tree; 83 logic [2**(IdxW+1)-2:0][DW-1:0] data_tree; 84 logic [N-1:0] prio_mask_d, prio_mask_q; 85 86 for (genvar level = 0; level < IdxW+1; level++) begin : gen_tree 87 // 88 // level+1 C0 C1 <- "Base1" points to the first node on "level+1", 89 // \ / these nodes are the children of the nodes one level below 90 // level Pa <- "Base0", points to the first node on "level", 91 // these nodes are the parents of the nodes one level above 92 // 93 // hence we have the following indices for the Pa, C0, C1 nodes: 94 // Pa = 2**level - 1 + offset = Base0 + offset 95 // C0 = 2**(level+1) - 1 + 2*offset = Base1 + 2*offset 96 // C1 = 2**(level+1) - 1 + 2*offset + 1 = Base1 + 2*offset + 1 97 // 98 localparam int Base0 = (2**level)-1; 99 localparam int Base1 = (2**(level+1))-1; 100 101 for (genvar offset = 0; offset < 2**level; offset++) begin : gen_level 102 localparam int Pa = Base0 + offset; 103 localparam int C0 = Base1 + 2*offset; 104 localparam int C1 = Base1 + 2*offset + 1; 105 106 // this assigns the gated interrupt source signals, their 107 // corresponding IDs and priorities to the tree leafs 108 if (level == IdxW) begin : gen_leafs 109 if (offset < N) begin : gen_assign 110 // forward path (requests and data) 111 // all requests inputs are assigned to the request tree 112 2/2 assign req_tree[Pa] = req_i[offset]; Tests: T1 T2 T3  | T1 T2 T3  113 // we basically split the incoming request vector into two halves with the following 114 // priority assignment. the prio_mask_q register contains a prefix sum that has been 115 // computed using the last winning index, and hence masks out all requests at offsets 116 // lower or equal the previously granted index. hence, all higher indices are considered 117 // first in the arbitration tree nodes below, before considering the lower indices. 118 2/2 assign prio_tree[Pa] = req_i[offset] & prio_mask_q[offset]; Tests: T1 T2 T3  | T1 T2 T3  119 // input for the index muxes (used to compute the winner index) 120 assign idx_tree[Pa] = offset; 121 // input for the data muxes 122 2/2 assign data_tree[Pa] = data_i[offset]; Tests: T1 T2 T3  | T1 T2 T3  123 124 // backward path (grants and prefix sum) 125 // grant if selected, ready and request asserted 126 2/2 assign gnt_o[offset] = req_i[offset] & sel_tree[Pa] & ready_i; Tests: T1 T2 T3  | T1 T2 T3  127 // only update mask if there is a valid request 128 2/2 assign prio_mask_d[offset] = (|req_i) ? Tests: T1 T2 T3  | T1 T2 T3  129 mask_tree[Pa] | sel_tree[Pa] & ~ready_i : 130 prio_mask_q[offset]; 131 end else begin : gen_tie_off 132 // forward path 133 assign req_tree[Pa] = '0; 134 assign prio_tree[Pa] = '0; 135 assign idx_tree[Pa] = '0; 136 assign data_tree[Pa] = '0; 137 logic unused_sigs; 138 assign unused_sigs = ^{mask_tree[Pa], 139 sel_tree[Pa]}; 140 end 141 // this creates the node assignments 142 end else begin : gen_nodes 143 // local helper variable 144 logic sel; 145 146 // forward path (requests and data) 147 // each node looks at its two children, and selects the one with higher priority 148 1/1 assign sel = ~req_tree[C0] | ~prio_tree[C0] & prio_tree[C1]; Tests: T1 T2 T3  149 // propagate requests 150 1/1 assign req_tree[Pa] = req_tree[C0] | req_tree[C1]; Tests: T1 T2 T3  151 1/1 assign prio_tree[Pa] = prio_tree[C1] | prio_tree[C0]; Tests: T1 T2 T3  152 // data and index muxes 153 // Note: these ternaries have triggered a synthesis bug in Vivado versions older 154 // than 2020.2. If the problem resurfaces again, have a look at issue #1408. 155 1/1 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; Tests: T1 T2 T3  156 1/1 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; Tests: T1 T2 T3  157 158 // backward path (grants and prefix sum) 159 // this propagates the selction index back and computes a hot one mask 160 1/1 assign sel_tree[C0] = sel_tree[Pa] & ~sel; Tests: T1 T2 T3  161 1/1 assign sel_tree[C1] = sel_tree[Pa] & sel; Tests: T1 T2 T3  162 // this performs a prefix sum for masking the input requests in the next cycle 163 unreachable assign mask_tree[C0] = mask_tree[Pa]; 164 1/1 assign mask_tree[C1] = mask_tree[Pa] | sel_tree[C0]; Tests: T1 T2 T3  165 end 166 end : gen_level 167 end : gen_tree 168 169 // the results can be found at the tree root 170 if (EnDataPort) begin : gen_data_port 171 1/1 assign data_o = data_tree[0]; Tests: T1 T2 T3  172 end else begin : gen_no_dataport 173 logic [DW-1:0] unused_data; 174 assign unused_data = data_tree[0]; 175 assign data_o = '1; 176 end 177 178 // This index is unused. 179 logic unused_prio_tree; 180 1/1 assign unused_prio_tree = prio_tree[0]; Tests: T1 T2 T3  181 182 1/1 assign idx_o = idx_tree[0]; Tests: T1 T2 T3  183 1/1 assign valid_o = req_tree[0]; Tests: T1 T2 T3  184 185 // the select tree computes a hot one signal that indicates which request is currently selected 186 assign sel_tree[0] = 1'b1; 187 // the mask tree is basically a prefix sum of the hot one select signal computed above 188 assign mask_tree[0] = 1'b0; 189 190 always_ff @(posedge clk_i or negedge rst_ni) begin : p_mask_reg 191 1/1 if (!rst_ni) begin Tests: T1 T2 T3  192 1/1 prio_mask_q <= '0; Tests: T1 T2 T3  193 end else begin 194 1/1 prio_mask_q <= prio_mask_d; Tests: T1 T2 T3 

Cond Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :
SCORECOND
97.86 97.67
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORECOND
97.86 97.67
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

TotalCoveredPercent
Conditions434297.67
Logical434297.67
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT18,T20,T27
11CoveredT18,T20,T26

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Unreachable
101UnreachableT11,T45,T41
110CoveredT1,T2,T3
111UnreachableT1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Unreachable
101UnreachableT11,T45,T41
110CoveredT18,T20,T26
111UnreachableT18,T20,T26

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT18,T20,T26
10UnreachableT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT18,T20,T26
01CoveredT18,T20,T26
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT18,T20,T26
11CoveredT18,T20,T26

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T45,T41
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT11,T45,T41
10CoveredT1,T2,T3
11CoveredT18,T20,T26

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT18,T20,T26
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT18,T20,T26

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

Cond Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :
SCORECOND
95.50 88.24
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORECOND
96.97 94.12
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

TotalCoveredPercent
Conditions514996.08
Logical514996.08
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT18,T20,T27
11CoveredT18,T20,T26

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT81
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011CoveredT81
101CoveredT81
110CoveredT18,T20,T26
111CoveredT18,T20,T26

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT18,T20,T26
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT18,T20,T26
01CoveredT18,T20,T26
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT18,T20,T26
11CoveredT18,T20,T26

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT81
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT81
10CoveredT1,T2,T3
11CoveredT18,T20,T26

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT18,T20,T26
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT18,T20,T26

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

Cond Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Cond Coverage for Module self-instances :
SCORECOND
92.50 97.69
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCORECOND
92.50 97.69
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

TotalCoveredPercent
Conditions13012797.69
Logical13012797.69
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT16,T27,T22
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT3,T16,T15
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT3,T16,T15
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT57,T176,T189
11CoveredT1,T2,T3

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T18
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T3,T18

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110CoveredT1,T3,T18
111CoveredT1,T18,T14

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT1,T18,T14
111CoveredT1,T18,T14

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T3,T18
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T18
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T18,T14
01CoveredT1,T3,T18
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T18,T14
11CoveredT1,T3,T18

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T18,T14
01CoveredT1,T18,T14
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T18,T14
11CoveredT1,T18,T14

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T18
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T3,T18

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T18,T14
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T18,T14

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T65,T41
10CoveredT17,T65,T41

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T3,T18

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T18,T14
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T65,T41
10CoveredT1,T3,T18

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T49,T45
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T18,T14

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T3,T18
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T3,T18

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT27,T17,T49
10CoveredT1,T3,T18
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T18
10CoveredT1,T2,T3

Branch Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Branch Coverage for Module self-instances :
SCOREBRANCH
92.50 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCOREBRANCH
92.50 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

Line No.TotalCoveredPercent
Branches 22 22 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


191 if (!rst_ni) begin -1- 192 prio_mask_q <= '0; ==> 193 end else begin 194 prio_mask_q <= prio_mask_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Branch Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 + N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Branch Coverage for Module self-instances :
SCOREBRANCH
97.86 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCOREBRANCH
97.86 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

SCOREBRANCH
95.50 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCOREBRANCH
96.97 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


191 if (!rst_ni) begin -1- 192 prio_mask_q <= '0; ==> 193 end else begin 194 prio_mask_q <= prio_mask_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_arbiter_tree
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 2147483647 2147483647 0 0
CheckNGreaterZero_A 6336 6336 0 0
GntImpliesReady_A 2147483647 69327822 0 0
GntImpliesValid_A 2147483647 69327822 0 0
GrantKnown_A 2147483647 2147483647 0 0
IdxKnown_A 2147483647 2147483647 0 0
IndexIsCorrect_A 2147483647 69327822 0 0
LockArbDecision_A 2147483647 64507218 0 0
NoReadyValidNoGrant_A 2147483647 1974869176 0 0
ReadyAndValidImplyGrant_A 2147483647 69327822 0 0
ReqAndReadyImplyGrant_A 2147483647 69327822 0 0
ReqImpliesValid_A 2147483647 338471027 0 0
ReqStaysHighUntilGranted0_M 2147483647 64507122 0 0
RoundRobin_A 2147483647 0 0 6306
ValidKnown_A 2147483647 2147483647 0 0
gen_data_port_assertion.DataFlow_A 1551823080 64507252 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 14316 13890 0 0
T2 9714 9384 0 0
T3 15744 15174 0 0
T7 21708 21384 0 0
T8 4548 4164 0 0
T14 344844 344322 0 0
T16 16668 16068 0 0
T18 8718 8280 0 0
T19 9552 8568 0 0
T20 11430 11046 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6336 6336 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T7 6 6 0 0
T8 6 6 0 0
T14 6 6 0 0
T16 6 6 0 0
T18 6 6 0 0
T19 6 6 0 0
T20 6 6 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 69327822 0 0
T1 11930 198 0 0
T2 9714 129 0 0
T3 15744 130 0 0
T7 21708 128 0 0
T8 4548 132 0 0
T14 344844 808 0 0
T15 82187 33 0 0
T16 16668 155 0 0
T18 8718 489 0 0
T19 9552 256 0 0
T20 11430 494 0 0
T22 0 814 0 0
T26 0 28 0 0
T27 0 94 0 0
T28 0 54 0 0
T59 0 891 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 69327822 0 0
T1 11930 198 0 0
T2 9714 129 0 0
T3 15744 130 0 0
T7 21708 128 0 0
T8 4548 132 0 0
T14 344844 808 0 0
T15 82187 33 0 0
T16 16668 155 0 0
T18 8718 489 0 0
T19 9552 256 0 0
T20 11430 494 0 0
T22 0 814 0 0
T26 0 28 0 0
T27 0 94 0 0
T28 0 54 0 0
T59 0 891 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 14316 13890 0 0
T2 9714 9384 0 0
T3 15744 15174 0 0
T7 21708 21384 0 0
T8 4548 4164 0 0
T14 344844 344322 0 0
T16 16668 16068 0 0
T18 8718 8280 0 0
T19 9552 8568 0 0
T20 11430 11046 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 14316 13890 0 0
T2 9714 9384 0 0
T3 15744 15174 0 0
T7 21708 21384 0 0
T8 4548 4164 0 0
T14 344844 344322 0 0
T16 16668 16068 0 0
T18 8718 8280 0 0
T19 9552 8568 0 0
T20 11430 11046 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 69327822 0 0
T1 11930 198 0 0
T2 9714 129 0 0
T3 15744 130 0 0
T7 21708 128 0 0
T8 4548 132 0 0
T14 344844 808 0 0
T15 82187 33 0 0
T16 16668 155 0 0
T18 8718 489 0 0
T19 9552 256 0 0
T20 11430 494 0 0
T22 0 814 0 0
T26 0 28 0 0
T27 0 94 0 0
T28 0 54 0 0
T59 0 891 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 64507218 0 0
T1 9544 128 0 0
T2 6476 128 0 0
T3 10496 128 0 0
T7 14472 128 0 0
T8 3032 132 0 0
T14 229896 128 0 0
T16 11112 128 0 0
T18 5812 420 0 0
T19 6368 256 0 0
T20 7620 424 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1974869176 0 0
T1 14316 11719 0 0
T2 9714 7855 0 0
T3 15744 13530 0 0
T7 21708 21096 0 0
T8 4548 3868 0 0
T14 344844 235206 0 0
T16 16668 14123 0 0
T18 8718 6479 0 0
T19 9552 7992 0 0
T20 11430 8763 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 69327822 0 0
T1 11930 198 0 0
T2 9714 129 0 0
T3 15744 130 0 0
T7 21708 128 0 0
T8 4548 132 0 0
T14 344844 808 0 0
T15 82187 33 0 0
T16 16668 155 0 0
T18 8718 489 0 0
T19 9552 256 0 0
T20 11430 494 0 0
T22 0 814 0 0
T26 0 28 0 0
T27 0 94 0 0
T28 0 54 0 0
T59 0 891 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 69327822 0 0
T1 11930 198 0 0
T2 9714 129 0 0
T3 15744 130 0 0
T7 21708 128 0 0
T8 4548 132 0 0
T14 344844 808 0 0
T15 82187 33 0 0
T16 16668 155 0 0
T18 8718 489 0 0
T19 9552 256 0 0
T20 11430 494 0 0
T22 0 814 0 0
T26 0 28 0 0
T27 0 94 0 0
T28 0 54 0 0
T59 0 891 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 338471027 0 0
T1 11930 2135 0 0
T2 9714 1493 0 0
T3 15744 1604 0 0
T7 21708 256 0 0
T8 4548 264 0 0
T14 344844 109076 0 0
T15 82187 130441 0 0
T16 16668 1901 0 0
T18 8718 1765 0 0
T19 9552 512 0 0
T20 11430 2247 0 0
T22 0 374045 0 0
T26 0 2334 0 0
T27 0 7736 0 0
T28 0 1985 0 0
T59 0 126434 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 64507122 0 0
T1 9544 128 0 0
T2 6476 128 0 0
T3 10496 128 0 0
T7 14472 128 0 0
T8 3032 132 0 0
T14 229896 128 0 0
T16 11112 128 0 0
T18 5812 420 0 0
T19 6368 256 0 0
T20 7620 424 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 0 0 6306

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 14316 13890 0 0
T2 9714 9384 0 0
T3 15744 15174 0 0
T7 21708 21384 0 0
T8 4548 4164 0 0
T14 344844 344322 0 0
T16 16668 16068 0 0
T18 8718 8280 0 0
T19 9552 8568 0 0
T20 11430 11046 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1551823080 64507252 0 0
T1 9544 128 0 0
T2 6476 128 0 0
T3 10496 128 0 0
T7 14472 128 0 0
T8 3032 132 0 0
T14 229896 128 0 0
T16 11112 128 0 0
T18 5812 420 0 0
T19 6368 256 0 0
T20 7620 424 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
Line No.TotalCoveredPercent
TOTAL524892.31
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16300
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00

61 logic unused_req_chk; 62 unreachable assign unused_req_chk = req_chk_i; 63 64 `ASSERT_INIT(CheckNGreaterZero_A, N > 0) 65 66 // this case is basically just a bypass 67 if (N == 1) begin : gen_degenerate_case 68 69 assign valid_o = req_i[0]; 70 assign data_o = data_i[0]; 71 assign gnt_o[0] = valid_o & ready_i; 72 assign idx_o = '0; 73 74 end else begin : gen_normal_case 75 76 // align to powers of 2 for simplicity 77 // a full binary tree with N levels has 2**N + 2**N-1 nodes 78 logic [2**(IdxW+1)-2:0] req_tree; 79 logic [2**(IdxW+1)-2:0] prio_tree; 80 logic [2**(IdxW+1)-2:0] sel_tree; 81 logic [2**(IdxW+1)-2:0] mask_tree; 82 logic [2**(IdxW+1)-2:0][IdxW-1:0] idx_tree; 83 logic [2**(IdxW+1)-2:0][DW-1:0] data_tree; 84 logic [N-1:0] prio_mask_d, prio_mask_q; 85 86 for (genvar level = 0; level < IdxW+1; level++) begin : gen_tree 87 // 88 // level+1 C0 C1 <- "Base1" points to the first node on "level+1", 89 // \ / these nodes are the children of the nodes one level below 90 // level Pa <- "Base0", points to the first node on "level", 91 // these nodes are the parents of the nodes one level above 92 // 93 // hence we have the following indices for the Pa, C0, C1 nodes: 94 // Pa = 2**level - 1 + offset = Base0 + offset 95 // C0 = 2**(level+1) - 1 + 2*offset = Base1 + 2*offset 96 // C1 = 2**(level+1) - 1 + 2*offset + 1 = Base1 + 2*offset + 1 97 // 98 localparam int Base0 = (2**level)-1; 99 localparam int Base1 = (2**(level+1))-1; 100 101 for (genvar offset = 0; offset < 2**level; offset++) begin : gen_level 102 localparam int Pa = Base0 + offset; 103 localparam int C0 = Base1 + 2*offset; 104 localparam int C1 = Base1 + 2*offset + 1; 105 106 // this assigns the gated interrupt source signals, their 107 // corresponding IDs and priorities to the tree leafs 108 if (level == IdxW) begin : gen_leafs 109 if (offset < N) begin : gen_assign 110 // forward path (requests and data) 111 // all requests inputs are assigned to the request tree 112 4/4 assign req_tree[Pa] = req_i[offset]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  113 // we basically split the incoming request vector into two halves with the following 114 // priority assignment. the prio_mask_q register contains a prefix sum that has been 115 // computed using the last winning index, and hence masks out all requests at offsets 116 // lower or equal the previously granted index. hence, all higher indices are considered 117 // first in the arbitration tree nodes below, before considering the lower indices. 118 4/4 assign prio_tree[Pa] = req_i[offset] & prio_mask_q[offset]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  119 // input for the index muxes (used to compute the winner index) 120 assign idx_tree[Pa] = offset; 121 // input for the data muxes 122 0/4 ==> assign data_tree[Pa] = data_i[offset]; 123 124 // backward path (grants and prefix sum) 125 // grant if selected, ready and request asserted 126 4/4 assign gnt_o[offset] = req_i[offset] & sel_tree[Pa] & ready_i; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  127 // only update mask if there is a valid request 128 4/4 assign prio_mask_d[offset] = (|req_i) ? Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  129 mask_tree[Pa] | sel_tree[Pa] & ~ready_i : 130 prio_mask_q[offset]; 131 end else begin : gen_tie_off 132 // forward path 133 assign req_tree[Pa] = '0; 134 assign prio_tree[Pa] = '0; 135 assign idx_tree[Pa] = '0; 136 assign data_tree[Pa] = '0; 137 logic unused_sigs; 138 assign unused_sigs = ^{mask_tree[Pa], 139 sel_tree[Pa]}; 140 end 141 // this creates the node assignments 142 end else begin : gen_nodes 143 // local helper variable 144 logic sel; 145 146 // forward path (requests and data) 147 // each node looks at its two children, and selects the one with higher priority 148 3/3 assign sel = ~req_tree[C0] | ~prio_tree[C0] & prio_tree[C1]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  149 // propagate requests 150 3/3 assign req_tree[Pa] = req_tree[C0] | req_tree[C1]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  151 3/3 assign prio_tree[Pa] = prio_tree[C1] | prio_tree[C0]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  152 // data and index muxes 153 // Note: these ternaries have triggered a synthesis bug in Vivado versions older 154 // than 2020.2. If the problem resurfaces again, have a look at issue #1408. 155 3/3 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  156 3/3 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  157 158 // backward path (grants and prefix sum) 159 // this propagates the selction index back and computes a hot one mask 160 3/3 assign sel_tree[C0] = sel_tree[Pa] & ~sel; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  161 3/3 assign sel_tree[C1] = sel_tree[Pa] & sel; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  162 // this performs a prefix sum for masking the input requests in the next cycle 163 1/1(2 unreachable) assign mask_tree[C0] = mask_tree[Pa]; Tests: T1 T2 T3  164 3/3 assign mask_tree[C1] = mask_tree[Pa] | sel_tree[C0]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  165 end 166 end : gen_level 167 end : gen_tree 168 169 // the results can be found at the tree root 170 if (EnDataPort) begin : gen_data_port 171 assign data_o = data_tree[0]; 172 end else begin : gen_no_dataport 173 logic [DW-1:0] unused_data; 174 1/1 assign unused_data = data_tree[0]; Tests: T1 T2 T3  175 assign data_o = '1; 176 end 177 178 // This index is unused. 179 logic unused_prio_tree; 180 1/1 assign unused_prio_tree = prio_tree[0]; Tests: T1 T2 T3  181 182 1/1 assign idx_o = idx_tree[0]; Tests: T1 T2 T3  183 1/1 assign valid_o = req_tree[0]; Tests: T1 T2 T3  184 185 // the select tree computes a hot one signal that indicates which request is currently selected 186 assign sel_tree[0] = 1'b1; 187 // the mask tree is basically a prefix sum of the hot one select signal computed above 188 assign mask_tree[0] = 1'b0; 189 190 always_ff @(posedge clk_i or negedge rst_ni) begin : p_mask_reg 191 1/1 if (!rst_ni) begin Tests: T1 T2 T3  192 1/1 prio_mask_q <= '0; Tests: T1 T2 T3  193 end else begin 194 1/1 prio_mask_q <= prio_mask_d; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
TotalCoveredPercent
Conditions13012797.69
Logical13012797.69
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT16,T27,T22
10CoveredT2,T3,T14
11CoveredT2,T3,T14

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT3,T16,T27
10CoveredT2,T3,T14
11CoveredT2,T3,T14

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT3,T16,T27
10CoveredT2,T3,T14
11CoveredT2,T3,T14

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T3,T14
10CoveredT57,T176,T189
11CoveredT2,T3,T14

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT3,T14,T16
110CoveredT2,T3,T14
111CoveredT2,T3,T14

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T3,T14
110CoveredT2,T3,T14
111CoveredT3,T14,T16

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T3,T14
110CoveredT3,T14,T16
111CoveredT14,T16,T15

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T14
110CoveredT14,T16,T15
111CoveredT14,T16,T15

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T14

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT2,T3,T14
01CoveredT2,T3,T14
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT2,T3,T14
10CoveredT2,T3,T14
11CoveredT2,T3,T14

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T14

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT3,T14,T16
01CoveredT2,T3,T14
10CoveredT2,T3,T14

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT2,T3,T14
10CoveredT3,T14,T16
11CoveredT2,T3,T14

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T14

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT14,T16,T15
01CoveredT3,T14,T16
10CoveredT2,T3,T14

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT2,T3,T14
10CoveredT14,T16,T15
11CoveredT3,T14,T16

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T14

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT14,T16,T15
01CoveredT14,T16,T15
10CoveredT2,T3,T14

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT2,T3,T14
10CoveredT14,T16,T15
11CoveredT14,T16,T15

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT2,T3,T14
01CoveredT3,T14,T16
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT2,T3,T14
10CoveredT1,T2,T3
11CoveredT3,T14,T16

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT2,T3,T14
01CoveredT2,T3,T14
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1--2-StatusTests
01CoveredT2,T3,T14
10CoveredT1,T2,T3
11CoveredT2,T3,T14

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1--2-StatusTests
00CoveredT2,T3,T14
01CoveredT14,T16,T15
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1--2-StatusTests
01CoveredT2,T3,T14
10CoveredT1,T2,T3
11CoveredT14,T16,T15

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T65,T50
10CoveredT17,T65,T50

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T14
10CoveredT3,T14,T16

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT14,T16,T15
10CoveredT2,T3,T14

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T65,T50
10CoveredT3,T14,T16

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T49,T45
10CoveredT2,T3,T14

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T14
10CoveredT14,T16,T15

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT2,T3,T14
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT2,T3,T14
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT2,T3,T14
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT2,T3,T14
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT2,T3,T14
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT2,T3,T14
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT2,T3,T14

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT3,T14,T16
10CoveredT2,T3,T14
11CoveredT2,T3,T14

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT2,T3,T14
10CoveredT1,T2,T3
11CoveredT3,T14,T16

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT2,T3,T14
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T14
11CoveredT2,T3,T14

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT27,T17,T49
10CoveredT3,T14,T16
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T14
10Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T14
10Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T14,T16
10CoveredT2,T3,T14

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
Line No.TotalCoveredPercent
Branches 22 22 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T14


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T14


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T14


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T14


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T14


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T14


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T14
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T14
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T14
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T14
0 Covered T1,T2,T3


191 if (!rst_ni) begin -1- 192 prio_mask_q <= '0; ==> 193 end else begin 194 prio_mask_q <= prio_mask_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 12 80.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 12 80.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 387955770 387167133 0 0
CheckNGreaterZero_A 1056 1056 0 0
GntImpliesReady_A 387955770 2580618 0 0
GntImpliesValid_A 387955770 2580618 0 0
GrantKnown_A 387955770 387167133 0 0
IdxKnown_A 387955770 387167133 0 0
IndexIsCorrect_A 387955770 2580618 0 0
LockArbDecision_A 387955770 0 0 0
NoReadyValidNoGrant_A 387955770 266979268 0 0
ReadyAndValidImplyGrant_A 387955770 2580618 0 0
ReqAndReadyImplyGrant_A 387955770 2580618 0 0
ReqImpliesValid_A 387955770 115046997 0 0
ReqStaysHighUntilGranted0_M 387955770 0 0 0
RoundRobin_A 387955770 0 0 1051
ValidKnown_A 387955770 387167133 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1056 1056 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T14 1 1 0 0
T16 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 2580618 0 0
T2 1619 1 0 0
T3 2624 2 0 0
T7 3618 0 0 0
T8 758 0 0 0
T14 57474 358 0 0
T15 82187 20 0 0
T16 2778 27 0 0
T18 1453 0 0 0
T19 1592 0 0 0
T20 1905 0 0 0
T22 0 354 0 0
T26 0 23 0 0
T27 0 76 0 0
T28 0 46 0 0
T59 0 485 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 2580618 0 0
T2 1619 1 0 0
T3 2624 2 0 0
T7 3618 0 0 0
T8 758 0 0 0
T14 57474 358 0 0
T15 82187 20 0 0
T16 2778 27 0 0
T18 1453 0 0 0
T19 1592 0 0 0
T20 1905 0 0 0
T22 0 354 0 0
T26 0 23 0 0
T27 0 76 0 0
T28 0 46 0 0
T59 0 485 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 2580618 0 0
T2 1619 1 0 0
T3 2624 2 0 0
T7 3618 0 0 0
T8 758 0 0 0
T14 57474 358 0 0
T15 82187 20 0 0
T16 2778 27 0 0
T18 1453 0 0 0
T19 1592 0 0 0
T20 1905 0 0 0
T22 0 354 0 0
T26 0 23 0 0
T27 0 76 0 0
T28 0 46 0 0
T59 0 485 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 0 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 266979268 0 0
T1 2386 2283 0 0
T2 1619 291 0 0
T3 2624 1141 0 0
T7 3618 3532 0 0
T8 758 662 0 0
T14 57474 817 0 0
T16 2778 989 0 0
T18 1453 1348 0 0
T19 1592 1364 0 0
T20 1905 1809 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 2580618 0 0
T2 1619 1 0 0
T3 2624 2 0 0
T7 3618 0 0 0
T8 758 0 0 0
T14 57474 358 0 0
T15 82187 20 0 0
T16 2778 27 0 0
T18 1453 0 0 0
T19 1592 0 0 0
T20 1905 0 0 0
T22 0 354 0 0
T26 0 23 0 0
T27 0 76 0 0
T28 0 46 0 0
T59 0 485 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 2580618 0 0
T2 1619 1 0 0
T3 2624 2 0 0
T7 3618 0 0 0
T8 758 0 0 0
T14 57474 358 0 0
T15 82187 20 0 0
T16 2778 27 0 0
T18 1453 0 0 0
T19 1592 0 0 0
T20 1905 0 0 0
T22 0 354 0 0
T26 0 23 0 0
T27 0 76 0 0
T28 0 46 0 0
T59 0 485 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 115046997 0 0
T2 1619 1237 0 0
T3 2624 1348 0 0
T7 3618 0 0 0
T8 758 0 0 0
T14 57474 56534 0 0
T15 82187 66985 0 0
T16 2778 1645 0 0
T18 1453 0 0 0
T19 1592 0 0 0
T20 1905 0 0 0
T22 0 188975 0 0
T26 0 1220 0 0
T27 0 3543 0 0
T28 0 912 0 0
T59 0 63190 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 0 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 0 0 1051

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
Line No.TotalCoveredPercent
TOTAL524892.31
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16300
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00

61 logic unused_req_chk; 62 unreachable assign unused_req_chk = req_chk_i; 63 64 `ASSERT_INIT(CheckNGreaterZero_A, N > 0) 65 66 // this case is basically just a bypass 67 if (N == 1) begin : gen_degenerate_case 68 69 assign valid_o = req_i[0]; 70 assign data_o = data_i[0]; 71 assign gnt_o[0] = valid_o & ready_i; 72 assign idx_o = '0; 73 74 end else begin : gen_normal_case 75 76 // align to powers of 2 for simplicity 77 // a full binary tree with N levels has 2**N + 2**N-1 nodes 78 logic [2**(IdxW+1)-2:0] req_tree; 79 logic [2**(IdxW+1)-2:0] prio_tree; 80 logic [2**(IdxW+1)-2:0] sel_tree; 81 logic [2**(IdxW+1)-2:0] mask_tree; 82 logic [2**(IdxW+1)-2:0][IdxW-1:0] idx_tree; 83 logic [2**(IdxW+1)-2:0][DW-1:0] data_tree; 84 logic [N-1:0] prio_mask_d, prio_mask_q; 85 86 for (genvar level = 0; level < IdxW+1; level++) begin : gen_tree 87 // 88 // level+1 C0 C1 <- "Base1" points to the first node on "level+1", 89 // \ / these nodes are the children of the nodes one level below 90 // level Pa <- "Base0", points to the first node on "level", 91 // these nodes are the parents of the nodes one level above 92 // 93 // hence we have the following indices for the Pa, C0, C1 nodes: 94 // Pa = 2**level - 1 + offset = Base0 + offset 95 // C0 = 2**(level+1) - 1 + 2*offset = Base1 + 2*offset 96 // C1 = 2**(level+1) - 1 + 2*offset + 1 = Base1 + 2*offset + 1 97 // 98 localparam int Base0 = (2**level)-1; 99 localparam int Base1 = (2**(level+1))-1; 100 101 for (genvar offset = 0; offset < 2**level; offset++) begin : gen_level 102 localparam int Pa = Base0 + offset; 103 localparam int C0 = Base1 + 2*offset; 104 localparam int C1 = Base1 + 2*offset + 1; 105 106 // this assigns the gated interrupt source signals, their 107 // corresponding IDs and priorities to the tree leafs 108 if (level == IdxW) begin : gen_leafs 109 if (offset < N) begin : gen_assign 110 // forward path (requests and data) 111 // all requests inputs are assigned to the request tree 112 4/4 assign req_tree[Pa] = req_i[offset]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  113 // we basically split the incoming request vector into two halves with the following 114 // priority assignment. the prio_mask_q register contains a prefix sum that has been 115 // computed using the last winning index, and hence masks out all requests at offsets 116 // lower or equal the previously granted index. hence, all higher indices are considered 117 // first in the arbitration tree nodes below, before considering the lower indices. 118 4/4 assign prio_tree[Pa] = req_i[offset] & prio_mask_q[offset]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  119 // input for the index muxes (used to compute the winner index) 120 assign idx_tree[Pa] = offset; 121 // input for the data muxes 122 0/4 ==> assign data_tree[Pa] = data_i[offset]; 123 124 // backward path (grants and prefix sum) 125 // grant if selected, ready and request asserted 126 4/4 assign gnt_o[offset] = req_i[offset] & sel_tree[Pa] & ready_i; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  127 // only update mask if there is a valid request 128 4/4 assign prio_mask_d[offset] = (|req_i) ? Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  129 mask_tree[Pa] | sel_tree[Pa] & ~ready_i : 130 prio_mask_q[offset]; 131 end else begin : gen_tie_off 132 // forward path 133 assign req_tree[Pa] = '0; 134 assign prio_tree[Pa] = '0; 135 assign idx_tree[Pa] = '0; 136 assign data_tree[Pa] = '0; 137 logic unused_sigs; 138 assign unused_sigs = ^{mask_tree[Pa], 139 sel_tree[Pa]}; 140 end 141 // this creates the node assignments 142 end else begin : gen_nodes 143 // local helper variable 144 logic sel; 145 146 // forward path (requests and data) 147 // each node looks at its two children, and selects the one with higher priority 148 3/3 assign sel = ~req_tree[C0] | ~prio_tree[C0] & prio_tree[C1]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  149 // propagate requests 150 3/3 assign req_tree[Pa] = req_tree[C0] | req_tree[C1]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  151 3/3 assign prio_tree[Pa] = prio_tree[C1] | prio_tree[C0]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  152 // data and index muxes 153 // Note: these ternaries have triggered a synthesis bug in Vivado versions older 154 // than 2020.2. If the problem resurfaces again, have a look at issue #1408. 155 3/3 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  156 3/3 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  157 158 // backward path (grants and prefix sum) 159 // this propagates the selction index back and computes a hot one mask 160 3/3 assign sel_tree[C0] = sel_tree[Pa] & ~sel; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  161 3/3 assign sel_tree[C1] = sel_tree[Pa] & sel; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  162 // this performs a prefix sum for masking the input requests in the next cycle 163 1/1(2 unreachable) assign mask_tree[C0] = mask_tree[Pa]; Tests: T1 T2 T3  164 3/3 assign mask_tree[C1] = mask_tree[Pa] | sel_tree[C0]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  165 end 166 end : gen_level 167 end : gen_tree 168 169 // the results can be found at the tree root 170 if (EnDataPort) begin : gen_data_port 171 assign data_o = data_tree[0]; 172 end else begin : gen_no_dataport 173 logic [DW-1:0] unused_data; 174 1/1 assign unused_data = data_tree[0]; Tests: T1 T2 T3  175 assign data_o = '1; 176 end 177 178 // This index is unused. 179 logic unused_prio_tree; 180 1/1 assign unused_prio_tree = prio_tree[0]; Tests: T1 T2 T3  181 182 1/1 assign idx_o = idx_tree[0]; Tests: T1 T2 T3  183 1/1 assign valid_o = req_tree[0]; Tests: T1 T2 T3  184 185 // the select tree computes a hot one signal that indicates which request is currently selected 186 assign sel_tree[0] = 1'b1; 187 // the mask tree is basically a prefix sum of the hot one select signal computed above 188 assign mask_tree[0] = 1'b0; 189 190 always_ff @(posedge clk_i or negedge rst_ni) begin : p_mask_reg 191 1/1 if (!rst_ni) begin Tests: T1 T2 T3  192 1/1 prio_mask_q <= '0; Tests: T1 T2 T3  193 end else begin 194 1/1 prio_mask_q <= prio_mask_d; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
TotalCoveredPercent
Conditions13012797.69
Logical13012797.69
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT22,T49,T65
10CoveredT1,T18,T14
11CoveredT1,T18,T14

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT15,T22,T49
10CoveredT1,T18,T14
11CoveredT1,T18,T14

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT15,T22,T49
10CoveredT1,T18,T14
11CoveredT1,T18,T14

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T18,T14
10CoveredT57,T176,T189
11CoveredT1,T18,T14

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T18,T14
110CoveredT1,T18,T14
111CoveredT1,T18,T14

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T18,T14
110CoveredT1,T18,T14
111CoveredT1,T18,T14

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T18,T14
110CoveredT1,T18,T14
111CoveredT1,T18,T14

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011CoveredT1,T18,T14
101CoveredT1,T18,T14
110CoveredT1,T18,T14
111CoveredT1,T18,T14

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T18,T14

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T18,T14
01CoveredT1,T18,T14
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T18,T14
10CoveredT1,T18,T14
11CoveredT1,T18,T14

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T18,T14

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T18,T14
01CoveredT1,T18,T14
10CoveredT1,T18,T14

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T18,T14
10CoveredT1,T18,T14
11CoveredT1,T18,T14

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T18,T14

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T18,T14
01CoveredT1,T18,T14
10CoveredT1,T18,T14

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T18,T14
10CoveredT1,T18,T14
11CoveredT1,T18,T14

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T18,T14

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T18,T14
01CoveredT1,T18,T14
10CoveredT1,T18,T14

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T18,T14
10CoveredT1,T18,T14
11CoveredT1,T18,T14

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T18,T14
01CoveredT1,T18,T14
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT1,T18,T14
10CoveredT1,T2,T3
11CoveredT1,T18,T14

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T18,T14
01CoveredT1,T18,T14
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1--2-StatusTests
01CoveredT1,T18,T14
10CoveredT1,T2,T3
11CoveredT1,T18,T14

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1--2-StatusTests
00CoveredT1,T18,T14
01CoveredT1,T18,T14
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1--2-StatusTests
01CoveredT1,T18,T14
10CoveredT1,T2,T3
11CoveredT1,T18,T14

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT65,T41,T50
10CoveredT41,T50,T57

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T18,T14
10CoveredT1,T18,T14

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T18,T14
10CoveredT1,T18,T14

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT41,T50,T57
10CoveredT1,T18,T14

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT49,T65,T41
10CoveredT1,T18,T14

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T18,T14
10CoveredT1,T18,T14

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T18,T14
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T18,T14
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T18,T14
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T18,T14
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T18,T14
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T18,T14
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T18,T14

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T18,T14
10CoveredT1,T18,T14
11CoveredT1,T18,T14

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T18,T14
10CoveredT1,T2,T3
11CoveredT1,T18,T14

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T18,T14
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T18,T14
11CoveredT1,T18,T14

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT49,T65,T41
10CoveredT1,T18,T14
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T18,T14
10Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T18,T14
10Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T18,T14
10CoveredT1,T18,T14

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
Line No.TotalCoveredPercent
Branches 22 22 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T18,T14


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T18,T14


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T18,T14


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T18,T14


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T18,T14


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T18,T14


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T18,T14
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T18,T14
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T18,T14
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T18,T14
0 Covered T1,T2,T3


191 if (!rst_ni) begin -1- 192 prio_mask_q <= '0; ==> 193 end else begin 194 prio_mask_q <= prio_mask_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 12 80.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 12 80.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 387955770 387167133 0 0
CheckNGreaterZero_A 1056 1056 0 0
GntImpliesReady_A 387955770 2239952 0 0
GntImpliesValid_A 387955770 2239952 0 0
GrantKnown_A 387955770 387167133 0 0
IdxKnown_A 387955770 387167133 0 0
IndexIsCorrect_A 387955770 2239952 0 0
LockArbDecision_A 387955770 0 0 0
NoReadyValidNoGrant_A 387955770 288235948 0 0
ReadyAndValidImplyGrant_A 387955770 2239952 0 0
ReqAndReadyImplyGrant_A 387955770 2239952 0 0
ReqImpliesValid_A 387955770 94409492 0 0
ReqStaysHighUntilGranted0_M 387955770 0 0 0
RoundRobin_A 387955770 0 0 1051
ValidKnown_A 387955770 387167133 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1056 1056 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T14 1 1 0 0
T16 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 2239952 0 0
T1 2386 70 0 0
T2 1619 0 0 0
T3 2624 0 0 0
T7 3618 0 0 0
T8 758 0 0 0
T14 57474 322 0 0
T15 0 13 0 0
T16 2778 0 0 0
T18 1453 69 0 0
T19 1592 0 0 0
T20 1905 70 0 0
T22 0 460 0 0
T26 0 5 0 0
T27 0 18 0 0
T28 0 8 0 0
T59 0 406 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 2239952 0 0
T1 2386 70 0 0
T2 1619 0 0 0
T3 2624 0 0 0
T7 3618 0 0 0
T8 758 0 0 0
T14 57474 322 0 0
T15 0 13 0 0
T16 2778 0 0 0
T18 1453 69 0 0
T19 1592 0 0 0
T20 1905 70 0 0
T22 0 460 0 0
T26 0 5 0 0
T27 0 18 0 0
T28 0 8 0 0
T59 0 406 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 2239952 0 0
T1 2386 70 0 0
T2 1619 0 0 0
T3 2624 0 0 0
T7 3618 0 0 0
T8 758 0 0 0
T14 57474 322 0 0
T15 0 13 0 0
T16 2778 0 0 0
T18 1453 69 0 0
T19 1592 0 0 0
T20 1905 70 0 0
T22 0 460 0 0
T26 0 5 0 0
T27 0 18 0 0
T28 0 8 0 0
T59 0 406 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 0 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 288235948 0 0
T1 2386 432 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 5097 0 0
T16 2778 2678 0 0
T18 1453 451 0 0
T19 1592 1428 0 0
T20 1905 438 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 2239952 0 0
T1 2386 70 0 0
T2 1619 0 0 0
T3 2624 0 0 0
T7 3618 0 0 0
T8 758 0 0 0
T14 57474 322 0 0
T15 0 13 0 0
T16 2778 0 0 0
T18 1453 69 0 0
T19 1592 0 0 0
T20 1905 70 0 0
T22 0 460 0 0
T26 0 5 0 0
T27 0 18 0 0
T28 0 8 0 0
T59 0 406 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 2239952 0 0
T1 2386 70 0 0
T2 1619 0 0 0
T3 2624 0 0 0
T7 3618 0 0 0
T8 758 0 0 0
T14 57474 322 0 0
T15 0 13 0 0
T16 2778 0 0 0
T18 1453 69 0 0
T19 1592 0 0 0
T20 1905 70 0 0
T22 0 460 0 0
T26 0 5 0 0
T27 0 18 0 0
T28 0 8 0 0
T59 0 406 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 94409492 0 0
T1 2386 1879 0 0
T2 1619 0 0 0
T3 2624 0 0 0
T7 3618 0 0 0
T8 758 0 0 0
T14 57474 52286 0 0
T15 0 63456 0 0
T16 2778 0 0 0
T18 1453 925 0 0
T19 1592 0 0 0
T20 1905 1399 0 0
T22 0 185070 0 0
T26 0 1114 0 0
T27 0 4193 0 0
T28 0 1073 0 0
T59 0 63244 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 0 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 0 0 1051

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00

61 logic unused_req_chk; 62 unreachable assign unused_req_chk = req_chk_i; 63 64 `ASSERT_INIT(CheckNGreaterZero_A, N > 0) 65 66 // this case is basically just a bypass 67 if (N == 1) begin : gen_degenerate_case 68 69 assign valid_o = req_i[0]; 70 assign data_o = data_i[0]; 71 assign gnt_o[0] = valid_o & ready_i; 72 assign idx_o = '0; 73 74 end else begin : gen_normal_case 75 76 // align to powers of 2 for simplicity 77 // a full binary tree with N levels has 2**N + 2**N-1 nodes 78 logic [2**(IdxW+1)-2:0] req_tree; 79 logic [2**(IdxW+1)-2:0] prio_tree; 80 logic [2**(IdxW+1)-2:0] sel_tree; 81 logic [2**(IdxW+1)-2:0] mask_tree; 82 logic [2**(IdxW+1)-2:0][IdxW-1:0] idx_tree; 83 logic [2**(IdxW+1)-2:0][DW-1:0] data_tree; 84 logic [N-1:0] prio_mask_d, prio_mask_q; 85 86 for (genvar level = 0; level < IdxW+1; level++) begin : gen_tree 87 // 88 // level+1 C0 C1 <- "Base1" points to the first node on "level+1", 89 // \ / these nodes are the children of the nodes one level below 90 // level Pa <- "Base0", points to the first node on "level", 91 // these nodes are the parents of the nodes one level above 92 // 93 // hence we have the following indices for the Pa, C0, C1 nodes: 94 // Pa = 2**level - 1 + offset = Base0 + offset 95 // C0 = 2**(level+1) - 1 + 2*offset = Base1 + 2*offset 96 // C1 = 2**(level+1) - 1 + 2*offset + 1 = Base1 + 2*offset + 1 97 // 98 localparam int Base0 = (2**level)-1; 99 localparam int Base1 = (2**(level+1))-1; 100 101 for (genvar offset = 0; offset < 2**level; offset++) begin : gen_level 102 localparam int Pa = Base0 + offset; 103 localparam int C0 = Base1 + 2*offset; 104 localparam int C1 = Base1 + 2*offset + 1; 105 106 // this assigns the gated interrupt source signals, their 107 // corresponding IDs and priorities to the tree leafs 108 if (level == IdxW) begin : gen_leafs 109 if (offset < N) begin : gen_assign 110 // forward path (requests and data) 111 // all requests inputs are assigned to the request tree 112 2/2 assign req_tree[Pa] = req_i[offset]; Tests: T1 T2 T3  | T1 T2 T3  113 // we basically split the incoming request vector into two halves with the following 114 // priority assignment. the prio_mask_q register contains a prefix sum that has been 115 // computed using the last winning index, and hence masks out all requests at offsets 116 // lower or equal the previously granted index. hence, all higher indices are considered 117 // first in the arbitration tree nodes below, before considering the lower indices. 118 2/2 assign prio_tree[Pa] = req_i[offset] & prio_mask_q[offset]; Tests: T1 T2 T3  | T1 T2 T3  119 // input for the index muxes (used to compute the winner index) 120 assign idx_tree[Pa] = offset; 121 // input for the data muxes 122 2/2 assign data_tree[Pa] = data_i[offset]; Tests: T1 T2 T3  | T1 T2 T3  123 124 // backward path (grants and prefix sum) 125 // grant if selected, ready and request asserted 126 2/2 assign gnt_o[offset] = req_i[offset] & sel_tree[Pa] & ready_i; Tests: T1 T2 T3  | T1 T2 T3  127 // only update mask if there is a valid request 128 2/2 assign prio_mask_d[offset] = (|req_i) ? Tests: T1 T2 T3  | T1 T2 T3  129 mask_tree[Pa] | sel_tree[Pa] & ~ready_i : 130 prio_mask_q[offset]; 131 end else begin : gen_tie_off 132 // forward path 133 assign req_tree[Pa] = '0; 134 assign prio_tree[Pa] = '0; 135 assign idx_tree[Pa] = '0; 136 assign data_tree[Pa] = '0; 137 logic unused_sigs; 138 assign unused_sigs = ^{mask_tree[Pa], 139 sel_tree[Pa]}; 140 end 141 // this creates the node assignments 142 end else begin : gen_nodes 143 // local helper variable 144 logic sel; 145 146 // forward path (requests and data) 147 // each node looks at its two children, and selects the one with higher priority 148 1/1 assign sel = ~req_tree[C0] | ~prio_tree[C0] & prio_tree[C1]; Tests: T1 T2 T3  149 // propagate requests 150 1/1 assign req_tree[Pa] = req_tree[C0] | req_tree[C1]; Tests: T1 T2 T3  151 1/1 assign prio_tree[Pa] = prio_tree[C1] | prio_tree[C0]; Tests: T1 T2 T3  152 // data and index muxes 153 // Note: these ternaries have triggered a synthesis bug in Vivado versions older 154 // than 2020.2. If the problem resurfaces again, have a look at issue #1408. 155 1/1 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; Tests: T1 T2 T3  156 1/1 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; Tests: T1 T2 T3  157 158 // backward path (grants and prefix sum) 159 // this propagates the selction index back and computes a hot one mask 160 1/1 assign sel_tree[C0] = sel_tree[Pa] & ~sel; Tests: T1 T2 T3  161 1/1 assign sel_tree[C1] = sel_tree[Pa] & sel; Tests: T1 T2 T3  162 // this performs a prefix sum for masking the input requests in the next cycle 163 unreachable assign mask_tree[C0] = mask_tree[Pa]; 164 1/1 assign mask_tree[C1] = mask_tree[Pa] | sel_tree[C0]; Tests: T1 T2 T3  165 end 166 end : gen_level 167 end : gen_tree 168 169 // the results can be found at the tree root 170 if (EnDataPort) begin : gen_data_port 171 1/1 assign data_o = data_tree[0]; Tests: T1 T2 T3  172 end else begin : gen_no_dataport 173 logic [DW-1:0] unused_data; 174 assign unused_data = data_tree[0]; 175 assign data_o = '1; 176 end 177 178 // This index is unused. 179 logic unused_prio_tree; 180 1/1 assign unused_prio_tree = prio_tree[0]; Tests: T1 T2 T3  181 182 1/1 assign idx_o = idx_tree[0]; Tests: T1 T2 T3  183 1/1 assign valid_o = req_tree[0]; Tests: T1 T2 T3  184 185 // the select tree computes a hot one signal that indicates which request is currently selected 186 assign sel_tree[0] = 1'b1; 187 // the mask tree is basically a prefix sum of the hot one select signal computed above 188 assign mask_tree[0] = 1'b0; 189 190 always_ff @(posedge clk_i or negedge rst_ni) begin : p_mask_reg 191 1/1 if (!rst_ni) begin Tests: T1 T2 T3  192 1/1 prio_mask_q <= '0; Tests: T1 T2 T3  193 end else begin 194 1/1 prio_mask_q <= prio_mask_d; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
TotalCoveredPercent
Conditions514588.24
Logical514588.24
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT18,T20,T27
11CoveredT18,T20,T26

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011CoveredT81
101Not Covered
110CoveredT18,T20,T26
111CoveredT18,T20,T26

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT18,T20,T26
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT18,T20,T26
01CoveredT18,T20,T26
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT18,T20,T26
11CoveredT18,T20,T26

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT18,T20,T26

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT18,T20,T26
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT18,T20,T26

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


191 if (!rst_ni) begin -1- 192 prio_mask_q <= '0; ==> 193 end else begin 194 prio_mask_q <= prio_mask_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 387955770 387167133 0 0
CheckNGreaterZero_A 1056 1056 0 0
GntImpliesReady_A 387955770 15580159 0 0
GntImpliesValid_A 387955770 15580159 0 0
GrantKnown_A 387955770 387167133 0 0
IdxKnown_A 387955770 387167133 0 0
IndexIsCorrect_A 387955770 15580159 0 0
LockArbDecision_A 387955699 15580159 0 0
NoReadyValidNoGrant_A 387955770 356006773 0 0
ReadyAndValidImplyGrant_A 387955770 15580159 0 0
ReqAndReadyImplyGrant_A 387955770 15580159 0 0
ReqImpliesValid_A 387955770 31160326 0 0
ReqStaysHighUntilGranted0_M 387867744 15580111 0 0
RoundRobin_A 387955770 0 0 1051
ValidKnown_A 387955770 387167133 0 0
gen_data_port_assertion.DataFlow_A 387955770 15580159 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1056 1056 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T14 1 1 0 0
T16 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 15580159 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 15580159 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 15580159 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955699 15580159 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 356006773 0 0
T1 2386 2251 0 0
T2 1619 1500 0 0
T3 2624 2465 0 0
T7 3618 3500 0 0
T8 758 628 0 0
T14 57474 57323 0 0
T16 2778 2614 0 0
T18 1453 1170 0 0
T19 1592 1300 0 0
T20 1905 1629 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 15580159 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 15580159 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 31160326 0 0
T1 2386 64 0 0
T2 1619 64 0 0
T3 2624 64 0 0
T7 3618 64 0 0
T8 758 66 0 0
T14 57474 64 0 0
T16 2778 64 0 0
T18 1453 210 0 0
T19 1592 128 0 0
T20 1905 212 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 387867744 15580111 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 0 0 1051

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 15580159 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00

61 logic unused_req_chk; 62 unreachable assign unused_req_chk = req_chk_i; 63 64 `ASSERT_INIT(CheckNGreaterZero_A, N > 0) 65 66 // this case is basically just a bypass 67 if (N == 1) begin : gen_degenerate_case 68 69 assign valid_o = req_i[0]; 70 assign data_o = data_i[0]; 71 assign gnt_o[0] = valid_o & ready_i; 72 assign idx_o = '0; 73 74 end else begin : gen_normal_case 75 76 // align to powers of 2 for simplicity 77 // a full binary tree with N levels has 2**N + 2**N-1 nodes 78 logic [2**(IdxW+1)-2:0] req_tree; 79 logic [2**(IdxW+1)-2:0] prio_tree; 80 logic [2**(IdxW+1)-2:0] sel_tree; 81 logic [2**(IdxW+1)-2:0] mask_tree; 82 logic [2**(IdxW+1)-2:0][IdxW-1:0] idx_tree; 83 logic [2**(IdxW+1)-2:0][DW-1:0] data_tree; 84 logic [N-1:0] prio_mask_d, prio_mask_q; 85 86 for (genvar level = 0; level < IdxW+1; level++) begin : gen_tree 87 // 88 // level+1 C0 C1 <- "Base1" points to the first node on "level+1", 89 // \ / these nodes are the children of the nodes one level below 90 // level Pa <- "Base0", points to the first node on "level", 91 // these nodes are the parents of the nodes one level above 92 // 93 // hence we have the following indices for the Pa, C0, C1 nodes: 94 // Pa = 2**level - 1 + offset = Base0 + offset 95 // C0 = 2**(level+1) - 1 + 2*offset = Base1 + 2*offset 96 // C1 = 2**(level+1) - 1 + 2*offset + 1 = Base1 + 2*offset + 1 97 // 98 localparam int Base0 = (2**level)-1; 99 localparam int Base1 = (2**(level+1))-1; 100 101 for (genvar offset = 0; offset < 2**level; offset++) begin : gen_level 102 localparam int Pa = Base0 + offset; 103 localparam int C0 = Base1 + 2*offset; 104 localparam int C1 = Base1 + 2*offset + 1; 105 106 // this assigns the gated interrupt source signals, their 107 // corresponding IDs and priorities to the tree leafs 108 if (level == IdxW) begin : gen_leafs 109 if (offset < N) begin : gen_assign 110 // forward path (requests and data) 111 // all requests inputs are assigned to the request tree 112 2/2 assign req_tree[Pa] = req_i[offset]; Tests: T1 T2 T3  | T1 T2 T3  113 // we basically split the incoming request vector into two halves with the following 114 // priority assignment. the prio_mask_q register contains a prefix sum that has been 115 // computed using the last winning index, and hence masks out all requests at offsets 116 // lower or equal the previously granted index. hence, all higher indices are considered 117 // first in the arbitration tree nodes below, before considering the lower indices. 118 2/2 assign prio_tree[Pa] = req_i[offset] & prio_mask_q[offset]; Tests: T1 T2 T3  | T1 T2 T3  119 // input for the index muxes (used to compute the winner index) 120 assign idx_tree[Pa] = offset; 121 // input for the data muxes 122 2/2 assign data_tree[Pa] = data_i[offset]; Tests: T1 T2 T3  | T1 T2 T3  123 124 // backward path (grants and prefix sum) 125 // grant if selected, ready and request asserted 126 2/2 assign gnt_o[offset] = req_i[offset] & sel_tree[Pa] & ready_i; Tests: T1 T2 T3  | T1 T2 T3  127 // only update mask if there is a valid request 128 2/2 assign prio_mask_d[offset] = (|req_i) ? Tests: T1 T2 T3  | T1 T2 T3  129 mask_tree[Pa] | sel_tree[Pa] & ~ready_i : 130 prio_mask_q[offset]; 131 end else begin : gen_tie_off 132 // forward path 133 assign req_tree[Pa] = '0; 134 assign prio_tree[Pa] = '0; 135 assign idx_tree[Pa] = '0; 136 assign data_tree[Pa] = '0; 137 logic unused_sigs; 138 assign unused_sigs = ^{mask_tree[Pa], 139 sel_tree[Pa]}; 140 end 141 // this creates the node assignments 142 end else begin : gen_nodes 143 // local helper variable 144 logic sel; 145 146 // forward path (requests and data) 147 // each node looks at its two children, and selects the one with higher priority 148 1/1 assign sel = ~req_tree[C0] | ~prio_tree[C0] & prio_tree[C1]; Tests: T1 T2 T3  149 // propagate requests 150 1/1 assign req_tree[Pa] = req_tree[C0] | req_tree[C1]; Tests: T1 T2 T3  151 1/1 assign prio_tree[Pa] = prio_tree[C1] | prio_tree[C0]; Tests: T1 T2 T3  152 // data and index muxes 153 // Note: these ternaries have triggered a synthesis bug in Vivado versions older 154 // than 2020.2. If the problem resurfaces again, have a look at issue #1408. 155 1/1 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; Tests: T1 T2 T3  156 1/1 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; Tests: T1 T2 T3  157 158 // backward path (grants and prefix sum) 159 // this propagates the selction index back and computes a hot one mask 160 1/1 assign sel_tree[C0] = sel_tree[Pa] & ~sel; Tests: T1 T2 T3  161 1/1 assign sel_tree[C1] = sel_tree[Pa] & sel; Tests: T1 T2 T3  162 // this performs a prefix sum for masking the input requests in the next cycle 163 unreachable assign mask_tree[C0] = mask_tree[Pa]; 164 1/1 assign mask_tree[C1] = mask_tree[Pa] | sel_tree[C0]; Tests: T1 T2 T3  165 end 166 end : gen_level 167 end : gen_tree 168 169 // the results can be found at the tree root 170 if (EnDataPort) begin : gen_data_port 171 1/1 assign data_o = data_tree[0]; Tests: T1 T2 T3  172 end else begin : gen_no_dataport 173 logic [DW-1:0] unused_data; 174 assign unused_data = data_tree[0]; 175 assign data_o = '1; 176 end 177 178 // This index is unused. 179 logic unused_prio_tree; 180 1/1 assign unused_prio_tree = prio_tree[0]; Tests: T1 T2 T3  181 182 1/1 assign idx_o = idx_tree[0]; Tests: T1 T2 T3  183 1/1 assign valid_o = req_tree[0]; Tests: T1 T2 T3  184 185 // the select tree computes a hot one signal that indicates which request is currently selected 186 assign sel_tree[0] = 1'b1; 187 // the mask tree is basically a prefix sum of the hot one select signal computed above 188 assign mask_tree[0] = 1'b0; 189 190 always_ff @(posedge clk_i or negedge rst_ni) begin : p_mask_reg 191 1/1 if (!rst_ni) begin Tests: T1 T2 T3  192 1/1 prio_mask_q <= '0; Tests: T1 T2 T3  193 end else begin 194 1/1 prio_mask_q <= prio_mask_d; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
TotalCoveredPercent
Conditions514894.12
Logical514894.12
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT18,T20,T27
11CoveredT18,T20,T26

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT81
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT81
110CoveredT18,T20,T26
111CoveredT18,T20,T26

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT18,T20,T26
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT18,T20,T26
01CoveredT18,T20,T26
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT18,T20,T26
11CoveredT18,T20,T26

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT81
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT81
10CoveredT1,T2,T3
11CoveredT18,T20,T26

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT18,T20,T26
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT18,T20,T26

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


191 if (!rst_ni) begin -1- 192 prio_mask_q <= '0; ==> 193 end else begin 194 prio_mask_q <= prio_mask_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 387955770 387167133 0 0
CheckNGreaterZero_A 1056 1056 0 0
GntImpliesReady_A 387955770 15580193 0 0
GntImpliesValid_A 387955770 15580193 0 0
GrantKnown_A 387955770 387167133 0 0
IdxKnown_A 387955770 387167133 0 0
IndexIsCorrect_A 387955770 15580193 0 0
LockArbDecision_A 387955699 15580159 0 0
NoReadyValidNoGrant_A 387955770 356006739 0 0
ReadyAndValidImplyGrant_A 387955770 15580193 0 0
ReqAndReadyImplyGrant_A 387955770 15580193 0 0
ReqImpliesValid_A 387955770 31160394 0 0
ReqStaysHighUntilGranted0_M 387867744 15580111 0 0
RoundRobin_A 387955770 0 0 1051
ValidKnown_A 387955770 387167133 0 0
gen_data_port_assertion.DataFlow_A 387955770 15580193 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1056 1056 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T14 1 1 0 0
T16 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 15580193 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 15580193 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 15580193 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955699 15580159 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 356006739 0 0
T1 2386 2251 0 0
T2 1619 1500 0 0
T3 2624 2465 0 0
T7 3618 3500 0 0
T8 758 628 0 0
T14 57474 57323 0 0
T16 2778 2614 0 0
T18 1453 1170 0 0
T19 1592 1300 0 0
T20 1905 1629 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 15580193 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 15580193 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 31160394 0 0
T1 2386 64 0 0
T2 1619 64 0 0
T3 2624 64 0 0
T7 3618 64 0 0
T8 758 66 0 0
T14 57474 64 0 0
T16 2778 64 0 0
T18 1453 210 0 0
T19 1592 128 0 0
T20 1905 212 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 387867744 15580111 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 0 0 1051

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 15580193 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
TOTAL2323100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12600
CONT_ASSIGN12600
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00

61 logic unused_req_chk; 62 unreachable assign unused_req_chk = req_chk_i; 63 64 `ASSERT_INIT(CheckNGreaterZero_A, N > 0) 65 66 // this case is basically just a bypass 67 if (N == 1) begin : gen_degenerate_case 68 69 assign valid_o = req_i[0]; 70 assign data_o = data_i[0]; 71 assign gnt_o[0] = valid_o & ready_i; 72 assign idx_o = '0; 73 74 end else begin : gen_normal_case 75 76 // align to powers of 2 for simplicity 77 // a full binary tree with N levels has 2**N + 2**N-1 nodes 78 logic [2**(IdxW+1)-2:0] req_tree; 79 logic [2**(IdxW+1)-2:0] prio_tree; 80 logic [2**(IdxW+1)-2:0] sel_tree; 81 logic [2**(IdxW+1)-2:0] mask_tree; 82 logic [2**(IdxW+1)-2:0][IdxW-1:0] idx_tree; 83 logic [2**(IdxW+1)-2:0][DW-1:0] data_tree; 84 logic [N-1:0] prio_mask_d, prio_mask_q; 85 86 for (genvar level = 0; level < IdxW+1; level++) begin : gen_tree 87 // 88 // level+1 C0 C1 <- "Base1" points to the first node on "level+1", 89 // \ / these nodes are the children of the nodes one level below 90 // level Pa <- "Base0", points to the first node on "level", 91 // these nodes are the parents of the nodes one level above 92 // 93 // hence we have the following indices for the Pa, C0, C1 nodes: 94 // Pa = 2**level - 1 + offset = Base0 + offset 95 // C0 = 2**(level+1) - 1 + 2*offset = Base1 + 2*offset 96 // C1 = 2**(level+1) - 1 + 2*offset + 1 = Base1 + 2*offset + 1 97 // 98 localparam int Base0 = (2**level)-1; 99 localparam int Base1 = (2**(level+1))-1; 100 101 for (genvar offset = 0; offset < 2**level; offset++) begin : gen_level 102 localparam int Pa = Base0 + offset; 103 localparam int C0 = Base1 + 2*offset; 104 localparam int C1 = Base1 + 2*offset + 1; 105 106 // this assigns the gated interrupt source signals, their 107 // corresponding IDs and priorities to the tree leafs 108 if (level == IdxW) begin : gen_leafs 109 if (offset < N) begin : gen_assign 110 // forward path (requests and data) 111 // all requests inputs are assigned to the request tree 112 2/2 assign req_tree[Pa] = req_i[offset]; Tests: T1 T2 T3  | T1 T2 T3  113 // we basically split the incoming request vector into two halves with the following 114 // priority assignment. the prio_mask_q register contains a prefix sum that has been 115 // computed using the last winning index, and hence masks out all requests at offsets 116 // lower or equal the previously granted index. hence, all higher indices are considered 117 // first in the arbitration tree nodes below, before considering the lower indices. 118 2/2 assign prio_tree[Pa] = req_i[offset] & prio_mask_q[offset]; Tests: T1 T2 T3  | T1 T2 T3  119 // input for the index muxes (used to compute the winner index) 120 assign idx_tree[Pa] = offset; 121 // input for the data muxes 122 2/2 assign data_tree[Pa] = data_i[offset]; Tests: T1 T2 T3  | T1 T2 T3  123 124 // backward path (grants and prefix sum) 125 // grant if selected, ready and request asserted 126 unreachable assign gnt_o[offset] = req_i[offset] & sel_tree[Pa] & ready_i; 127 // only update mask if there is a valid request 128 2/2 assign prio_mask_d[offset] = (|req_i) ? Tests: T1 T2 T3  | T1 T2 T3  129 mask_tree[Pa] | sel_tree[Pa] & ~ready_i : 130 prio_mask_q[offset]; 131 end else begin : gen_tie_off 132 // forward path 133 assign req_tree[Pa] = '0; 134 assign prio_tree[Pa] = '0; 135 assign idx_tree[Pa] = '0; 136 assign data_tree[Pa] = '0; 137 logic unused_sigs; 138 assign unused_sigs = ^{mask_tree[Pa], 139 sel_tree[Pa]}; 140 end 141 // this creates the node assignments 142 end else begin : gen_nodes 143 // local helper variable 144 logic sel; 145 146 // forward path (requests and data) 147 // each node looks at its two children, and selects the one with higher priority 148 1/1 assign sel = ~req_tree[C0] | ~prio_tree[C0] & prio_tree[C1]; Tests: T1 T2 T3  149 // propagate requests 150 1/1 assign req_tree[Pa] = req_tree[C0] | req_tree[C1]; Tests: T1 T2 T3  151 1/1 assign prio_tree[Pa] = prio_tree[C1] | prio_tree[C0]; Tests: T1 T2 T3  152 // data and index muxes 153 // Note: these ternaries have triggered a synthesis bug in Vivado versions older 154 // than 2020.2. If the problem resurfaces again, have a look at issue #1408. 155 1/1 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; Tests: T1 T2 T3  156 1/1 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; Tests: T1 T2 T3  157 158 // backward path (grants and prefix sum) 159 // this propagates the selction index back and computes a hot one mask 160 1/1 assign sel_tree[C0] = sel_tree[Pa] & ~sel; Tests: T1 T2 T3  161 1/1 assign sel_tree[C1] = sel_tree[Pa] & sel; Tests: T1 T2 T3  162 // this performs a prefix sum for masking the input requests in the next cycle 163 unreachable assign mask_tree[C0] = mask_tree[Pa]; 164 1/1 assign mask_tree[C1] = mask_tree[Pa] | sel_tree[C0]; Tests: T1 T2 T3  165 end 166 end : gen_level 167 end : gen_tree 168 169 // the results can be found at the tree root 170 if (EnDataPort) begin : gen_data_port 171 1/1 assign data_o = data_tree[0]; Tests: T1 T2 T3  172 end else begin : gen_no_dataport 173 logic [DW-1:0] unused_data; 174 assign unused_data = data_tree[0]; 175 assign data_o = '1; 176 end 177 178 // This index is unused. 179 logic unused_prio_tree; 180 1/1 assign unused_prio_tree = prio_tree[0]; Tests: T1 T2 T3  181 182 1/1 assign idx_o = idx_tree[0]; Tests: T1 T2 T3  183 1/1 assign valid_o = req_tree[0]; Tests: T1 T2 T3  184 185 // the select tree computes a hot one signal that indicates which request is currently selected 186 assign sel_tree[0] = 1'b1; 187 // the mask tree is basically a prefix sum of the hot one select signal computed above 188 assign mask_tree[0] = 1'b0; 189 190 always_ff @(posedge clk_i or negedge rst_ni) begin : p_mask_reg 191 1/1 if (!rst_ni) begin Tests: T1 T2 T3  192 1/1 prio_mask_q <= '0; Tests: T1 T2 T3  193 end else begin 194 1/1 prio_mask_q <= prio_mask_d; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
TotalCoveredPercent
Conditions434297.67
Logical434297.67
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT18,T20,T27
11CoveredT18,T20,T26

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Unreachable
101UnreachableT11,T45,T41
110CoveredT1,T2,T3
111UnreachableT1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Unreachable
101UnreachableT11,T45,T41
110CoveredT18,T20,T26
111UnreachableT18,T20,T26

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT18,T20,T26
10UnreachableT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT18,T20,T26
01CoveredT18,T20,T26
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT18,T20,T26
11CoveredT18,T20,T26

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T45,T41
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT11,T45,T41
10CoveredT1,T2,T3
11CoveredT18,T20,T26

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT18,T20,T26
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT18,T20,T26

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


191 if (!rst_ni) begin -1- 192 prio_mask_q <= '0; ==> 193 end else begin 194 prio_mask_q <= prio_mask_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 387955770 387167133 0 0
CheckNGreaterZero_A 1056 1056 0 0
GntImpliesReady_A 387955770 16673450 0 0
GntImpliesValid_A 387955770 16673450 0 0
GrantKnown_A 387955770 387167133 0 0
IdxKnown_A 387955770 387167133 0 0
IndexIsCorrect_A 387955770 16673450 0 0
LockArbDecision_A 387955771 16673450 0 0
NoReadyValidNoGrant_A 387955770 353820224 0 0
ReadyAndValidImplyGrant_A 387955770 16673450 0 0
ReqAndReadyImplyGrant_A 387955770 16673450 0 0
ReqImpliesValid_A 387955770 33346909 0 0
ReqStaysHighUntilGranted0_M 387955771 16673450 0 0
RoundRobin_A 387955770 0 0 1051
ValidKnown_A 387955770 387167133 0 0
gen_data_port_assertion.DataFlow_A 387955770 16673450 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1056 1056 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T14 1 1 0 0
T16 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 16673450 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 16673450 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 16673450 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955771 16673450 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 353820224 0 0
T1 2386 2251 0 0
T2 1619 1500 0 0
T3 2624 2465 0 0
T7 3618 3500 0 0
T8 758 628 0 0
T14 57474 57323 0 0
T16 2778 2614 0 0
T18 1453 1170 0 0
T19 1592 1300 0 0
T20 1905 1629 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 16673450 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 16673450 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 33346909 0 0
T1 2386 64 0 0
T2 1619 64 0 0
T3 2624 64 0 0
T7 3618 64 0 0
T8 758 66 0 0
T14 57474 64 0 0
T16 2778 64 0 0
T18 1453 210 0 0
T19 1592 128 0 0
T20 1905 212 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955771 16673450 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 0 0 1051

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 16673450 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
TOTAL2323100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12600
CONT_ASSIGN12600
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00

61 logic unused_req_chk; 62 unreachable assign unused_req_chk = req_chk_i; 63 64 `ASSERT_INIT(CheckNGreaterZero_A, N > 0) 65 66 // this case is basically just a bypass 67 if (N == 1) begin : gen_degenerate_case 68 69 assign valid_o = req_i[0]; 70 assign data_o = data_i[0]; 71 assign gnt_o[0] = valid_o & ready_i; 72 assign idx_o = '0; 73 74 end else begin : gen_normal_case 75 76 // align to powers of 2 for simplicity 77 // a full binary tree with N levels has 2**N + 2**N-1 nodes 78 logic [2**(IdxW+1)-2:0] req_tree; 79 logic [2**(IdxW+1)-2:0] prio_tree; 80 logic [2**(IdxW+1)-2:0] sel_tree; 81 logic [2**(IdxW+1)-2:0] mask_tree; 82 logic [2**(IdxW+1)-2:0][IdxW-1:0] idx_tree; 83 logic [2**(IdxW+1)-2:0][DW-1:0] data_tree; 84 logic [N-1:0] prio_mask_d, prio_mask_q; 85 86 for (genvar level = 0; level < IdxW+1; level++) begin : gen_tree 87 // 88 // level+1 C0 C1 <- "Base1" points to the first node on "level+1", 89 // \ / these nodes are the children of the nodes one level below 90 // level Pa <- "Base0", points to the first node on "level", 91 // these nodes are the parents of the nodes one level above 92 // 93 // hence we have the following indices for the Pa, C0, C1 nodes: 94 // Pa = 2**level - 1 + offset = Base0 + offset 95 // C0 = 2**(level+1) - 1 + 2*offset = Base1 + 2*offset 96 // C1 = 2**(level+1) - 1 + 2*offset + 1 = Base1 + 2*offset + 1 97 // 98 localparam int Base0 = (2**level)-1; 99 localparam int Base1 = (2**(level+1))-1; 100 101 for (genvar offset = 0; offset < 2**level; offset++) begin : gen_level 102 localparam int Pa = Base0 + offset; 103 localparam int C0 = Base1 + 2*offset; 104 localparam int C1 = Base1 + 2*offset + 1; 105 106 // this assigns the gated interrupt source signals, their 107 // corresponding IDs and priorities to the tree leafs 108 if (level == IdxW) begin : gen_leafs 109 if (offset < N) begin : gen_assign 110 // forward path (requests and data) 111 // all requests inputs are assigned to the request tree 112 2/2 assign req_tree[Pa] = req_i[offset]; Tests: T1 T2 T3  | T1 T2 T3  113 // we basically split the incoming request vector into two halves with the following 114 // priority assignment. the prio_mask_q register contains a prefix sum that has been 115 // computed using the last winning index, and hence masks out all requests at offsets 116 // lower or equal the previously granted index. hence, all higher indices are considered 117 // first in the arbitration tree nodes below, before considering the lower indices. 118 2/2 assign prio_tree[Pa] = req_i[offset] & prio_mask_q[offset]; Tests: T1 T2 T3  | T1 T2 T3  119 // input for the index muxes (used to compute the winner index) 120 assign idx_tree[Pa] = offset; 121 // input for the data muxes 122 2/2 assign data_tree[Pa] = data_i[offset]; Tests: T1 T2 T3  | T1 T2 T3  123 124 // backward path (grants and prefix sum) 125 // grant if selected, ready and request asserted 126 unreachable assign gnt_o[offset] = req_i[offset] & sel_tree[Pa] & ready_i; 127 // only update mask if there is a valid request 128 2/2 assign prio_mask_d[offset] = (|req_i) ? Tests: T1 T2 T3  | T1 T2 T3  129 mask_tree[Pa] | sel_tree[Pa] & ~ready_i : 130 prio_mask_q[offset]; 131 end else begin : gen_tie_off 132 // forward path 133 assign req_tree[Pa] = '0; 134 assign prio_tree[Pa] = '0; 135 assign idx_tree[Pa] = '0; 136 assign data_tree[Pa] = '0; 137 logic unused_sigs; 138 assign unused_sigs = ^{mask_tree[Pa], 139 sel_tree[Pa]}; 140 end 141 // this creates the node assignments 142 end else begin : gen_nodes 143 // local helper variable 144 logic sel; 145 146 // forward path (requests and data) 147 // each node looks at its two children, and selects the one with higher priority 148 1/1 assign sel = ~req_tree[C0] | ~prio_tree[C0] & prio_tree[C1]; Tests: T1 T2 T3  149 // propagate requests 150 1/1 assign req_tree[Pa] = req_tree[C0] | req_tree[C1]; Tests: T1 T2 T3  151 1/1 assign prio_tree[Pa] = prio_tree[C1] | prio_tree[C0]; Tests: T1 T2 T3  152 // data and index muxes 153 // Note: these ternaries have triggered a synthesis bug in Vivado versions older 154 // than 2020.2. If the problem resurfaces again, have a look at issue #1408. 155 1/1 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; Tests: T1 T2 T3  156 1/1 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; Tests: T1 T2 T3  157 158 // backward path (grants and prefix sum) 159 // this propagates the selction index back and computes a hot one mask 160 1/1 assign sel_tree[C0] = sel_tree[Pa] & ~sel; Tests: T1 T2 T3  161 1/1 assign sel_tree[C1] = sel_tree[Pa] & sel; Tests: T1 T2 T3  162 // this performs a prefix sum for masking the input requests in the next cycle 163 unreachable assign mask_tree[C0] = mask_tree[Pa]; 164 1/1 assign mask_tree[C1] = mask_tree[Pa] | sel_tree[C0]; Tests: T1 T2 T3  165 end 166 end : gen_level 167 end : gen_tree 168 169 // the results can be found at the tree root 170 if (EnDataPort) begin : gen_data_port 171 1/1 assign data_o = data_tree[0]; Tests: T1 T2 T3  172 end else begin : gen_no_dataport 173 logic [DW-1:0] unused_data; 174 assign unused_data = data_tree[0]; 175 assign data_o = '1; 176 end 177 178 // This index is unused. 179 logic unused_prio_tree; 180 1/1 assign unused_prio_tree = prio_tree[0]; Tests: T1 T2 T3  181 182 1/1 assign idx_o = idx_tree[0]; Tests: T1 T2 T3  183 1/1 assign valid_o = req_tree[0]; Tests: T1 T2 T3  184 185 // the select tree computes a hot one signal that indicates which request is currently selected 186 assign sel_tree[0] = 1'b1; 187 // the mask tree is basically a prefix sum of the hot one select signal computed above 188 assign mask_tree[0] = 1'b0; 189 190 always_ff @(posedge clk_i or negedge rst_ni) begin : p_mask_reg 191 1/1 if (!rst_ni) begin Tests: T1 T2 T3  192 1/1 prio_mask_q <= '0; Tests: T1 T2 T3  193 end else begin 194 1/1 prio_mask_q <= prio_mask_d; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
TotalCoveredPercent
Conditions434297.67
Logical434297.67
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT18,T20,T27
11CoveredT18,T20,T26

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Unreachable
101UnreachableT11,T45,T41
110CoveredT1,T2,T3
111UnreachableT1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Unreachable
101UnreachableT11,T45,T41
110CoveredT18,T20,T26
111UnreachableT18,T20,T26

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT18,T20,T26
10UnreachableT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT18,T20,T26
01CoveredT18,T20,T26
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT18,T20,T26
11CoveredT18,T20,T26

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T45,T41
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT11,T45,T41
10CoveredT1,T2,T3
11CoveredT18,T20,T26

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT18,T20,T26
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT18,T20,T26

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00


155 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


156 assign data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


128 assign prio_mask_d[offset] = (|req_i) ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


191 if (!rst_ni) begin -1- 192 prio_mask_q <= '0; ==> 193 end else begin 194 prio_mask_q <= prio_mask_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 387955770 387167133 0 0
CheckNGreaterZero_A 1056 1056 0 0
GntImpliesReady_A 387955770 16673450 0 0
GntImpliesValid_A 387955770 16673450 0 0
GrantKnown_A 387955770 387167133 0 0
IdxKnown_A 387955770 387167133 0 0
IndexIsCorrect_A 387955770 16673450 0 0
LockArbDecision_A 387955771 16673450 0 0
NoReadyValidNoGrant_A 387955770 353820224 0 0
ReadyAndValidImplyGrant_A 387955770 16673450 0 0
ReqAndReadyImplyGrant_A 387955770 16673450 0 0
ReqImpliesValid_A 387955770 33346909 0 0
ReqStaysHighUntilGranted0_M 387955771 16673450 0 0
RoundRobin_A 387955770 0 0 1051
ValidKnown_A 387955770 387167133 0 0
gen_data_port_assertion.DataFlow_A 387955770 16673450 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1056 1056 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T14 1 1 0 0
T16 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 16673450 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 16673450 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 16673450 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955771 16673450 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 353820224 0 0
T1 2386 2251 0 0
T2 1619 1500 0 0
T3 2624 2465 0 0
T7 3618 3500 0 0
T8 758 628 0 0
T14 57474 57323 0 0
T16 2778 2614 0 0
T18 1453 1170 0 0
T19 1592 1300 0 0
T20 1905 1629 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 16673450 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 16673450 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 33346909 0 0
T1 2386 64 0 0
T2 1619 64 0 0
T3 2624 64 0 0
T7 3618 64 0 0
T8 758 66 0 0
T14 57474 64 0 0
T16 2778 64 0 0
T18 1453 210 0 0
T19 1592 128 0 0
T20 1905 212 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955771 16673450 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 0 0 1051

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 16673450 0 0
T1 2386 32 0 0
T2 1619 32 0 0
T3 2624 32 0 0
T7 3618 32 0 0
T8 758 33 0 0
T14 57474 32 0 0
T16 2778 32 0 0
T18 1453 105 0 0
T19 1592 64 0 0
T20 1905 106 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%