Module Definition
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Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.22 100.00 88.89 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.22 100.00 88.89 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.87 100.00 91.51 100.00 97.83 100.00 gen_flash_cores[0].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.22 100.00 88.89 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.22 100.00 88.89 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.55 100.00 84.91 100.00 97.83 100.00 gen_flash_cores[1].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : flash_phy_erase
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS3933100.00
ALWAYS471717100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00

38 always_ff @(posedge clk_i or negedge rst_ni) begin 39 1/1 if (!rst_ni) begin Tests: T1 T2 T3  40 1/1 state_q <= StEraseIdle; Tests: T1 T2 T3  41 end else begin 42 1/1 state_q <= state_d; Tests: T1 T2 T3  43 end 44 end 45 46 always_comb begin 47 1/1 req_valid = 1'b0; Tests: T1 T2 T3  48 1/1 suspend_valid = 1'b0; Tests: T1 T2 T3  49 1/1 ack_o = 1'b0; Tests: T1 T2 T3  50 1/1 state_d = state_q; Tests: T1 T2 T3  51 52 1/1 unique case (state_q) Tests: T1 T2 T3  53 StEraseIdle: begin 54 1/1 req_valid = 1'b1; Tests: T1 T2 T3  55 56 1/1 if ((pg_erase_req_o || bk_erase_req_o) && ack_i) begin Tests: T1 T2 T3  57 1/1 state_d = StEraseBusy; Tests: T3 T15 T27  58 end MISSING_ELSE 59 end 60 61 StEraseBusy: begin 62 1/1 suspend_valid = '1; Tests: T3 T15 T27  63 64 1/1 if (suspend_req_i && ack_i) begin Tests: T3 T15 T27  65 1/1 state_d = StEraseSuspend; Tests: T15 T93 T71  66 1/1 end else if (done_i) begin Tests: T3 T15 T27  67 1/1 ack_o = 1'b1; Tests: T3 T15 T27  68 1/1 state_d = StEraseIdle; Tests: T3 T15 T27  69 end MISSING_ELSE 70 end 71 72 StEraseSuspend: begin 73 1/1 if (done_i) begin Tests: T15 T11 T93  74 1/1 ack_o = 1'b1; Tests: T15 T11 T93  75 1/1 state_d = StEraseIdle; Tests: T15 T11 T93  76 end MISSING_ELSE 77 end 78 79 default:; 80 endcase // unique case (state_q) 81 end 82 83 1/1 assign pg_erase_req_o = pg_erase_req_i & req_valid; Tests: T1 T2 T3  84 1/1 assign bk_erase_req_o = bk_erase_req_i & req_valid; Tests: T1 T2 T3  85 1/1 assign suspend_req_o = suspend_req_i & suspend_valid; Tests: T1 T2 T3 

Cond Coverage for Module : flash_phy_erase
TotalCoveredPercent
Conditions181688.89
Logical181688.89
Non-Logical00
Event00

 LINE       56
 EXPRESSION ((pg_erase_req_o || bk_erase_req_o) && ack_i)
             -----------------1----------------    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T15,T27

 LINE       56
 SUB-EXPRESSION (pg_erase_req_o || bk_erase_req_o)
                 -------1------    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT70,T71,T72
10CoveredT3,T15,T27

 LINE       64
 EXPRESSION (suspend_req_i && ack_i)
             ------1------    --2--
-1--2-StatusTests
01CoveredT3,T15,T27
10Not Covered
11CoveredT15,T93,T71

 LINE       83
 EXPRESSION (pg_erase_req_i & req_valid)
             -------1------   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T15,T27
11CoveredT3,T15,T27

 LINE       84
 EXPRESSION (bk_erase_req_i & req_valid)
             -------1------   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT70,T71,T72
11CoveredT70,T71,T72

 LINE       85
 EXPRESSION (suspend_req_i & suspend_valid)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT3,T15,T27
10CoveredT15,T93,T71
11CoveredT15,T93,T71

FSM Coverage for Module : flash_phy_erase
Summary for FSM :: state_q
TotalCoveredPercent
States 3 3 100.00 (Not included in score)
Transitions 4 4 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StEraseBusy 57 Covered T3,T15,T27
StEraseIdle 68 Covered T1,T2,T3
StEraseSuspend 65 Covered T15,T93,T71


transitionsLine No.CoveredTests
StEraseBusy->StEraseIdle 68 Covered T3,T15,T27
StEraseBusy->StEraseSuspend 65 Covered T15,T93,T71
StEraseIdle->StEraseBusy 57 Covered T3,T15,T27
StEraseSuspend->StEraseIdle 75 Covered T15,T93,T71



Branch Coverage for Module : flash_phy_erase
Line No.TotalCoveredPercent
Branches 10 10 100.00
IF 39 2 2 100.00
CASE 52 8 8 100.00


39 if (!rst_ni) begin -1- 40 state_q <= StEraseIdle; ==> 41 end else begin 42 state_q <= state_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


52 unique case (state_q) -1- 53 StEraseIdle: begin 54 req_valid = 1'b1; 55 56 if ((pg_erase_req_o || bk_erase_req_o) && ack_i) begin -2- 57 state_d = StEraseBusy; ==> 58 end MISSING_ELSE ==> 59 end 60 61 StEraseBusy: begin 62 suspend_valid = '1; 63 64 if (suspend_req_i && ack_i) begin -3- 65 state_d = StEraseSuspend; ==> 66 end else if (done_i) begin -4- 67 ack_o = 1'b1; ==> 68 state_d = StEraseIdle; 69 end MISSING_ELSE ==> 70 end 71 72 StEraseSuspend: begin 73 if (done_i) begin -5- 74 ack_o = 1'b1; ==> 75 state_d = StEraseIdle; 76 end MISSING_ELSE ==> 77 end 78 79 default:; ==>

Branches:
-1--2--3--4--5-StatusTests
StEraseIdle 1 - - - Covered T3,T15,T27
StEraseIdle 0 - - - Covered T1,T2,T3
StEraseBusy - 1 - - Covered T15,T93,T71
StEraseBusy - 0 1 - Covered T3,T15,T27
StEraseBusy - 0 0 - Covered T3,T15,T27
StEraseSuspend - - - 1 Covered T15,T11,T93
StEraseSuspend - - - 0 Covered T11,T12,T13
default - - - - Covered T11,T12,T13

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS3933100.00
ALWAYS471717100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00

38 always_ff @(posedge clk_i or negedge rst_ni) begin 39 1/1 if (!rst_ni) begin Tests: T1 T2 T3  40 1/1 state_q <= StEraseIdle; Tests: T1 T2 T3  41 end else begin 42 1/1 state_q <= state_d; Tests: T1 T2 T3  43 end 44 end 45 46 always_comb begin 47 1/1 req_valid = 1'b0; Tests: T1 T2 T3  48 1/1 suspend_valid = 1'b0; Tests: T1 T2 T3  49 1/1 ack_o = 1'b0; Tests: T1 T2 T3  50 1/1 state_d = state_q; Tests: T1 T2 T3  51 52 1/1 unique case (state_q) Tests: T1 T2 T3  53 StEraseIdle: begin 54 1/1 req_valid = 1'b1; Tests: T1 T2 T3  55 56 1/1 if ((pg_erase_req_o || bk_erase_req_o) && ack_i) begin Tests: T1 T2 T3  57 1/1 state_d = StEraseBusy; Tests: T3 T15 T27  58 end MISSING_ELSE 59 end 60 61 StEraseBusy: begin 62 1/1 suspend_valid = '1; Tests: T3 T15 T27  63 64 1/1 if (suspend_req_i && ack_i) begin Tests: T3 T15 T27  65 1/1 state_d = StEraseSuspend; Tests: T93 T71 T103  66 1/1 end else if (done_i) begin Tests: T3 T15 T27  67 1/1 ack_o = 1'b1; Tests: T3 T15 T27  68 1/1 state_d = StEraseIdle; Tests: T3 T15 T27  69 end MISSING_ELSE 70 end 71 72 StEraseSuspend: begin 73 1/1 if (done_i) begin Tests: T11 T93 T71  74 1/1 ack_o = 1'b1; Tests: T11 T93 T71  75 1/1 state_d = StEraseIdle; Tests: T11 T93 T71  76 end MISSING_ELSE 77 end 78 79 default:; 80 endcase // unique case (state_q) 81 end 82 83 1/1 assign pg_erase_req_o = pg_erase_req_i & req_valid; Tests: T1 T2 T3  84 1/1 assign bk_erase_req_o = bk_erase_req_i & req_valid; Tests: T1 T2 T3  85 1/1 assign suspend_req_o = suspend_req_i & suspend_valid; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase
TotalCoveredPercent
Conditions181688.89
Logical181688.89
Non-Logical00
Event00

 LINE       56
 EXPRESSION ((pg_erase_req_o || bk_erase_req_o) && ack_i)
             -----------------1----------------    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T15,T27

 LINE       56
 SUB-EXPRESSION (pg_erase_req_o || bk_erase_req_o)
                 -------1------    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT72,T73,T74
10CoveredT3,T15,T27

 LINE       64
 EXPRESSION (suspend_req_i && ack_i)
             ------1------    --2--
-1--2-StatusTests
01CoveredT3,T15,T27
10Not Covered
11CoveredT93,T71,T103

 LINE       83
 EXPRESSION (pg_erase_req_i & req_valid)
             -------1------   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T15,T27
11CoveredT3,T15,T27

 LINE       84
 EXPRESSION (bk_erase_req_i & req_valid)
             -------1------   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT72,T73,T74
11CoveredT72,T73,T74

 LINE       85
 EXPRESSION (suspend_req_i & suspend_valid)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT3,T15,T27
10CoveredT15,T93,T71
11CoveredT93,T71,T103

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase
Summary for FSM :: state_q
TotalCoveredPercent
States 3 3 100.00 (Not included in score)
Transitions 4 4 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StEraseBusy 57 Covered T3,T15,T27
StEraseIdle 68 Covered T1,T2,T3
StEraseSuspend 65 Covered T93,T71,T103


transitionsLine No.CoveredTests
StEraseBusy->StEraseIdle 68 Covered T3,T15,T27
StEraseBusy->StEraseSuspend 65 Covered T93,T71,T103
StEraseIdle->StEraseBusy 57 Covered T3,T15,T27
StEraseSuspend->StEraseIdle 75 Covered T93,T71,T103



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase
Line No.TotalCoveredPercent
Branches 10 10 100.00
IF 39 2 2 100.00
CASE 52 8 8 100.00


39 if (!rst_ni) begin -1- 40 state_q <= StEraseIdle; ==> 41 end else begin 42 state_q <= state_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


52 unique case (state_q) -1- 53 StEraseIdle: begin 54 req_valid = 1'b1; 55 56 if ((pg_erase_req_o || bk_erase_req_o) && ack_i) begin -2- 57 state_d = StEraseBusy; ==> 58 end MISSING_ELSE ==> 59 end 60 61 StEraseBusy: begin 62 suspend_valid = '1; 63 64 if (suspend_req_i && ack_i) begin -3- 65 state_d = StEraseSuspend; ==> 66 end else if (done_i) begin -4- 67 ack_o = 1'b1; ==> 68 state_d = StEraseIdle; 69 end MISSING_ELSE ==> 70 end 71 72 StEraseSuspend: begin 73 if (done_i) begin -5- 74 ack_o = 1'b1; ==> 75 state_d = StEraseIdle; 76 end MISSING_ELSE ==> 77 end 78 79 default:; ==>

Branches:
-1--2--3--4--5-StatusTests
StEraseIdle 1 - - - Covered T3,T15,T27
StEraseIdle 0 - - - Covered T1,T2,T3
StEraseBusy - 1 - - Covered T93,T71,T103
StEraseBusy - 0 1 - Covered T3,T15,T27
StEraseBusy - 0 0 - Covered T3,T15,T27
StEraseSuspend - - - 1 Covered T11,T93,T71
StEraseSuspend - - - 0 Covered T11,T12,T13
default - - - - Covered T11,T12,T13

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS3933100.00
ALWAYS471717100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00

38 always_ff @(posedge clk_i or negedge rst_ni) begin 39 1/1 if (!rst_ni) begin Tests: T1 T2 T3  40 1/1 state_q <= StEraseIdle; Tests: T1 T2 T3  41 end else begin 42 1/1 state_q <= state_d; Tests: T1 T2 T3  43 end 44 end 45 46 always_comb begin 47 1/1 req_valid = 1'b0; Tests: T1 T2 T3  48 1/1 suspend_valid = 1'b0; Tests: T1 T2 T3  49 1/1 ack_o = 1'b0; Tests: T1 T2 T3  50 1/1 state_d = state_q; Tests: T1 T2 T3  51 52 1/1 unique case (state_q) Tests: T1 T2 T3  53 StEraseIdle: begin 54 1/1 req_valid = 1'b1; Tests: T1 T2 T3  55 56 1/1 if ((pg_erase_req_o || bk_erase_req_o) && ack_i) begin Tests: T1 T2 T3  57 1/1 state_d = StEraseBusy; Tests: T15 T27 T22  58 end MISSING_ELSE 59 end 60 61 StEraseBusy: begin 62 1/1 suspend_valid = '1; Tests: T15 T27 T22  63 64 1/1 if (suspend_req_i && ack_i) begin Tests: T15 T27 T22  65 1/1 state_d = StEraseSuspend; Tests: T15 T71 T74  66 1/1 end else if (done_i) begin Tests: T15 T27 T22  67 1/1 ack_o = 1'b1; Tests: T15 T27 T22  68 1/1 state_d = StEraseIdle; Tests: T15 T27 T22  69 end MISSING_ELSE 70 end 71 72 StEraseSuspend: begin 73 1/1 if (done_i) begin Tests: T15 T11 T71  74 1/1 ack_o = 1'b1; Tests: T15 T11 T71  75 1/1 state_d = StEraseIdle; Tests: T15 T11 T71  76 end MISSING_ELSE 77 end 78 79 default:; 80 endcase // unique case (state_q) 81 end 82 83 1/1 assign pg_erase_req_o = pg_erase_req_i & req_valid; Tests: T1 T2 T3  84 1/1 assign bk_erase_req_o = bk_erase_req_i & req_valid; Tests: T1 T2 T3  85 1/1 assign suspend_req_o = suspend_req_i & suspend_valid; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase
TotalCoveredPercent
Conditions181688.89
Logical181688.89
Non-Logical00
Event00

 LINE       56
 EXPRESSION ((pg_erase_req_o || bk_erase_req_o) && ack_i)
             -----------------1----------------    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT15,T27,T22

 LINE       56
 SUB-EXPRESSION (pg_erase_req_o || bk_erase_req_o)
                 -------1------    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT70,T71,T36
10CoveredT15,T27,T22

 LINE       64
 EXPRESSION (suspend_req_i && ack_i)
             ------1------    --2--
-1--2-StatusTests
01CoveredT15,T27,T22
10Not Covered
11CoveredT15,T71,T74

 LINE       83
 EXPRESSION (pg_erase_req_i & req_valid)
             -------1------   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT15,T27,T22
11CoveredT15,T27,T22

 LINE       84
 EXPRESSION (bk_erase_req_i & req_valid)
             -------1------   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT70,T71,T36
11CoveredT70,T71,T36

 LINE       85
 EXPRESSION (suspend_req_i & suspend_valid)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT15,T27,T22
10CoveredT15,T93,T71
11CoveredT15,T71,T74

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase
Summary for FSM :: state_q
TotalCoveredPercent
States 3 3 100.00 (Not included in score)
Transitions 4 4 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StEraseBusy 57 Covered T15,T27,T22
StEraseIdle 68 Covered T1,T2,T3
StEraseSuspend 65 Covered T15,T71,T74


transitionsLine No.CoveredTests
StEraseBusy->StEraseIdle 68 Covered T15,T27,T22
StEraseBusy->StEraseSuspend 65 Covered T15,T71,T74
StEraseIdle->StEraseBusy 57 Covered T15,T27,T22
StEraseSuspend->StEraseIdle 75 Covered T15,T71,T74



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase
Line No.TotalCoveredPercent
Branches 10 10 100.00
IF 39 2 2 100.00
CASE 52 8 8 100.00


39 if (!rst_ni) begin -1- 40 state_q <= StEraseIdle; ==> 41 end else begin 42 state_q <= state_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


52 unique case (state_q) -1- 53 StEraseIdle: begin 54 req_valid = 1'b1; 55 56 if ((pg_erase_req_o || bk_erase_req_o) && ack_i) begin -2- 57 state_d = StEraseBusy; ==> 58 end MISSING_ELSE ==> 59 end 60 61 StEraseBusy: begin 62 suspend_valid = '1; 63 64 if (suspend_req_i && ack_i) begin -3- 65 state_d = StEraseSuspend; ==> 66 end else if (done_i) begin -4- 67 ack_o = 1'b1; ==> 68 state_d = StEraseIdle; 69 end MISSING_ELSE ==> 70 end 71 72 StEraseSuspend: begin 73 if (done_i) begin -5- 74 ack_o = 1'b1; ==> 75 state_d = StEraseIdle; 76 end MISSING_ELSE ==> 77 end 78 79 default:; ==>

Branches:
-1--2--3--4--5-StatusTests
StEraseIdle 1 - - - Covered T15,T27,T22
StEraseIdle 0 - - - Covered T1,T2,T3
StEraseBusy - 1 - - Covered T15,T71,T74
StEraseBusy - 0 1 - Covered T15,T27,T22
StEraseBusy - 0 0 - Covered T15,T27,T22
StEraseSuspend - - - 1 Covered T15,T11,T71
StEraseSuspend - - - 0 Covered T11,T12,T13
default - - - - Covered T11,T12,T13

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%