Module Definition
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Module : prim_subreg_arb
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg_core.u_phy_status_prog_normal_avail.wr_en_data_arb 0.00 0.00
tb.dut.u_reg_core.u_phy_status_prog_repair_avail.wr_en_data_arb 0.00 0.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field2.wr_en_data_arb 0.00 0.00
tb.dut.u_reg_core.u_intr_state_prog_empty.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_intr_state_prog_lvl.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_intr_state_rd_full.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_intr_state_rd_lvl.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_status_init_wip.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_status_initialized.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_std_fault_status_reg_intg_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_std_fault_status_prog_intg_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_std_fault_status_lcmgr_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_std_fault_status_lcmgr_intg_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_std_fault_status_arb_fsm_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_std_fault_status_storage_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_std_fault_status_phy_fsm_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_std_fault_status_ctrl_cnt_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_std_fault_status_fifo_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_fault_status_op_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_fault_status_mp_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_fault_status_rd_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_fault_status_prog_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_fault_status_prog_win_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_fault_status_prog_type_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_fault_status_seed_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_fault_status_spurious_ack.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_fault_status_arb_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_fault_status_host_gnt_err.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_phy_status_init_wip.wr_en_data_arb 50.00 50.00
tb.dut.u_reg_core.u_phy_alert_cfg_alert_ack.wr_en_data_arb 66.67 100.00 50.00 50.00
tb.dut.u_reg_core.u_phy_alert_cfg_alert_trig.wr_en_data_arb 66.67 100.00 50.00 50.00
tb.dut.u_reg_core.u_err_code_update_err.wr_en_data_arb 80.00 100.00 60.00
tb.dut.u_reg_core.u_err_code_macro_err.wr_en_data_arb 80.00 100.00 60.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field0.wr_en_data_arb 80.00 100.00 60.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field1.wr_en_data_arb 80.00 100.00 60.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field2.wr_en_data_arb 80.00 100.00 60.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field4.wr_en_data_arb 80.00 100.00 60.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field5.wr_en_data_arb 80.00 100.00 60.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field6.wr_en_data_arb 80.00 100.00 60.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field0.wr_en_data_arb 80.00 100.00 60.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field1.wr_en_data_arb 80.00 100.00 60.00
tb.dut.u_reg_core.u_fault_status_phy_relbl_err.wr_en_data_arb 95.00 100.00 90.00
tb.dut.u_reg_core.u_fault_status_phy_storage_err.wr_en_data_arb 95.00 100.00 90.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field3.wr_en_data_arb 95.24 100.00 85.71 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field7.wr_en_data_arb 95.24 100.00 85.71 100.00
tb.dut.u_reg_core.u_intr_state_op_done.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_state_corr_err.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_enable_prog_empty.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_enable_prog_lvl.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_enable_rd_full.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_enable_rd_lvl.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_enable_op_done.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_intr_enable_corr_err.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_dis.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_exec.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_init.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_control_start.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_control_op.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_control_prog_sel.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_control_erase_sel.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_control_partition_sel.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_control_info_sel.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_control_num.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_addr.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_prog_type_en_normal.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_prog_type_en_repair.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_erase_suspend.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_0.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_1.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_2.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_3.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_4.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_5.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_6.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_7.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_rd_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_prog_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_erase_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_scramble_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_ecc_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_he_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_rd_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_prog_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_erase_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_scramble_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_ecc_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_he_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_en_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_rd_en_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_prog_en_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_erase_en_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_scramble_en_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_ecc_en_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_he_en_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_en_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_rd_en_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_prog_en_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_erase_en_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_scramble_en_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_ecc_en_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_he_en_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_en_4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_rd_en_4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_prog_en_4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_erase_en_4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_scramble_en_4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_ecc_en_4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_he_en_4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_en_5.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_rd_en_5.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_prog_en_5.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_erase_en_5.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_scramble_en_5.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_ecc_en_5.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_he_en_5.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_en_6.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_rd_en_6.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_prog_en_6.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_erase_en_6.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_scramble_en_6.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_ecc_en_6.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_he_en_6.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_en_7.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_rd_en_7.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_prog_en_7.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_erase_en_7.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_scramble_en_7.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_ecc_en_7.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_he_en_7.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_0_base_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_0_size_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_1_base_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_1_size_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_2_base_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_2_size_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_3_base_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_3_size_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_4_base_4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_4_size_4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_5_base_5.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_5_size_5.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_6_base_6.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_6_size_6.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_7_base_7.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_region_7_size_7.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_default_region_rd_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_default_region_prog_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_default_region_erase_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_default_region_scramble_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_default_region_ecc_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_default_region_he_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_0.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_1.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_2.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_3.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_4.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_5.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_6.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_7.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_8.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_9.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_rd_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_prog_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_erase_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_scramble_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_ecc_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_he_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_rd_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_prog_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_erase_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_scramble_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_ecc_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_he_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_en_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_rd_en_2.wr_en_data_arb 100.00 100.00 100.00 100.00
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tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_scramble_en_9.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_ecc_en_9.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_he_en_9.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_regwen.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_rd_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_prog_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_erase_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_scramble_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_ecc_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_he_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_regwen_0.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_regwen_1.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_rd_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_prog_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_erase_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_scramble_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_ecc_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_he_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_rd_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_prog_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_erase_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_scramble_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_ecc_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_he_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_hw_info_cfg_override_scramble_dis.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_hw_info_cfg_override_ecc_dis.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_bank_cfg_regwen.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_op_status_done.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_op_status_err.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_status_rd_full.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_status_rd_empty.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_status_prog_full.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_status_prog_empty.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_err_code_op_err.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_err_code_mp_err.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_err_code_rd_err.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_err_code_prog_err.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_err_code_prog_win_err.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_err_code_prog_type_err.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg_core.u_err_addr.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_ecc_single_err_addr_0.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_ecc_single_err_addr_1.wr_en_data_arb 100.00 100.00
tb.dut.u_reg_core.u_scratch.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_fifo_lvl_prog.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_fifo_lvl_rd.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg_core.u_fifo_rst.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr0_regwen.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr1_field0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr1_field1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field9.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field5.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field6.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field7.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field8.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr8.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr9.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr10.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr11.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr12.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr13_field0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr13_field1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr14_field0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr14_field1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr15_field0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr15_field1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr16_field0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr16_field1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr17_field0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr17_field1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr18.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr19.wr_en_data_arb 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 + DW=20,SwAccess=1,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_intr_state_prog_empty.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_intr_state_prog_lvl.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_intr_state_rd_full.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_intr_state_rd_lvl.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_status_rd_full.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_status_rd_empty.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_status_prog_full.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_status_prog_empty.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_status_init_wip.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_status_initialized.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_std_fault_status_reg_intg_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_std_fault_status_prog_intg_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_std_fault_status_lcmgr_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_std_fault_status_lcmgr_intg_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_std_fault_status_arb_fsm_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_std_fault_status_storage_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_std_fault_status_phy_fsm_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_std_fault_status_ctrl_cnt_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_std_fault_status_fifo_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_fault_status_op_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_fault_status_mp_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_fault_status_rd_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_fault_status_prog_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_fault_status_prog_win_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_fault_status_prog_type_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_fault_status_seed_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_fault_status_spurious_ack.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_fault_status_arb_err.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_fault_status_host_gnt_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_err_addr.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_ecc_single_err_addr_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_ecc_single_err_addr_1.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg_core.u_phy_status_init_wip.wr_en_data_arb

SCORELINE
0.00 0.00
tb.dut.u_reg_core.u_phy_status_prog_normal_avail.wr_en_data_arb

SCORELINE
0.00 0.00
tb.dut.u_reg_core.u_phy_status_prog_repair_avail.wr_en_data_arb

SCORELINE
0.00 0.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field2.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300

42 end else if (SwAccess == SwAccessRO) begin : gen_ro 43 1/1 assign wr_en = de; Tests: T1 T2 T3  44 1/1 assign wr_data = d; Tests: T1 T2 T3  45 // Unused we, wd, q - Prevent lint errors. 46 logic unused_we; 47 logic [DW-1:0] unused_wd; 48 logic [DW-1:0] unused_q; 49 //VCS coverage off 50 // pragma coverage off 51 unreachable assign unused_we = we; 52 unreachable assign unused_wd = wd; 53 unreachable assign unused_q = q;

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_intr_state_op_done.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_intr_state_corr_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_err_code_op_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_err_code_mp_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_err_code_rd_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_err_code_prog_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_err_code_prog_win_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_err_code_prog_type_err.wr_en_data_arb

SCORELINE
80.00 100.00
tb.dut.u_reg_core.u_err_code_update_err.wr_en_data_arb

SCORELINE
80.00 100.00
tb.dut.u_reg_core.u_err_code_macro_err.wr_en_data_arb

SCORELINE
80.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field0.wr_en_data_arb

SCORELINE
80.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field1.wr_en_data_arb

SCORELINE
80.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field2.wr_en_data_arb

SCORELINE
80.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field4.wr_en_data_arb

SCORELINE
80.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field5.wr_en_data_arb

SCORELINE
80.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field6.wr_en_data_arb

SCORELINE
80.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field0.wr_en_data_arb

SCORELINE
80.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field1.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00

87 // If both try to set/clr at the same bit pos, SW wins. 88 1/1 assign wr_en = we | de; Tests: T1 T2 T3  89 if (Mubi) begin : gen_mubi 90 if (DW == 4) begin : gen_mubi4 91 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 92 (we ? prim_mubi_pkg::mubi4_t'(~wd) : 93 prim_mubi_pkg::MuBi4True)); 94 end else if (DW == 8) begin : gen_mubi8 95 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 96 (we ? prim_mubi_pkg::mubi8_t'(~wd) : 97 prim_mubi_pkg::MuBi8True)); 98 end else if (DW == 12) begin : gen_mubi12 99 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 100 (we ? prim_mubi_pkg::mubi12_t'(~wd) : 101 prim_mubi_pkg::MuBi12True)); 102 end else if (DW == 16) begin : gen_mubi16 103 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 104 (we ? prim_mubi_pkg::mubi16_t'(~wd) : 105 prim_mubi_pkg::MuBi16True)); 106 end else begin : gen_invalid_mubi 107 $error("%m: Invalid width for MuBi"); 108 end 109 end else begin : gen_non_mubi 110 1/1 assign wr_data = (de ? d : q) & (we ? ~wd : '1); Tests: T1 T2 T3 

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=32,SwAccess=0,Mubi=0 + DW=2,SwAccess=0,Mubi=0 + DW=12,SwAccess=0,Mubi=0 + DW=20,SwAccess=0,Mubi=0 + DW=4,SwAccess=0,Mubi=1 + DW=9,SwAccess=0,Mubi=0 + DW=10,SwAccess=0,Mubi=0 + DW=8,SwAccess=0,Mubi=0 + DW=5,SwAccess=0,Mubi=0 + DW=3,SwAccess=0,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_prog_empty.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_prog_lvl.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_rd_full.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_rd_lvl.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_op_done.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_corr_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_exec.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_control_start.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_control_op.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_control_prog_sel.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_control_erase_sel.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_control_partition_sel.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_control_info_sel.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_control_num.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_addr.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_erase_suspend.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_en_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_rd_en_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_prog_en_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_erase_en_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_scramble_en_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_ecc_en_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_he_en_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_en_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_rd_en_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_prog_en_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_erase_en_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_scramble_en_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_ecc_en_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_he_en_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_en_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_rd_en_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_prog_en_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_erase_en_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_scramble_en_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_ecc_en_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_he_en_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_en_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_rd_en_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_prog_en_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_erase_en_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_scramble_en_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_ecc_en_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_he_en_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_en_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_rd_en_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_prog_en_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_erase_en_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_scramble_en_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_ecc_en_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_he_en_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_en_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_rd_en_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_prog_en_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_erase_en_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_scramble_en_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_ecc_en_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_he_en_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_en_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_rd_en_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_prog_en_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_erase_en_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_scramble_en_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_ecc_en_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_he_en_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_en_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_rd_en_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_prog_en_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_erase_en_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_scramble_en_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_ecc_en_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_he_en_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_0_base_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_0_size_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_1_base_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_1_size_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_2_base_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_2_size_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_3_base_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_3_size_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_4_base_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_4_size_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_5_base_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_5_size_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_6_base_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_6_size_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_7_base_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_mp_region_7_size_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_default_region_rd_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_default_region_prog_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_default_region_erase_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_default_region_scramble_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_default_region_ecc_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_default_region_he_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_en_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_rd_en_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_prog_en_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_erase_en_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_scramble_en_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_ecc_en_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_he_en_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_en_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_rd_en_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_prog_en_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_erase_en_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_scramble_en_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_ecc_en_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_he_en_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_en_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_rd_en_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_prog_en_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_erase_en_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_scramble_en_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_ecc_en_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_he_en_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_en_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_rd_en_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_prog_en_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_erase_en_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_scramble_en_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_ecc_en_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_he_en_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_en_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_rd_en_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_prog_en_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_erase_en_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_scramble_en_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_ecc_en_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_he_en_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_en_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_rd_en_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_prog_en_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_erase_en_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_scramble_en_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_ecc_en_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_he_en_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_en_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_rd_en_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_prog_en_6.wr_en_data_arb

SCORELINE
100.00 100.00
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SCORELINE
66.67 100.00
tb.dut.u_reg_core.u_phy_alert_cfg_alert_trig.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_scratch.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_fifo_lvl_prog.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_fifo_lvl_rd.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_fifo_rst.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr1_field0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr1_field1.wr_en_data_arb

SCORELINE
95.24 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field3.wr_en_data_arb

SCORELINE
95.24 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field9.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field8.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr8.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr9.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr10.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr11.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr12.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr13_field0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr13_field1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr14_field0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr14_field1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr15_field0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr15_field1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr16_field0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr16_field1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr17_field0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr17_field1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr18.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr19.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T1 T14 T26  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Line Coverage for Module : prim_subreg_arb ( parameter DW=4,SwAccess=4,Mubi=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_dis.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6311100.00

59 // If both try to set/clr at the same bit pos, SW wins. 60 1/1 assign wr_en = we | de; Tests: T75 T76 T84  61 if (Mubi) begin : gen_mubi 62 if (DW == 4) begin : gen_mubi4 63 1/1 assign wr_data = prim_mubi_pkg::mubi4_or_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), Tests: T1 T2 T3 

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=4,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_init.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN8211100.00

59 // If both try to set/clr at the same bit pos, SW wins. 60 1/1 assign wr_en = we | de; Tests: T1 T2 T3  61 if (Mubi) begin : gen_mubi 62 if (DW == 4) begin : gen_mubi4 63 assign wr_data = prim_mubi_pkg::mubi4_or_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 64 (we ? prim_mubi_pkg::mubi4_t'(wd) : 65 prim_mubi_pkg::MuBi4False)); 66 end else if (DW == 8) begin : gen_mubi8 67 assign wr_data = prim_mubi_pkg::mubi8_or_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 68 (we ? prim_mubi_pkg::mubi8_t'(wd) : 69 prim_mubi_pkg::MuBi8False)); 70 end else if (DW == 12) begin : gen_mubi12 71 assign wr_data = prim_mubi_pkg::mubi12_or_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 72 (we ? prim_mubi_pkg::mubi12_t'(wd) : 73 prim_mubi_pkg::MuBi12False)); 74 end else if (DW == 16) begin : gen_mubi16 75 assign wr_data = prim_mubi_pkg::mubi16_or_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 76 (we ? prim_mubi_pkg::mubi16_t'(wd) : 77 prim_mubi_pkg::MuBi16False)); 78 end else begin : gen_invalid_mubi 79 $error("%m: Invalid width for MuBi"); 80 end 81 end else begin : gen_non_mubi 82 1/1 assign wr_data = (de ? d : q) | (we ? wd : '0); Tests: T1 T2 T3 

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_prog_type_en_normal.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_prog_type_en_repair.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_8.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_9.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_regwen.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_regwen_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_regwen_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_8.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_9.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_regwen.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_regwen_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_regwen_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_bank_cfg_regwen.wr_en_data_arb

SCORELINE
95.00 100.00
tb.dut.u_reg_core.u_fault_status_phy_relbl_err.wr_en_data_arb

SCORELINE
95.00 100.00
tb.dut.u_reg_core.u_fault_status_phy_storage_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr0_regwen.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T94 T95 T96  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Module : prim_subreg_arb ( parameter DW=4,SwAccess=4,Mubi=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_dis.wr_en_data_arb

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       60
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT75,T76,T84

Cond Coverage for Module : prim_subreg_arb ( parameter DW=9,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_0_base_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_1_base_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_2_base_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_3_base_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_4_base_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_5_base_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_6_base_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_7_base_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr7_field1.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg_arb ( parameter DW=3,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field3.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT66,T68,T118

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT66,T68,T118

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT66,T68,T118

Cond Coverage for Module : prim_subreg_arb ( parameter DW=4,SwAccess=0,Mubi=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_rd_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_prog_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_erase_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_scramble_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_ecc_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_0_he_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_rd_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_prog_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_erase_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_scramble_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_ecc_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_1_he_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_en_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_rd_en_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_prog_en_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_erase_en_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_scramble_en_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_ecc_en_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_2_he_en_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_en_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_rd_en_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_prog_en_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_erase_en_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_scramble_en_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_ecc_en_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_3_he_en_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_en_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_rd_en_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_prog_en_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_erase_en_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_scramble_en_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_ecc_en_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_4_he_en_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_en_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_rd_en_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_prog_en_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_erase_en_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_scramble_en_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_ecc_en_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_5_he_en_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_en_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_rd_en_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_prog_en_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_erase_en_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_scramble_en_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_ecc_en_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_6_he_en_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_en_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_rd_en_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_prog_en_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_erase_en_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_scramble_en_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_ecc_en_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_cfg_7_he_en_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_default_region_rd_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_default_region_prog_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_default_region_erase_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_default_region_scramble_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_default_region_ecc_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_default_region_he_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_rd_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_prog_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_erase_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_scramble_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_ecc_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_0_he_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_rd_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_prog_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_erase_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_scramble_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_ecc_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_1_he_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_en_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_rd_en_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_prog_en_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_erase_en_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_scramble_en_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_ecc_en_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_2_he_en_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_en_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_rd_en_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_prog_en_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_erase_en_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_scramble_en_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_ecc_en_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_3_he_en_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_en_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_rd_en_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_prog_en_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_erase_en_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_scramble_en_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_ecc_en_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_4_he_en_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_en_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_rd_en_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_prog_en_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_erase_en_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_scramble_en_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_ecc_en_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_5_he_en_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_en_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_rd_en_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_prog_en_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_erase_en_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_scramble_en_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_ecc_en_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_6_he_en_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_en_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_rd_en_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_prog_en_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_erase_en_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_scramble_en_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_ecc_en_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_7_he_en_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_en_8.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_rd_en_8.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_prog_en_8.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_erase_en_8.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_scramble_en_8.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_ecc_en_8.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_8_he_en_8.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_en_9.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_rd_en_9.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_prog_en_9.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_erase_en_9.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_scramble_en_9.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_ecc_en_9.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_page_cfg_9_he_en_9.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_rd_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_prog_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_erase_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_scramble_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_ecc_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_page_cfg_he_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_rd_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_prog_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_erase_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_scramble_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_ecc_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_0_he_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_rd_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_prog_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_erase_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_scramble_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_ecc_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_page_cfg_1_he_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_rd_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_prog_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_erase_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_scramble_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_ecc_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_0_he_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_rd_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_prog_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_erase_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_scramble_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_ecc_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_1_he_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_en_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_rd_en_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_prog_en_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_erase_en_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_scramble_en_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_ecc_en_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_2_he_en_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_en_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_rd_en_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_prog_en_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_erase_en_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_scramble_en_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_ecc_en_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_3_he_en_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_en_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_rd_en_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_prog_en_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_erase_en_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_scramble_en_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_ecc_en_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_4_he_en_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_en_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_rd_en_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_prog_en_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_erase_en_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_scramble_en_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_ecc_en_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_5_he_en_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_en_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_rd_en_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_prog_en_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_erase_en_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_scramble_en_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_ecc_en_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_6_he_en_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_en_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_rd_en_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_prog_en_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_erase_en_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_scramble_en_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_ecc_en_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_7_he_en_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_en_8.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_rd_en_8.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_prog_en_8.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_erase_en_8.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_scramble_en_8.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_ecc_en_8.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_8_he_en_8.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_en_9.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_rd_en_9.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_prog_en_9.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_erase_en_9.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_scramble_en_9.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_ecc_en_9.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_page_cfg_9_he_en_9.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_rd_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_prog_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_erase_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_scramble_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_ecc_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_page_cfg_he_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_rd_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_prog_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_erase_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_scramble_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_ecc_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_0_he_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_rd_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_prog_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_erase_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_scramble_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_ecc_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_page_cfg_1_he_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_hw_info_cfg_override_scramble_dis.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_hw_info_cfg_override_ecc_dis.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg_arb ( parameter DW=12,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_control_num.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T3,T7

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T7

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T7

Cond Coverage for Module : prim_subreg_arb ( parameter DW=10,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_0_size_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_1_size_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_2_size_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_3_size_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_4_size_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_5_size_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_6_size_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_region_7_size_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr12.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_intr_state_op_done.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_intr_state_corr_err.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_err_code_op_err.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_err_code_mp_err.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_err_code_rd_err.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_err_code_prog_err.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_err_code_prog_win_err.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_err_code_prog_type_err.wr_en_data_arb

SCORECOND
80.00 60.00
tb.dut.u_reg_core.u_err_code_update_err.wr_en_data_arb

SCORECOND
80.00 60.00
tb.dut.u_reg_core.u_err_code_macro_err.wr_en_data_arb

SCORECOND
80.00 60.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field0.wr_en_data_arb

SCORECOND
80.00 60.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field1.wr_en_data_arb

SCORECOND
80.00 60.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field2.wr_en_data_arb

SCORECOND
80.00 60.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field4.wr_en_data_arb

SCORECOND
80.00 60.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field5.wr_en_data_arb

SCORECOND
80.00 60.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field6.wr_en_data_arb

SCORECOND
80.00 60.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field0.wr_en_data_arb

SCORECOND
80.00 60.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr20_field1.wr_en_data_arb

TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T7
10CoveredT1,T3,T7

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T7
11CoveredT1,T3,T7

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T7

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T7

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=4,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_init.wr_en_data_arb

TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       60
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       82
 EXPRESSION ((de ? d : q) | (we ? wd : '0))
             ------1-----   -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       82
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1Unreachable

 LINE       82
 SUB-EXPRESSION (we ? wd : '0)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_prog_type_en_normal.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_prog_type_en_repair.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_region_cfg_regwen_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_8.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info0_regwen_9.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info1_regwen.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_regwen_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank0_info2_regwen_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_8.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info0_regwen_9.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info1_regwen.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_regwen_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank1_info2_regwen_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_bank_cfg_regwen.wr_en_data_arb

SCORECOND
95.00 90.00
tb.dut.u_reg_core.u_fault_status_phy_relbl_err.wr_en_data_arb

SCORECOND
95.00 90.00
tb.dut.u_reg_core.u_fault_status_phy_storage_err.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr0_regwen.wr_en_data_arb

TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT26,T28,T24
10CoveredT94,T95,T96

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT94,T95,T96
10CoveredT94,T95,T96
11CoveredT1,T2,T3

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT26,T28,T24

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT94,T95,T96

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_prog_empty.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_prog_lvl.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_rd_full.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_rd_lvl.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_op_done.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_intr_enable_corr_err.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_control_start.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_control_prog_sel.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_control_erase_sel.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_control_partition_sel.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_erase_suspend.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.committed_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.committed_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_op_status_done.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_op_status_err.wr_en_data_arb

SCORECOND
66.67 50.00
tb.dut.u_reg_core.u_phy_alert_cfg_alert_ack.wr_en_data_arb

SCORECOND
66.67 50.00
tb.dut.u_reg_core.u_phy_alert_cfg_alert_trig.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_fifo_rst.wr_en_data_arb

SCORECOND
95.24 85.71
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field3.wr_en_data_arb

SCORECOND
95.24 85.71
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr2_field7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field8.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr13_field1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr14_field1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr15_field1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr16_field1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr17_field1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr18.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr19.wr_en_data_arb

TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T7
10CoveredT1,T3,T7

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T7

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T7

Cond Coverage for Module : prim_subreg_arb ( parameter DW=5,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_fifo_lvl_prog.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_fifo_lvl_rd.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr1_field1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT30,T181,T39

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T181,T39

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T181,T39

Cond Coverage for Module : prim_subreg_arb ( parameter DW=20,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_addr.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr13_field0.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T3,T7

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T7

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T7

Cond Coverage for Module : prim_subreg_arb ( parameter DW=2,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_control_op.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_control_info_sel.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr3_field9.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field6.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T3,T7

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T7

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T7

Cond Coverage for Module : prim_subreg_arb ( parameter DW=8,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_ecc_single_err_cnt_ecc_single_err_cnt_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr1_field0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr6_field2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr7_field0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr14_field0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr15_field0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr16_field0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr17_field0.wr_en_data_arb

TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT26,T17,T25
10CoveredT66,T68,T69

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT66,T68,T69

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT66,T68,T69

Cond Coverage for Module : prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_exec.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg_core.u_scratch.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr8.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr9.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr10.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_csr11.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT14,T53,T54

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T53,T54

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T53,T54

Branch Coverage for Module : prim_subreg_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T3,T7
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%