FLASH_CTRL Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: `ed1c41cd0f`

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	5.710m	168.373us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	54.890s	17.456us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	1.146m	84.963us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	28.320s	67.478us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.338m	6.197ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.300m	3.077ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	34.310s	754.040us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	28.320s	67.478us	20	20	100.00
		flash_ctrl_csr_aliasing	1.300m	3.077ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	27.390s	14.799us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	23.520s	44.675us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	53.350s	46.007us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	3.005m	242.202us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	38.636m	167.369ms	3	3	100.00
		flash_ctrl_hw_rma_reset	19.184m	80.134ms	20	20	100.00
		flash_ctrl_lcmgr_intg	28.580s	59.254us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	57.916m	369.762ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	12.538m	6.423ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	4.200m	2.640ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.136h	232.816ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	4.404m	2.075ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	1.067m	59.939us	40	40	100.00
		flash_ctrl_rw_evict_all_en	1.064m	33.037us	38	40	95.00
		flash_ctrl_re_evict	1.094m	238.320us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	14.100m	131.441us	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	14.100m	131.441us	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	11.335m	30.304ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	48.000s	2.299ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	31.352m	557.707us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	56.513m	14.534ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	29.830m	6.293ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	57.762m	1.107ms	4	5	80.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	28.980s	25.479us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.178m	1.320ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	45.370s	10.547us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	33.660s	87.980us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	24.493m	1.590ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.315m	2.655ms	50	50	100.00
		flash_ctrl_otp_reset	4.456m	714.939us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	38.636m	167.369ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	5.272m	2.286ms	38	40	95.00
		flash_ctrl_intr_wr	2.156m	21.412ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	9.123m	51.912ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	6.617m	155.534ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	2.211m	5.376ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	2.299m	827.299us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	45.940s	31.427us	5	5	100.00
		flash_ctrl_ro_derr	3.213m	4.895ms	10	10	100.00
		flash_ctrl_rw_derr	5.263m	2.001ms	10	10	100.00
		flash_ctrl_derr_detect	5.094m	772.652us	5	5	100.00
		flash_ctrl_integrity	9.187m	18.171ms	4	5	80.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	44.320s	76.286us	5	5	100.00
		flash_ctrl_ro_serr	3.057m	629.740us	10	10	100.00
		flash_ctrl_rw_serr	4.406m	7.328ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.716m	1.421ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	2.295m	2.990ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.801m	2.781ms	19	20	95.00
		flash_ctrl_write_word_sweep	26.570s	278.789us	1	1	100.00
		flash_ctrl_read_word_sweep	17.470s	24.844us	1	1	100.00
		flash_ctrl_ro	3.073m	12.172ms	20	20	100.00
		flash_ctrl_rw	11.396m	19.106ms	17	20	85.00
V2	filesystem_support	flash_ctrl_fs_sup	1.033m	507.335us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	18.791m	82.226ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.001m	10.015ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	31.530s	63.686us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	26.800s	58.465us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	34.150s	97.368us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	34.150s	97.368us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	1.146m	84.963us	5	5	100.00
		flash_ctrl_csr_rw	28.320s	67.478us	20	20	100.00
		flash_ctrl_csr_aliasing	1.300m	3.077ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	48.320s	125.160us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	1.146m	84.963us	5	5	100.00
		flash_ctrl_csr_rw	28.320s	67.478us	20	20	100.00
		flash_ctrl_csr_aliasing	1.300m	3.077ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	48.320s	125.160us	20	20	100.00
V2		TOTAL			1003	1013	99.01
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	30.120s	12.297us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	30.120s	12.297us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	30.120s	12.297us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	30.120s	12.297us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	27.500s	97.527us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	2.075h	2.181ms	5	5	100.00
		flash_ctrl_tl_intg_err	25.518m	1.746ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	25.518m	1.746ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	25.518m	1.746ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	1.025m	63.789us	3	3	100.00
		flash_ctrl_wr_intg	30.760s	46.517us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	5.710m	168.373us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	4.456m	714.939us	80	80	100.00
		flash_ctrl_disable	45.370s	10.547us	50	50	100.00
		flash_ctrl_sec_info_access	2.005m	7.541ms	50	50	100.00
		flash_ctrl_connect	33.660s	87.980us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	29.000s	40.752us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	28.320s	67.478us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	30.120s	12.297us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	28.320s	67.478us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	30.120s	12.297us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	28.320s	67.478us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	30.120s	12.297us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	45.370s	10.547us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	1.025m	63.789us	3	3	100.00
		flash_ctrl_access_after_disable	28.640s	23.437us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	56.070s	39.990us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	45.370s	10.547us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	48.000s	2.299ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.396m	19.106ms	17	20	85.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	4.406m	7.328ms	10	10	100.00
		flash_ctrl_rw_derr	5.263m	2.001ms	10	10	100.00
		flash_ctrl_integrity	9.187m	18.171ms	4	5	80.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	38.636m	167.369ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	2.075h	2.181ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	2.075h	2.181ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	2.075h	2.181ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	2.075h	2.181ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	41.520s	885.176us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	28.430s	45.126us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	29.870s	15.779us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	2.075h	2.181ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	2.075h	2.181ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	2.075h	2.181ms	5	5	100.00
V2S		TOTAL			147	147	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	1.137m	156.643us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1271	1281	99.22

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	49	89.09
V2S	13	13	13	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.18	95.73	93.97	98.31	91.84	98.25	96.89	98.24

Failure Buckets

Job timed out after * minutes has 6 failures:
- Test flash_ctrl_rw has 3 failures.
  - 0.flash_ctrl_rw.7634446539839203823918329236721918130829605978308522290817249951260713979792
    Log /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/0.flash_ctrl_rw/latest/run.log
```
  Job timed out after 60 minutes
```
  - 1.flash_ctrl_rw.69556156721528105584103936781028583770244772062997191073763926338759359237455
    Log /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_rw/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 1 more failures.
- Test flash_ctrl_integrity has 1 failures.
  - 1.flash_ctrl_integrity.24505801554947494071037324087708735987575298981867782871504993693648327794007
    Log /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest/run.log
```
  Job timed out after 60 minutes
```
- Test flash_ctrl_error_prog_type has 1 failures.
  - 4.flash_ctrl_error_prog_type.4282037044004486528836889889517377978792349733685078843253289162135778533078
    Log /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/4.flash_ctrl_error_prog_type/latest/run.log
```
  Job timed out after 60 minutes
```
- Test flash_ctrl_wo has 1 failures.
  - 13.flash_ctrl_wo.24539466580082924388081135388296855184248408426153730972154776156814010079496
    Log /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/13.flash_ctrl_wo/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:
- Test flash_ctrl_rw_evict_all_en has 2 failures.
  - 22.flash_ctrl_rw_evict_all_en.69770733718650395008072377808673065580094896060418082407347351617254773442432
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 30122.2 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 30122.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.flash_ctrl_rw_evict_all_en.102774101081440809167883423207398864746185592528350469571007188502265108088951
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 42853.3 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 42853.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp ff6494ee_f6f63401:ffffffff_f6f* mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 2.flash_ctrl_intr_rd.9464503300556285459730863265545061277068480274821050942110438994150902286475
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 860914.0 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    6: obs:exp    ff6494ee_f6f63401:ffffffff_f6f63401  mismatch!!
  UVM_INFO @ 860914.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp d9459cc6_eb86623b:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 5.flash_ctrl_intr_rd.107971776488916147912573858140424525966978619021183962004820828622396691916321
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 4152563.6 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    7: obs:exp    d9459cc6_eb86623b:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 4152563.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

FLASH_CTRL Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: ed1c41cd0f

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `ed1c41cd0f`