Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	25531029	1		T1	281		T2	58		T3	1137
full_word	7678392	1		T1	247		T2	3		T3	161

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33209111	1		T1	528		T2	61		T3	1298
auto[TlIntgErrCmd]	116	1		T248	4		T249	5		T250	1
auto[TlIntgErrData]	87	1		T248	5		T249	4		T250	3
auto[TlIntgErrBoth]	107	1		T248	1		T249	1		T250	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28871298	1		T1	422		T2	57		T3	1132
auto[1]	4338123	1		T1	106		T2	4		T3	166

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	24822493	1		T1	261		T2	57		T3	1126
auto[TlIntgErrNone]	partial	auto[1]	708251	1		T1	20		T2	1		T3	11
auto[TlIntgErrNone]	full_word	auto[0]	4048662	1		T1	161		T3	6		T7	23
auto[TlIntgErrNone]	full_word	auto[1]	3629705	1		T1	86		T2	3		T3	155
auto[TlIntgErrCmd]	partial	auto[0]	44	1		T248	2		T249	2		T250	1
auto[TlIntgErrCmd]	partial	auto[1]	65	1		T248	2		T249	3		T354	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T355	1		T358	1		T360	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T268	1		T359	1		T356	1
auto[TlIntgErrData]	partial	auto[0]	40	1		T248	1		T249	1		T250	3
auto[TlIntgErrData]	partial	auto[1]	40	1		T248	4		T249	2		T357	1
auto[TlIntgErrData]	full_word	auto[0]	3	1		T350	1		T267	2		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1		T249	1		T352	1		T359	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1		T250	4		T354	1		T357	1
auto[TlIntgErrBoth]	partial	auto[1]	49	1		T248	1		T249	1		T250	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1		T353	1		T358	2		T268	2
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T353	1		T359	2		T356	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	19164	1		T114	417		T115	441		T68	159
full_word	3761360	1		T2	10		T14	394		T15	108

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3780231	1		T2	10		T14	394		T15	108
auto[TlIntgErrCmd]	107	1		T248	3		T249	3		T250	3
auto[TlIntgErrData]	91	1		T248	2		T249	2		T250	4
auto[TlIntgErrBoth]	95	1		T248	5		T249	5		T250	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3756150	1		T2	10		T14	394		T15	108
auto[1]	24374	1		T114	599		T115	463		T68	200

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1048	1		T114	13		T115	54		T68	16
auto[TlIntgErrNone]	partial	auto[1]	17846	1		T114	404		T115	387		T68	143
auto[TlIntgErrNone]	full_word	auto[0]	3754970	1		T2	10		T14	394		T15	108
auto[TlIntgErrNone]	full_word	auto[1]	6367	1		T114	195		T115	76		T68	57
auto[TlIntgErrCmd]	partial	auto[0]	45	1		T248	2		T249	2		T354	2
auto[TlIntgErrCmd]	partial	auto[1]	53	1		T248	1		T249	1		T250	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T351	1		T361	1		T360	2
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T266	1		T358	2		T267	1
auto[TlIntgErrData]	partial	auto[0]	45	1		T249	2		T250	3		T354	3
auto[TlIntgErrData]	partial	auto[1]	38	1		T248	2		T250	1		T354	1
auto[TlIntgErrData]	full_word	auto[0]	5	1		T266	1		T353	2		T358	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T358	1		T356	1		T267	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1		T248	1		T249	2		T250	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1		T248	4		T249	3		T354	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T354	1		T357	1		T350	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T266	1		T267	1		T360	1