Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T3 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T15

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T14,T15
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T14,T15
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T25,T26
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T14,T15

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T15
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T25,T26
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T14,T15

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T14,T15

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1593547908	1590102064	0	0
CheckNGreaterZero_A	4224	4224	0	0
GntImpliesReady_A	1593547908	401911702	0	0
GntImpliesValid_A	1593547908	401911702	0	0
GrantKnown_A	1593547908	1590102064	0	0
IdxKnown_A	1593547908	1590102064	0	0
IndexIsCorrect_A	1593547908	401911702	0	0
NoReadyValidNoGrant_A	1593547908	174870891	0	0
Priority_A	1593547908	425464655	0	0
ReadyAndValidImplyGrant_A	1593547908	401911702	0	0
ReqAndReadyImplyGrant_A	1593547908	401911702	0	0
ReqImpliesValid_A	1593547908	425464655	0	0
ValidKnown_A	1593547908	1590102064	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593547908	1590102064	0	0
T1	8152	7828	0	0
T2	3476	3160	0	0
T3	16480	16208	0	0
T7	10496	10236	0	0
T14	49592	49388	0	0
T15	15520	15220	0	0
T18	7316	6944	0	0
T19	8296	7992	0	0
T20	7296	7064	0	0
T21	5936	5312	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4224	4224	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T7	4	4	0	0
T14	4	4	0	0
T15	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593547908	401911702	0	0
T1	8152	356	0	0
T2	3476	84	0	0
T3	16480	4442	0	0
T7	10496	1160	0	0
T14	49592	2000	0	0
T15	15520	3572	0	0
T16	0	128950	0	0
T18	7316	356	0	0
T19	8296	356	0	0
T20	7296	78	0	0
T21	5936	132	0	0
T25	0	26	0	0
T26	0	1102	0	0
T27	0	8	0	0
T49	0	21276	0	0
T58	0	19478	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593547908	401911702	0	0
T1	8152	356	0	0
T2	3476	84	0	0
T3	16480	4442	0	0
T7	10496	1160	0	0
T14	49592	2000	0	0
T15	15520	3572	0	0
T16	0	128950	0	0
T18	7316	356	0	0
T19	8296	356	0	0
T20	7296	78	0	0
T21	5936	132	0	0
T25	0	26	0	0
T26	0	1102	0	0
T27	0	8	0	0
T49	0	21276	0	0
T58	0	19478	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593547908	1590102064	0	0
T1	8152	7828	0	0
T2	3476	3160	0	0
T3	16480	16208	0	0
T7	10496	10236	0	0
T14	49592	49388	0	0
T15	15520	15220	0	0
T18	7316	6944	0	0
T19	8296	7992	0	0
T20	7296	7064	0	0
T21	5936	5312	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593547908	1590102064	0	0
T1	8152	7828	0	0
T2	3476	3160	0	0
T3	16480	16208	0	0
T7	10496	10236	0	0
T14	49592	49388	0	0
T15	15520	15220	0	0
T18	7316	6944	0	0
T19	8296	7992	0	0
T20	7296	7064	0	0
T21	5936	5312	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593547908	401911702	0	0
T1	8152	356	0	0
T2	3476	84	0	0
T3	16480	4442	0	0
T7	10496	1160	0	0
T14	49592	2000	0	0
T15	15520	3572	0	0
T16	0	128950	0	0
T18	7316	356	0	0
T19	8296	356	0	0
T20	7296	78	0	0
T21	5936	132	0	0
T25	0	26	0	0
T26	0	1102	0	0
T27	0	8	0	0
T49	0	21276	0	0
T58	0	19478	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593547908	174870891	0	0
T1	8152	696	0	0
T2	3476	286	0	0
T3	16480	256	0	0
T7	10496	316	0	0
T14	49592	3152	0	0
T15	15520	548	0	0
T16	0	4838	0	0
T18	7316	986	0	0
T19	8296	992	0	0
T20	7296	278	0	0
T21	5936	512	0	0
T25	0	74	0	0
T26	0	108	0	0
T27	0	32	0	0
T49	0	26906	0	0
T58	0	44	0	0
T62	0	3432	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593547908	425464655	0	0
T1	8152	356	0	0
T2	3476	84	0	0
T3	16480	4442	0	0
T7	10496	1160	0	0
T14	49592	2000	0	0
T15	15520	3574	0	0
T16	0	128950	0	0
T18	7316	356	0	0
T19	8296	356	0	0
T20	7296	78	0	0
T21	5936	132	0	0
T25	0	26	0	0
T26	0	1102	0	0
T27	0	8	0	0
T49	0	32232	0	0
T58	0	19478	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593547908	401911702	0	0
T1	8152	356	0	0
T2	3476	84	0	0
T3	16480	4442	0	0
T7	10496	1160	0	0
T14	49592	2000	0	0
T15	15520	3572	0	0
T16	0	128950	0	0
T18	7316	356	0	0
T19	8296	356	0	0
T20	7296	78	0	0
T21	5936	132	0	0
T25	0	26	0	0
T26	0	1102	0	0
T27	0	8	0	0
T49	0	21276	0	0
T58	0	19478	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593547908	401911702	0	0
T1	8152	356	0	0
T2	3476	84	0	0
T3	16480	4442	0	0
T7	10496	1160	0	0
T14	49592	2000	0	0
T15	15520	3572	0	0
T16	0	128950	0	0
T18	7316	356	0	0
T19	8296	356	0	0
T20	7296	78	0	0
T21	5936	132	0	0
T25	0	26	0	0
T26	0	1102	0	0
T27	0	8	0	0
T49	0	21276	0	0
T58	0	19478	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593547908	425464655	0	0
T1	8152	356	0	0
T2	3476	84	0	0
T3	16480	4442	0	0
T7	10496	1160	0	0
T14	49592	2000	0	0
T15	15520	3574	0	0
T16	0	128950	0	0
T18	7316	356	0	0
T19	8296	356	0	0
T20	7296	78	0	0
T21	5936	132	0	0
T25	0	26	0	0
T26	0	1102	0	0
T27	0	8	0	0
T49	0	32232	0	0
T58	0	19478	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593547908	1590102064	0	0
T1	8152	7828	0	0
T2	3476	3160	0	0
T3	16480	16208	0	0
T7	10496	10236	0	0
T14	49592	49388	0	0
T15	15520	15220	0	0
T18	7316	6944	0	0
T19	8296	7992	0	0
T20	7296	7064	0	0
T21	5936	5312	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T3 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T15

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T14,T15
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T14,T15
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T25,T27,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T14,T15

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T15
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T25,T27,T16
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T14,T15

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T14,T15

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398386977	397525516	0	0
CheckNGreaterZero_A	1056	1056	0	0
GntImpliesReady_A	398386977	105502412	0	0
GntImpliesValid_A	398386977	105502412	0	0
GrantKnown_A	398386977	397525516	0	0
IdxKnown_A	398386977	397525516	0	0
IndexIsCorrect_A	398386977	105502412	0	0
NoReadyValidNoGrant_A	398386977	45190696	0	0
Priority_A	398386977	111248399	0	0
ReadyAndValidImplyGrant_A	398386977	105502412	0	0
ReqAndReadyImplyGrant_A	398386977	105502412	0	0
ReqImpliesValid_A	398386977	111248399	0	0
ValidKnown_A	398386977	397525516	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	397525516	0	0
T1	2038	1957	0	0
T2	869	790	0	0
T3	4120	4052	0	0
T7	2624	2559	0	0
T14	12398	12347	0	0
T15	3880	3805	0	0
T18	1829	1736	0	0
T19	2074	1998	0	0
T20	1824	1766	0	0
T21	1484	1328	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1056	1056	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	105502412	0	0
T1	2038	32	0	0
T2	869	42	0	0
T3	4120	32	0	0
T7	2624	580	0	0
T14	12398	566	0	0
T15	3880	337	0	0
T18	1829	178	0	0
T19	2074	178	0	0
T20	1824	39	0	0
T21	1484	66	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	105502412	0	0
T1	2038	32	0	0
T2	869	42	0	0
T3	4120	32	0	0
T7	2624	580	0	0
T14	12398	566	0	0
T15	3880	337	0	0
T18	1829	178	0	0
T19	2074	178	0	0
T20	1824	39	0	0
T21	1484	66	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	397525516	0	0
T1	2038	1957	0	0
T2	869	790	0	0
T3	4120	4052	0	0
T7	2624	2559	0	0
T14	12398	12347	0	0
T15	3880	3805	0	0
T18	1829	1736	0	0
T19	2074	1998	0	0
T20	1824	1766	0	0
T21	1484	1328	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	397525516	0	0
T1	2038	1957	0	0
T2	869	790	0	0
T3	4120	4052	0	0
T7	2624	2559	0	0
T14	12398	12347	0	0
T15	3880	3805	0	0
T18	1829	1736	0	0
T19	2074	1998	0	0
T20	1824	1766	0	0
T21	1484	1328	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	105502412	0	0
T1	2038	32	0	0
T2	869	42	0	0
T3	4120	32	0	0
T7	2624	580	0	0
T14	12398	566	0	0
T15	3880	337	0	0
T18	1829	178	0	0
T19	2074	178	0	0
T20	1824	39	0	0
T21	1484	66	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	45190696	0	0
T1	2038	128	0	0
T2	869	143	0	0
T3	4120	128	0	0
T7	2624	158	0	0
T14	12398	924	0	0
T15	3880	153	0	0
T18	1829	493	0	0
T19	2074	496	0	0
T20	1824	139	0	0
T21	1484	256	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	111248399	0	0
T1	2038	32	0	0
T2	869	42	0	0
T3	4120	32	0	0
T7	2624	580	0	0
T14	12398	566	0	0
T15	3880	337	0	0
T18	1829	178	0	0
T19	2074	178	0	0
T20	1824	39	0	0
T21	1484	66	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	105502412	0	0
T1	2038	32	0	0
T2	869	42	0	0
T3	4120	32	0	0
T7	2624	580	0	0
T14	12398	566	0	0
T15	3880	337	0	0
T18	1829	178	0	0
T19	2074	178	0	0
T20	1824	39	0	0
T21	1484	66	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	105502412	0	0
T1	2038	32	0	0
T2	869	42	0	0
T3	4120	32	0	0
T7	2624	580	0	0
T14	12398	566	0	0
T15	3880	337	0	0
T18	1829	178	0	0
T19	2074	178	0	0
T20	1824	39	0	0
T21	1484	66	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	111248399	0	0
T1	2038	32	0	0
T2	869	42	0	0
T3	4120	32	0	0
T7	2624	580	0	0
T14	12398	566	0	0
T15	3880	337	0	0
T18	1829	178	0	0
T19	2074	178	0	0
T20	1824	39	0	0
T21	1484	66	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	397525516	0	0
T1	2038	1957	0	0
T2	869	790	0	0
T3	4120	4052	0	0
T7	2624	2559	0	0
T14	12398	12347	0	0
T15	3880	3805	0	0
T18	1829	1736	0	0
T19	2074	1998	0	0
T20	1824	1766	0	0
T21	1484	1328	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T3 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T15

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T14,T15
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T14,T15
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T25,T27,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T14,T15

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T15
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T25,T27,T16
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T14,T15

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T14,T15

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398386977	397525516	0	0
CheckNGreaterZero_A	1056	1056	0	0
GntImpliesReady_A	398386977	105502412	0	0
GntImpliesValid_A	398386977	105502412	0	0
GrantKnown_A	398386977	397525516	0	0
IdxKnown_A	398386977	397525516	0	0
IndexIsCorrect_A	398386977	105502412	0	0
NoReadyValidNoGrant_A	398386977	45190696	0	0
Priority_A	398386977	111248399	0	0
ReadyAndValidImplyGrant_A	398386977	105502412	0	0
ReqAndReadyImplyGrant_A	398386977	105502412	0	0
ReqImpliesValid_A	398386977	111248399	0	0
ValidKnown_A	398386977	397525516	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	397525516	0	0
T1	2038	1957	0	0
T2	869	790	0	0
T3	4120	4052	0	0
T7	2624	2559	0	0
T14	12398	12347	0	0
T15	3880	3805	0	0
T18	1829	1736	0	0
T19	2074	1998	0	0
T20	1824	1766	0	0
T21	1484	1328	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1056	1056	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	105502412	0	0
T1	2038	32	0	0
T2	869	42	0	0
T3	4120	32	0	0
T7	2624	580	0	0
T14	12398	566	0	0
T15	3880	337	0	0
T18	1829	178	0	0
T19	2074	178	0	0
T20	1824	39	0	0
T21	1484	66	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	105502412	0	0
T1	2038	32	0	0
T2	869	42	0	0
T3	4120	32	0	0
T7	2624	580	0	0
T14	12398	566	0	0
T15	3880	337	0	0
T18	1829	178	0	0
T19	2074	178	0	0
T20	1824	39	0	0
T21	1484	66	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	397525516	0	0
T1	2038	1957	0	0
T2	869	790	0	0
T3	4120	4052	0	0
T7	2624	2559	0	0
T14	12398	12347	0	0
T15	3880	3805	0	0
T18	1829	1736	0	0
T19	2074	1998	0	0
T20	1824	1766	0	0
T21	1484	1328	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	397525516	0	0
T1	2038	1957	0	0
T2	869	790	0	0
T3	4120	4052	0	0
T7	2624	2559	0	0
T14	12398	12347	0	0
T15	3880	3805	0	0
T18	1829	1736	0	0
T19	2074	1998	0	0
T20	1824	1766	0	0
T21	1484	1328	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	105502412	0	0
T1	2038	32	0	0
T2	869	42	0	0
T3	4120	32	0	0
T7	2624	580	0	0
T14	12398	566	0	0
T15	3880	337	0	0
T18	1829	178	0	0
T19	2074	178	0	0
T20	1824	39	0	0
T21	1484	66	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	45190696	0	0
T1	2038	128	0	0
T2	869	143	0	0
T3	4120	128	0	0
T7	2624	158	0	0
T14	12398	924	0	0
T15	3880	153	0	0
T18	1829	493	0	0
T19	2074	496	0	0
T20	1824	139	0	0
T21	1484	256	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	111248399	0	0
T1	2038	32	0	0
T2	869	42	0	0
T3	4120	32	0	0
T7	2624	580	0	0
T14	12398	566	0	0
T15	3880	337	0	0
T18	1829	178	0	0
T19	2074	178	0	0
T20	1824	39	0	0
T21	1484	66	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	105502412	0	0
T1	2038	32	0	0
T2	869	42	0	0
T3	4120	32	0	0
T7	2624	580	0	0
T14	12398	566	0	0
T15	3880	337	0	0
T18	1829	178	0	0
T19	2074	178	0	0
T20	1824	39	0	0
T21	1484	66	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	105502412	0	0
T1	2038	32	0	0
T2	869	42	0	0
T3	4120	32	0	0
T7	2624	580	0	0
T14	12398	566	0	0
T15	3880	337	0	0
T18	1829	178	0	0
T19	2074	178	0	0
T20	1824	39	0	0
T21	1484	66	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	111248399	0	0
T1	2038	32	0	0
T2	869	42	0	0
T3	4120	32	0	0
T7	2624	580	0	0
T14	12398	566	0	0
T15	3880	337	0	0
T18	1829	178	0	0
T19	2074	178	0	0
T20	1824	39	0	0
T21	1484	66	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	397525516	0	0
T1	2038	1957	0	0
T2	869	790	0	0
T3	4120	4052	0	0
T7	2624	2559	0	0
T14	12398	12347	0	0
T15	3880	3805	0	0
T18	1829	1736	0	0
T19	2074	1998	0	0
T20	1824	1766	0	0
T21	1484	1328	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T3 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T14
1	0	Covered	T14,T15,T25

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T14,T15,T25
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T14,T15,T25
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T25,T26
1	0	Covered	T1,T3,T14
1	1	Covered	T14,T15,T25

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T25
1	1	Covered	T1,T3,T14

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T25,T26
1	1	Covered	T1,T3,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T25

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T25

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398386977	397525516	0	0
CheckNGreaterZero_A	1056	1056	0	0
GntImpliesReady_A	398386977	95453368	0	0
GntImpliesValid_A	398386977	95453368	0	0
GrantKnown_A	398386977	397525516	0	0
IdxKnown_A	398386977	397525516	0	0
IndexIsCorrect_A	398386977	95453368	0	0
NoReadyValidNoGrant_A	398386977	42244808	0	0
Priority_A	398386977	101483799	0	0
ReadyAndValidImplyGrant_A	398386977	95453368	0	0
ReqAndReadyImplyGrant_A	398386977	95453368	0	0
ReqImpliesValid_A	398386977	101483799	0	0
ValidKnown_A	398386977	397525516	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	397525516	0	0
T1	2038	1957	0	0
T2	869	790	0	0
T3	4120	4052	0	0
T7	2624	2559	0	0
T14	12398	12347	0	0
T15	3880	3805	0	0
T18	1829	1736	0	0
T19	2074	1998	0	0
T20	1824	1766	0	0
T21	1484	1328	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1056	1056	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	95453368	0	0
T1	2038	146	0	0
T2	869	0	0	0
T3	4120	2189	0	0
T7	2624	0	0	0
T14	12398	434	0	0
T15	3880	1449	0	0
T16	0	64475	0	0
T18	1829	0	0	0
T19	2074	0	0	0
T20	1824	0	0	0
T21	1484	0	0	0
T25	0	13	0	0
T26	0	551	0	0
T27	0	4	0	0
T49	0	10638	0	0
T58	0	9739	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	95453368	0	0
T1	2038	146	0	0
T2	869	0	0	0
T3	4120	2189	0	0
T7	2624	0	0	0
T14	12398	434	0	0
T15	3880	1449	0	0
T16	0	64475	0	0
T18	1829	0	0	0
T19	2074	0	0	0
T20	1824	0	0	0
T21	1484	0	0	0
T25	0	13	0	0
T26	0	551	0	0
T27	0	4	0	0
T49	0	10638	0	0
T58	0	9739	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	397525516	0	0
T1	2038	1957	0	0
T2	869	790	0	0
T3	4120	4052	0	0
T7	2624	2559	0	0
T14	12398	12347	0	0
T15	3880	3805	0	0
T18	1829	1736	0	0
T19	2074	1998	0	0
T20	1824	1766	0	0
T21	1484	1328	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	397525516	0	0
T1	2038	1957	0	0
T2	869	790	0	0
T3	4120	4052	0	0
T7	2624	2559	0	0
T14	12398	12347	0	0
T15	3880	3805	0	0
T18	1829	1736	0	0
T19	2074	1998	0	0
T20	1824	1766	0	0
T21	1484	1328	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	95453368	0	0
T1	2038	146	0	0
T2	869	0	0	0
T3	4120	2189	0	0
T7	2624	0	0	0
T14	12398	434	0	0
T15	3880	1449	0	0
T16	0	64475	0	0
T18	1829	0	0	0
T19	2074	0	0	0
T20	1824	0	0	0
T21	1484	0	0	0
T25	0	13	0	0
T26	0	551	0	0
T27	0	4	0	0
T49	0	10638	0	0
T58	0	9739	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	42244808	0	0
T1	2038	220	0	0
T2	869	0	0	0
T3	4120	0	0	0
T7	2624	0	0	0
T14	12398	652	0	0
T15	3880	121	0	0
T16	0	2419	0	0
T18	1829	0	0	0
T19	2074	0	0	0
T20	1824	0	0	0
T21	1484	0	0	0
T25	0	37	0	0
T26	0	54	0	0
T27	0	16	0	0
T49	0	13453	0	0
T58	0	22	0	0
T62	0	1716	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	101483799	0	0
T1	2038	146	0	0
T2	869	0	0	0
T3	4120	2189	0	0
T7	2624	0	0	0
T14	12398	434	0	0
T15	3880	1450	0	0
T16	0	64475	0	0
T18	1829	0	0	0
T19	2074	0	0	0
T20	1824	0	0	0
T21	1484	0	0	0
T25	0	13	0	0
T26	0	551	0	0
T27	0	4	0	0
T49	0	16116	0	0
T58	0	9739	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	95453368	0	0
T1	2038	146	0	0
T2	869	0	0	0
T3	4120	2189	0	0
T7	2624	0	0	0
T14	12398	434	0	0
T15	3880	1449	0	0
T16	0	64475	0	0
T18	1829	0	0	0
T19	2074	0	0	0
T20	1824	0	0	0
T21	1484	0	0	0
T25	0	13	0	0
T26	0	551	0	0
T27	0	4	0	0
T49	0	10638	0	0
T58	0	9739	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	95453368	0	0
T1	2038	146	0	0
T2	869	0	0	0
T3	4120	2189	0	0
T7	2624	0	0	0
T14	12398	434	0	0
T15	3880	1449	0	0
T16	0	64475	0	0
T18	1829	0	0	0
T19	2074	0	0	0
T20	1824	0	0	0
T21	1484	0	0	0
T25	0	13	0	0
T26	0	551	0	0
T27	0	4	0	0
T49	0	10638	0	0
T58	0	9739	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	101483799	0	0
T1	2038	146	0	0
T2	869	0	0	0
T3	4120	2189	0	0
T7	2624	0	0	0
T14	12398	434	0	0
T15	3880	1450	0	0
T16	0	64475	0	0
T18	1829	0	0	0
T19	2074	0	0	0
T20	1824	0	0	0
T21	1484	0	0	0
T25	0	13	0	0
T26	0	551	0	0
T27	0	4	0	0
T49	0	16116	0	0
T58	0	9739	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	397525516	0	0
T1	2038	1957	0	0
T2	869	790	0	0
T3	4120	4052	0	0
T7	2624	2559	0	0
T14	12398	12347	0	0
T15	3880	3805	0	0
T18	1829	1736	0	0
T19	2074	1998	0	0
T20	1824	1766	0	0
T21	1484	1328	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T3 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T14
1	0	Covered	T14,T15,T25

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T14,T15,T25
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T14,T15,T25
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T25,T26
1	0	Covered	T1,T3,T14
1	1	Covered	T14,T15,T25

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T25
1	1	Covered	T1,T3,T14

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T25,T26
1	1	Covered	T1,T3,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T25

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T15,T25

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398386977	397525516	0	0
CheckNGreaterZero_A	1056	1056	0	0
GntImpliesReady_A	398386977	95453510	0	0
GntImpliesValid_A	398386977	95453510	0	0
GrantKnown_A	398386977	397525516	0	0
IdxKnown_A	398386977	397525516	0	0
IndexIsCorrect_A	398386977	95453510	0	0
NoReadyValidNoGrant_A	398386977	42244691	0	0
Priority_A	398386977	101484058	0	0
ReadyAndValidImplyGrant_A	398386977	95453510	0	0
ReqAndReadyImplyGrant_A	398386977	95453510	0	0
ReqImpliesValid_A	398386977	101484058	0	0
ValidKnown_A	398386977	397525516	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	397525516	0	0
T1	2038	1957	0	0
T2	869	790	0	0
T3	4120	4052	0	0
T7	2624	2559	0	0
T14	12398	12347	0	0
T15	3880	3805	0	0
T18	1829	1736	0	0
T19	2074	1998	0	0
T20	1824	1766	0	0
T21	1484	1328	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1056	1056	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	95453510	0	0
T1	2038	146	0	0
T2	869	0	0	0
T3	4120	2189	0	0
T7	2624	0	0	0
T14	12398	434	0	0
T15	3880	1449	0	0
T16	0	64475	0	0
T18	1829	0	0	0
T19	2074	0	0	0
T20	1824	0	0	0
T21	1484	0	0	0
T25	0	13	0	0
T26	0	551	0	0
T27	0	4	0	0
T49	0	10638	0	0
T58	0	9739	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	95453510	0	0
T1	2038	146	0	0
T2	869	0	0	0
T3	4120	2189	0	0
T7	2624	0	0	0
T14	12398	434	0	0
T15	3880	1449	0	0
T16	0	64475	0	0
T18	1829	0	0	0
T19	2074	0	0	0
T20	1824	0	0	0
T21	1484	0	0	0
T25	0	13	0	0
T26	0	551	0	0
T27	0	4	0	0
T49	0	10638	0	0
T58	0	9739	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	397525516	0	0
T1	2038	1957	0	0
T2	869	790	0	0
T3	4120	4052	0	0
T7	2624	2559	0	0
T14	12398	12347	0	0
T15	3880	3805	0	0
T18	1829	1736	0	0
T19	2074	1998	0	0
T20	1824	1766	0	0
T21	1484	1328	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	397525516	0	0
T1	2038	1957	0	0
T2	869	790	0	0
T3	4120	4052	0	0
T7	2624	2559	0	0
T14	12398	12347	0	0
T15	3880	3805	0	0
T18	1829	1736	0	0
T19	2074	1998	0	0
T20	1824	1766	0	0
T21	1484	1328	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	95453510	0	0
T1	2038	146	0	0
T2	869	0	0	0
T3	4120	2189	0	0
T7	2624	0	0	0
T14	12398	434	0	0
T15	3880	1449	0	0
T16	0	64475	0	0
T18	1829	0	0	0
T19	2074	0	0	0
T20	1824	0	0	0
T21	1484	0	0	0
T25	0	13	0	0
T26	0	551	0	0
T27	0	4	0	0
T49	0	10638	0	0
T58	0	9739	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	42244691	0	0
T1	2038	220	0	0
T2	869	0	0	0
T3	4120	0	0	0
T7	2624	0	0	0
T14	12398	652	0	0
T15	3880	121	0	0
T16	0	2419	0	0
T18	1829	0	0	0
T19	2074	0	0	0
T20	1824	0	0	0
T21	1484	0	0	0
T25	0	37	0	0
T26	0	54	0	0
T27	0	16	0	0
T49	0	13453	0	0
T58	0	22	0	0
T62	0	1716	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	101484058	0	0
T1	2038	146	0	0
T2	869	0	0	0
T3	4120	2189	0	0
T7	2624	0	0	0
T14	12398	434	0	0
T15	3880	1450	0	0
T16	0	64475	0	0
T18	1829	0	0	0
T19	2074	0	0	0
T20	1824	0	0	0
T21	1484	0	0	0
T25	0	13	0	0
T26	0	551	0	0
T27	0	4	0	0
T49	0	16116	0	0
T58	0	9739	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	95453510	0	0
T1	2038	146	0	0
T2	869	0	0	0
T3	4120	2189	0	0
T7	2624	0	0	0
T14	12398	434	0	0
T15	3880	1449	0	0
T16	0	64475	0	0
T18	1829	0	0	0
T19	2074	0	0	0
T20	1824	0	0	0
T21	1484	0	0	0
T25	0	13	0	0
T26	0	551	0	0
T27	0	4	0	0
T49	0	10638	0	0
T58	0	9739	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	95453510	0	0
T1	2038	146	0	0
T2	869	0	0	0
T3	4120	2189	0	0
T7	2624	0	0	0
T14	12398	434	0	0
T15	3880	1449	0	0
T16	0	64475	0	0
T18	1829	0	0	0
T19	2074	0	0	0
T20	1824	0	0	0
T21	1484	0	0	0
T25	0	13	0	0
T26	0	551	0	0
T27	0	4	0	0
T49	0	10638	0	0
T58	0	9739	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	101484058	0	0
T1	2038	146	0	0
T2	869	0	0	0
T3	4120	2189	0	0
T7	2624	0	0	0
T14	12398	434	0	0
T15	3880	1450	0	0
T16	0	64475	0	0
T18	1829	0	0	0
T19	2074	0	0	0
T20	1824	0	0	0
T21	1484	0	0	0
T25	0	13	0	0
T26	0	551	0	0
T27	0	4	0	0
T49	0	16116	0	0
T58	0	9739	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	397525516	0	0
T1	2038	1957	0	0
T2	869	790	0	0
T3	4120	4052	0	0
T7	2624	2559	0	0
T14	12398	12347	0	0
T15	3880	3805	0	0
T18	1829	1736	0	0
T19	2074	1998	0	0
T20	1824	1766	0	0
T21	1484	1328	0	0