Unified Coverage Report :: Module :: flash_phy_rd_buffers

Module : flash_phy_rd_buffers

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.82	100.00	91.27			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.82	100.00	91.27			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.82	100.00	91.27			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.82	100.00	91.27			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.76	100.00	91.05			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.76	100.00	91.05			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.76	100.00	91.05			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.76	100.00	91.05			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : flash_phy_rd_buffers

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T77 T78 T12 
47         1/1                out_o.err <= '0;
           Tests:       T77 T78 T12 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T7 T15 T25 
50         1/1                out_o.err <= '0;
           Tests:       T7 T15 T25 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T1 T2 T7 
53         1/1                out_o.part <= part_i;
           Tests:       T1 T2 T7 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T1 T2 T7 
55         1/1                out_o.attr <= Wip;
           Tests:       T1 T2 T7 
56         1/1                out_o.err <= '0;
           Tests:       T1 T2 T7 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T1 T2 T7 
59         1/1                out_o.attr <= Valid;
           Tests:       T1 T2 T7 
60         1/1                out_o.err <= err_i;
           Tests:       T1 T2 T7 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Module : flash_phy_rd_buffers

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T77,T78,T79

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T15,T25

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Module : flash_phy_rd_buffers

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T77,T78,T12
0	0	1	-	-	Covered	T7,T15,T25
0	0	0	1	-	Covered	T1,T2,T7
0	0	0	0	1	Covered	T1,T2,T7
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd_buffers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	2147483647	5156546	0	0
UpdateCheck_A	2147483647	5156531	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5156546	0	0
T1	8152	74	0	0
T2	6952	5	0	0
T3	32960	0	0	0
T7	20992	10	0	0
T14	99184	528	0	0
T15	31040	83	0	0
T16	0	810	0	0
T18	14632	73	0	0
T19	16592	74	0	0
T20	14592	4	0	0
T21	11872	0	0	0
T25	0	36	0	0
T26	0	120	0	0
T27	0	4	0	0
T49	0	9639	0	0
T58	189968	630	0	0
T62	0	576	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5156531	0	0
T1	8152	74	0	0
T2	6952	5	0	0
T3	32960	0	0	0
T7	20992	10	0	0
T14	99184	528	0	0
T15	31040	83	0	0
T16	0	810	0	0
T18	14632	73	0	0
T19	16592	74	0	0
T20	14592	4	0	0
T21	11872	0	0	0
T25	0	36	0	0
T26	0	120	0	0
T27	0	4	0	0
T49	0	9639	0	0
T58	189968	630	0	0
T62	0	576	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T12 T79 T80 
47         1/1                out_o.err <= '0;
           Tests:       T12 T79 T80 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T7 T15 T26 
50         1/1                out_o.err <= '0;
           Tests:       T7 T15 T26 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T2 T7 T14 
53         1/1                out_o.part <= part_i;
           Tests:       T2 T7 T14 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T2 T7 T14 
55         1/1                out_o.attr <= Wip;
           Tests:       T2 T7 T14 
56         1/1                out_o.err <= '0;
           Tests:       T2 T7 T14 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T2 T7 T14 
59         1/1                out_o.attr <= Valid;
           Tests:       T2 T7 T14 
60         1/1                out_o.err <= err_i;
           Tests:       T2 T7 T14 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T79,T80,T81

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T14

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T15,T26

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T14

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T12,T79,T80
0	0	1	-	-	Covered	T7,T15,T26
0	0	0	1	-	Covered	T2,T7,T14
0	0	0	0	1	Covered	T2,T7,T14
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	398386977	656460	0	0
UpdateCheck_A	398386977	656457	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	656460	0	0
T2	869	2	0	0
T3	4120	0	0	0
T7	2624	3	0	0
T14	12398	73	0	0
T15	3880	4	0	0
T18	1829	19	0	0
T19	2074	19	0	0
T20	1824	1	0	0
T21	1484	0	0	0
T25	0	7	0	0
T26	0	24	0	0
T58	47492	157	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	656457	0	0
T2	869	2	0	0
T3	4120	0	0	0
T7	2624	3	0	0
T14	12398	73	0	0
T15	3880	4	0	0
T18	1829	19	0	0
T19	2074	19	0	0
T20	1824	1	0	0
T21	1484	0	0	0
T25	0	7	0	0
T26	0	24	0	0
T58	47492	157	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T12 T79 T80 
47         1/1                out_o.err <= '0;
           Tests:       T12 T79 T80 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T7 T15 T26 
50         1/1                out_o.err <= '0;
           Tests:       T7 T15 T26 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T2 T7 T14 
53         1/1                out_o.part <= part_i;
           Tests:       T2 T7 T14 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T2 T7 T14 
55         1/1                out_o.attr <= Wip;
           Tests:       T2 T7 T14 
56         1/1                out_o.err <= '0;
           Tests:       T2 T7 T14 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T2 T7 T14 
59         1/1                out_o.attr <= Valid;
           Tests:       T2 T7 T14 
60         1/1                out_o.err <= err_i;
           Tests:       T2 T7 T14 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T79,T80,T81

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T14

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T15,T26

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T14

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T12,T79,T80
0	0	1	-	-	Covered	T7,T15,T26
0	0	0	1	-	Covered	T2,T7,T14
0	0	0	0	1	Covered	T2,T7,T14
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	398386977	656629	0	0
UpdateCheck_A	398386977	656625	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	656629	0	0
T2	869	1	0	0
T3	4120	0	0	0
T7	2624	3	0	0
T14	12398	73	0	0
T15	3880	3	0	0
T18	1829	18	0	0
T19	2074	19	0	0
T20	1824	1	0	0
T21	1484	0	0	0
T25	0	7	0	0
T26	0	25	0	0
T58	47492	156	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	656625	0	0
T2	869	1	0	0
T3	4120	0	0	0
T7	2624	3	0	0
T14	12398	73	0	0
T15	3880	3	0	0
T18	1829	18	0	0
T19	2074	19	0	0
T20	1824	1	0	0
T21	1484	0	0	0
T25	0	7	0	0
T26	0	25	0	0
T58	47492	156	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T12 T79 T81 
47         1/1                out_o.err <= '0;
           Tests:       T12 T79 T81 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T7 T15 T25 
50         1/1                out_o.err <= '0;
           Tests:       T7 T15 T25 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T2 T7 T14 
53         1/1                out_o.part <= part_i;
           Tests:       T2 T7 T14 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T2 T7 T14 
55         1/1                out_o.attr <= Wip;
           Tests:       T2 T7 T14 
56         1/1                out_o.err <= '0;
           Tests:       T2 T7 T14 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T2 T7 T14 
59         1/1                out_o.attr <= Valid;
           Tests:       T2 T7 T14 
60         1/1                out_o.err <= err_i;
           Tests:       T2 T7 T14 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T79,T81,T82

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T14

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T15,T25

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T14

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T12,T79,T81
0	0	1	-	-	Covered	T7,T15,T25
0	0	0	1	-	Covered	T2,T7,T14
0	0	0	0	1	Covered	T2,T7,T14
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	398386977	655993	0	0
UpdateCheck_A	398386977	655991	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	655993	0	0
T2	869	1	0	0
T3	4120	0	0	0
T7	2624	2	0	0
T14	12398	73	0	0
T15	3880	3	0	0
T18	1829	18	0	0
T19	2074	18	0	0
T20	1824	1	0	0
T21	1484	0	0	0
T25	0	8	0	0
T26	0	27	0	0
T58	47492	156	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	655991	0	0
T2	869	1	0	0
T3	4120	0	0	0
T7	2624	2	0	0
T14	12398	73	0	0
T15	3880	3	0	0
T18	1829	18	0	0
T19	2074	18	0	0
T20	1824	1	0	0
T21	1484	0	0	0
T25	0	8	0	0
T26	0	27	0	0
T58	47492	156	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T12 T79 T81 
47         1/1                out_o.err <= '0;
           Tests:       T12 T79 T81 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T7 T15 T26 
50         1/1                out_o.err <= '0;
           Tests:       T7 T15 T26 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T2 T7 T14 
53         1/1                out_o.part <= part_i;
           Tests:       T2 T7 T14 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T2 T7 T14 
55         1/1                out_o.attr <= Wip;
           Tests:       T2 T7 T14 
56         1/1                out_o.err <= '0;
           Tests:       T2 T7 T14 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T2 T7 T14 
59         1/1                out_o.attr <= Valid;
           Tests:       T2 T7 T14 
60         1/1                out_o.err <= err_i;
           Tests:       T2 T7 T14 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T79,T81,T82

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T14

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T15,T26

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T14

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T12,T79,T81
0	0	1	-	-	Covered	T7,T15,T26
0	0	0	1	-	Covered	T2,T7,T14
0	0	0	0	1	Covered	T2,T7,T14
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	398386977	655849	0	0
UpdateCheck_A	398386977	655849	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	655849	0	0
T2	869	1	0	0
T3	4120	0	0	0
T7	2624	2	0	0
T14	12398	72	0	0
T15	3880	3	0	0
T18	1829	18	0	0
T19	2074	18	0	0
T20	1824	1	0	0
T21	1484	0	0	0
T25	0	6	0	0
T26	0	25	0	0
T58	47492	156	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	655849	0	0
T2	869	1	0	0
T3	4120	0	0	0
T7	2624	2	0	0
T14	12398	72	0	0
T15	3880	3	0	0
T18	1829	18	0	0
T19	2074	18	0	0
T20	1824	1	0	0
T21	1484	0	0	0
T25	0	6	0	0
T26	0	25	0	0
T58	47492	156	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T77 T78 T12 
47         1/1                out_o.err <= '0;
           Tests:       T77 T78 T12 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T15 T71 T83 
50         1/1                out_o.err <= '0;
           Tests:       T15 T71 T83 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T1 T14 T15 
53         1/1                out_o.part <= part_i;
           Tests:       T1 T14 T15 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T1 T14 T15 
55         1/1                out_o.attr <= Wip;
           Tests:       T1 T14 T15 
56         1/1                out_o.err <= '0;
           Tests:       T1 T14 T15 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T1 T14 T15 
59         1/1                out_o.attr <= Valid;
           Tests:       T1 T14 T15 
60         1/1                out_o.err <= err_i;
           Tests:       T1 T14 T15 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T77,T78,T79

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T14,T15

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T71,T83

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T14,T15

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T14,T15

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T77,T78,T12
0	0	1	-	-	Covered	T15,T71,T83
0	0	0	1	-	Covered	T1,T14,T15
0	0	0	0	1	Covered	T1,T14,T15
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	398386977	633315	0	0
UpdateCheck_A	398386977	633313	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	633315	0	0
T1	2038	19	0	0
T2	869	0	0	0
T3	4120	0	0	0
T7	2624	0	0	0
T14	12398	60	0	0
T15	3880	18	0	0
T16	0	203	0	0
T18	1829	0	0	0
T19	2074	0	0	0
T20	1824	0	0	0
T21	1484	0	0	0
T25	0	2	0	0
T26	0	5	0	0
T27	0	1	0	0
T49	0	2403	0	0
T58	0	2	0	0
T62	0	144	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	633313	0	0
T1	2038	19	0	0
T2	869	0	0	0
T3	4120	0	0	0
T7	2624	0	0	0
T14	12398	60	0	0
T15	3880	18	0	0
T16	0	203	0	0
T18	1829	0	0	0
T19	2074	0	0	0
T20	1824	0	0	0
T21	1484	0	0	0
T25	0	2	0	0
T26	0	5	0	0
T27	0	1	0	0
T49	0	2403	0	0
T58	0	2	0	0
T62	0	144	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T77 T78 T12 
47         1/1                out_o.err <= '0;
           Tests:       T77 T78 T12 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T15 T71 T83 
50         1/1                out_o.err <= '0;
           Tests:       T15 T71 T83 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T1 T14 T15 
53         1/1                out_o.part <= part_i;
           Tests:       T1 T14 T15 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T1 T14 T15 
55         1/1                out_o.attr <= Wip;
           Tests:       T1 T14 T15 
56         1/1                out_o.err <= '0;
           Tests:       T1 T14 T15 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T1 T14 T15 
59         1/1                out_o.attr <= Valid;
           Tests:       T1 T14 T15 
60         1/1                out_o.err <= err_i;
           Tests:       T1 T14 T15 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T77,T78,T79

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T14,T15

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T71,T83

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T14,T15

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T14,T15

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T77,T78,T12
0	0	1	-	-	Covered	T15,T71,T83
0	0	0	1	-	Covered	T1,T14,T15
0	0	0	0	1	Covered	T1,T14,T15
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	398386977	633176	0	0
UpdateCheck_A	398386977	633176	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	633176	0	0
T1	2038	19	0	0
T2	869	0	0	0
T3	4120	0	0	0
T7	2624	0	0	0
T14	12398	59	0	0
T15	3880	18	0	0
T16	0	203	0	0
T18	1829	0	0	0
T19	2074	0	0	0
T20	1824	0	0	0
T21	1484	0	0	0
T25	0	2	0	0
T26	0	5	0	0
T27	0	1	0	0
T49	0	2412	0	0
T58	0	1	0	0
T62	0	144	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	633176	0	0
T1	2038	19	0	0
T2	869	0	0	0
T3	4120	0	0	0
T7	2624	0	0	0
T14	12398	59	0	0
T15	3880	18	0	0
T16	0	203	0	0
T18	1829	0	0	0
T19	2074	0	0	0
T20	1824	0	0	0
T21	1484	0	0	0
T25	0	2	0	0
T26	0	5	0	0
T27	0	1	0	0
T49	0	2412	0	0
T58	0	1	0	0
T62	0	144	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T77 T12 T79 
47         1/1                out_o.err <= '0;
           Tests:       T77 T12 T79 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T15 T71 T83 
50         1/1                out_o.err <= '0;
           Tests:       T15 T71 T83 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T1 T14 T15 
53         1/1                out_o.part <= part_i;
           Tests:       T1 T14 T15 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T1 T14 T15 
55         1/1                out_o.attr <= Wip;
           Tests:       T1 T14 T15 
56         1/1                out_o.err <= '0;
           Tests:       T1 T14 T15 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T1 T14 T15 
59         1/1                out_o.attr <= Valid;
           Tests:       T1 T14 T15 
60         1/1                out_o.err <= err_i;
           Tests:       T1 T14 T15 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T77,T79,T81

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T14,T15

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T71,T83

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T14,T15

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T14,T15

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T77,T12,T79
0	0	1	-	-	Covered	T15,T71,T83
0	0	0	1	-	Covered	T1,T14,T15
0	0	0	0	1	Covered	T1,T14,T15
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	398386977	632730	0	0
UpdateCheck_A	398386977	632726	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	632730	0	0
T1	2038	18	0	0
T2	869	0	0	0
T3	4120	0	0	0
T7	2624	0	0	0
T14	12398	59	0	0
T15	3880	18	0	0
T16	0	202	0	0
T18	1829	0	0	0
T19	2074	0	0	0
T20	1824	0	0	0
T21	1484	0	0	0
T25	0	2	0	0
T26	0	5	0	0
T27	0	1	0	0
T49	0	2409	0	0
T58	0	1	0	0
T62	0	144	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	632726	0	0
T1	2038	18	0	0
T2	869	0	0	0
T3	4120	0	0	0
T7	2624	0	0	0
T14	12398	59	0	0
T15	3880	18	0	0
T16	0	202	0	0
T18	1829	0	0	0
T19	2074	0	0	0
T20	1824	0	0	0
T21	1484	0	0	0
T25	0	2	0	0
T26	0	5	0	0
T27	0	1	0	0
T49	0	2409	0	0
T58	0	1	0	0
T62	0	144	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

37                        always_ff @(posedge clk_i or negedge rst_ni) begin
38         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
39         1/1                out_o.data <= '0;
           Tests:       T1 T2 T3 
40         1/1                out_o.addr <= '0;
           Tests:       T1 T2 T3 
41         1/1                out_o.part <= flash_ctrl_pkg::FlashPartData;
           Tests:       T1 T2 T3 
42         1/1                out_o.info_sel <= '0;
           Tests:       T1 T2 T3 
43         1/1                out_o.attr <= Invalid;
           Tests:       T1 T2 T3 
44         1/1                out_o.err <= '0;
           Tests:       T1 T2 T3 
45         1/1              end else if (!en_i && out_o.attr != Invalid) begin
           Tests:       T1 T2 T3 
46         1/1                out_o.attr <= Invalid;
           Tests:       T77 T12 T79 
47         1/1                out_o.err <= '0;
           Tests:       T77 T12 T79 
48         1/1              end else if (wipe_i && en_i) begin
           Tests:       T1 T2 T3 
49         1/1                out_o.attr <= Invalid;
           Tests:       T15 T71 T83 
50         1/1                out_o.err <= '0;
           Tests:       T15 T71 T83 
51         1/1              end else if (alloc_i && en_i) begin
           Tests:       T1 T2 T3 
52         1/1                out_o.addr <= addr_i;
           Tests:       T1 T14 T15 
53         1/1                out_o.part <= part_i;
           Tests:       T1 T14 T15 
54         1/1                out_o.info_sel <= info_sel_i;
           Tests:       T1 T14 T15 
55         1/1                out_o.attr <= Wip;
           Tests:       T1 T14 T15 
56         1/1                out_o.err <= '0;
           Tests:       T1 T14 T15 
57         1/1              end else if (update_i && en_i) begin
           Tests:       T1 T2 T3 
58         1/1                out_o.data <= data_i;
           Tests:       T1 T14 T15 
59         1/1                out_o.attr <= Valid;
           Tests:       T1 T14 T15 
60         1/1                out_o.err <= err_i;
           Tests:       T1 T14 T15 
61                          end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T77,T79,T81

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T14,T15

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T71,T83

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T14,T15

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T14,T15

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

38             if (!rst_ni) begin
               -1-  
39               out_o.data <= '0;
                 ==>
40               out_o.addr <= '0;
41               out_o.part <= flash_ctrl_pkg::FlashPartData;
42               out_o.info_sel <= '0;
43               out_o.attr <= Invalid;
44               out_o.err <= '0;
45             end else if (!en_i && out_o.attr != Invalid) begin
                        -2-  
46               out_o.attr <= Invalid;
                 ==>
47               out_o.err <= '0;
48             end else if (wipe_i && en_i) begin
                        -3-  
49               out_o.attr <= Invalid;
                 ==>
50               out_o.err <= '0;
51             end else if (alloc_i && en_i) begin
                        -4-  
52               out_o.addr <= addr_i;
                 ==>
53               out_o.part <= part_i;
54               out_o.info_sel <= info_sel_i;
55               out_o.attr <= Wip;
56               out_o.err <= '0;
57             end else if (update_i && en_i) begin
                        -5-  
58               out_o.data <= data_i;
                 ==>
59               out_o.attr <= Valid;
60               out_o.err <= err_i;
61             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T77,T12,T79
0	0	1	-	-	Covered	T15,T71,T83
0	0	0	1	-	Covered	T1,T14,T15
0	0	0	0	1	Covered	T1,T14,T15
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	398386977	632394	0	0
UpdateCheck_A	398386977	632394	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	632394	0	0
T1	2038	18	0	0
T2	869	0	0	0
T3	4120	0	0	0
T7	2624	0	0	0
T14	12398	59	0	0
T15	3880	16	0	0
T16	0	202	0	0
T18	1829	0	0	0
T19	2074	0	0	0
T20	1824	0	0	0
T21	1484	0	0	0
T25	0	2	0	0
T26	0	4	0	0
T27	0	1	0	0
T49	0	2415	0	0
T58	0	1	0	0
T62	0	144	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398386977	632394	0	0
T1	2038	18	0	0
T2	869	0	0	0
T3	4120	0	0	0
T7	2624	0	0	0
T14	12398	59	0	0
T15	3880	16	0	0
T16	0	202	0	0
T18	1829	0	0	0
T19	2074	0	0	0
T20	1824	0	0	0
T21	1484	0	0	0
T25	0	2	0	0
T26	0	4	0	0
T27	0	1	0	0
T49	0	2415	0	0
T58	0	1	0	0
T62	0	144	0	0