Unified Coverage Report :: Module :: flash_ctrl_core_csr_assert_fpv

Module : flash_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_flash_ctrl_csr_assert_0/flash_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.flash_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.flash_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.69	97.12	93.60	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : flash_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	87	87	100.00	87	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	87	87	100.00	87	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	396824248	4171	0	0
addr_rd_A	396824248	1279	0	0
bank0_info0_page_cfg_0_rd_A	396824248	2903	0	0
bank0_info0_page_cfg_1_rd_A	396824248	2934	0	0
bank0_info0_page_cfg_2_rd_A	396824248	2614	0	0
bank0_info0_page_cfg_3_rd_A	396824248	2741	0	0
bank0_info0_page_cfg_4_rd_A	396824248	2832	0	0
bank0_info0_page_cfg_5_rd_A	396824248	2788	0	0
bank0_info0_page_cfg_6_rd_A	396824248	2854	0	0
bank0_info0_page_cfg_7_rd_A	396824248	3143	0	0
bank0_info0_page_cfg_8_rd_A	396824248	2654	0	0
bank0_info0_page_cfg_9_rd_A	396824248	2862	0	0
bank0_info0_regwen_0_rd_A	396824248	1330	0	0
bank0_info0_regwen_1_rd_A	396824248	1253	0	0
bank0_info0_regwen_2_rd_A	396824248	1162	0	0
bank0_info0_regwen_3_rd_A	396824248	1136	0	0
bank0_info0_regwen_4_rd_A	396824248	939	0	0
bank0_info0_regwen_5_rd_A	396824248	1352	0	0
bank0_info0_regwen_6_rd_A	396824248	1206	0	0
bank0_info0_regwen_7_rd_A	396824248	1200	0	0
bank0_info0_regwen_8_rd_A	396824248	1264	0	0
bank0_info0_regwen_9_rd_A	396824248	1291	0	0
bank0_info1_page_cfg_rd_A	396824248	2580	0	0
bank0_info1_regwen_rd_A	396824248	903	0	0
bank0_info2_page_cfg_0_rd_A	396824248	3004	0	0
bank0_info2_page_cfg_1_rd_A	396824248	2745	0	0
bank0_info2_regwen_0_rd_A	396824248	1257	0	0
bank0_info2_regwen_1_rd_A	396824248	1388	0	0
bank1_info0_page_cfg_0_rd_A	396824248	2473	0	0
bank1_info0_page_cfg_1_rd_A	396824248	2739	0	0
bank1_info0_page_cfg_2_rd_A	396824248	2985	0	0
bank1_info0_page_cfg_3_rd_A	396824248	3135	0	0
bank1_info0_page_cfg_4_rd_A	396824248	2827	0	0
bank1_info0_page_cfg_5_rd_A	396824248	3104	0	0
bank1_info0_page_cfg_6_rd_A	396824248	2832	0	0
bank1_info0_page_cfg_7_rd_A	396824248	2495	0	0
bank1_info0_page_cfg_8_rd_A	396824248	3165	0	0
bank1_info0_page_cfg_9_rd_A	396824248	2486	0	0
bank1_info0_regwen_0_rd_A	396824248	1295	0	0
bank1_info0_regwen_1_rd_A	396824248	1325	0	0
bank1_info0_regwen_2_rd_A	396824248	1391	0	0
bank1_info0_regwen_3_rd_A	396824248	1290	0	0
bank1_info0_regwen_4_rd_A	396824248	1133	0	0
bank1_info0_regwen_5_rd_A	396824248	1297	0	0
bank1_info0_regwen_6_rd_A	396824248	1355	0	0
bank1_info0_regwen_7_rd_A	396824248	1363	0	0
bank1_info0_regwen_8_rd_A	396824248	1323	0	0
bank1_info0_regwen_9_rd_A	396824248	1306	0	0
bank1_info1_page_cfg_rd_A	396824248	2830	0	0
bank1_info1_regwen_rd_A	396824248	1258	0	0
bank1_info2_page_cfg_0_rd_A	396824248	2950	0	0
bank1_info2_page_cfg_1_rd_A	396824248	2685	0	0
bank1_info2_regwen_0_rd_A	396824248	1135	0	0
bank1_info2_regwen_1_rd_A	396824248	1270	0	0
bank_cfg_regwen_rd_A	396824248	1167	0	0
default_region_rd_A	396824248	2436	0	0
exec_rd_A	396824248	1133	0	0
fifo_lvl_rd_A	396824248	1501	0	0
fifo_rst_rd_A	396824248	1266	0	0
hw_info_cfg_override_rd_A	396824248	1533	0	0
intr_enable_rd_A	396824248	2409	0	0
mp_region_0_rd_A	396824248	1301	0	0
mp_region_1_rd_A	396824248	1539	0	0
mp_region_2_rd_A	396824248	1567	0	0
mp_region_3_rd_A	396824248	1485	0	0
mp_region_4_rd_A	396824248	1339	0	0
mp_region_5_rd_A	396824248	1512	0	0
mp_region_6_rd_A	396824248	1444	0	0
mp_region_7_rd_A	396824248	1628	0	0
mp_region_cfg_0_rd_A	396824248	2765	0	0
mp_region_cfg_1_rd_A	396824248	2748	0	0
mp_region_cfg_2_rd_A	396824248	2608	0	0
mp_region_cfg_3_rd_A	396824248	2629	0	0
mp_region_cfg_4_rd_A	396824248	3000	0	0
mp_region_cfg_5_rd_A	396824248	2805	0	0
mp_region_cfg_6_rd_A	396824248	2667	0	0
mp_region_cfg_7_rd_A	396824248	2821	0	0
phy_alert_cfg_rd_A	396824248	464	0	0
region_cfg_regwen_0_rd_A	396824248	1250	0	0
region_cfg_regwen_1_rd_A	396824248	1336	0	0
region_cfg_regwen_2_rd_A	396824248	1307	0	0
region_cfg_regwen_3_rd_A	396824248	1042	0	0
region_cfg_regwen_4_rd_A	396824248	1353	0	0
region_cfg_regwen_5_rd_A	396824248	1240	0	0
region_cfg_regwen_6_rd_A	396824248	903	0	0
region_cfg_regwen_7_rd_A	396824248	1283	0	0
scratch_rd_A	396824248	987	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	4171	0	0
T72	8908	4	0	0
T124	2369	246	0	0
T125	2538	2	0	0
T126	4358	7	0	0
T127	6183	275	0	0
T221	3526	71	0	0
T224	3869	57	0	0
T225	3950	115	0	0
T226	9768	4	0	0
T227	3610	118	0	0

addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1279	0	0
T72	8908	16	0	0
T226	9768	8	0	0
T234	3803	4	0	0
T235	10923	8	0	0
T247	18052	41	0	0
T278	5211	2	0	0
T279	77400	272	0	0
T280	4714	8	0	0
T281	4555	5	0	0
T282	5976	11	0	0

bank0_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2903	0	0
T72	8908	11	0	0
T226	9768	57	0	0
T234	3803	20	0	0
T235	10923	12	0	0
T247	18052	10	0	0
T278	5211	10	0	0
T280	4714	7	0	0
T281	4555	2	0	0
T282	5976	34	0	0
T283	20583	56	0	0

bank0_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2934	0	0
T72	8908	30	0	0
T226	9768	64	0	0
T234	3803	31	0	0
T235	10923	33	0	0
T247	18052	22	0	0
T278	5211	8	0	0
T279	77400	277	0	0
T280	4714	8	0	0
T281	4555	9	0	0
T282	5976	1	0	0

bank0_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2614	0	0
T72	8908	2	0	0
T226	9768	34	0	0
T234	3803	33	0	0
T235	10923	27	0	0
T247	18052	34	0	0
T278	5211	18	0	0
T280	4714	3	0	0
T281	4555	14	0	0
T282	5976	29	0	0
T283	20583	55	0	0

bank0_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2741	0	0
T72	8908	49	0	0
T226	9768	71	0	0
T234	3803	4	0	0
T235	10923	19	0	0
T247	18052	16	0	0
T278	5211	11	0	0
T279	77400	272	0	0
T280	4714	10	0	0
T281	4555	1	0	0
T282	5976	16	0	0

bank0_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2832	0	0
T72	8908	4	0	0
T226	9768	57	0	0
T234	3803	6	0	0
T235	10923	29	0	0
T247	18052	7	0	0
T278	5211	4	0	0
T279	77400	224	0	0
T280	4714	9	0	0
T281	4555	6	0	0
T282	5976	66	0	0

bank0_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2788	0	0
T226	9768	36	0	0
T234	3803	30	0	0
T235	10923	3	0	0
T247	18052	19	0	0
T278	5211	2	0	0
T279	77400	258	0	0
T280	4714	14	0	0
T281	4555	6	0	0
T282	5976	28	0	0
T283	20583	61	0	0

bank0_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2854	0	0
T72	8908	47	0	0
T226	9768	56	0	0
T234	3803	39	0	0
T235	10923	15	0	0
T247	18052	40	0	0
T278	5211	9	0	0
T279	77400	252	0	0
T280	4714	12	0	0
T281	4555	13	0	0
T282	5976	10	0	0

bank0_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	3143	0	0
T72	8908	10	0	0
T226	9768	44	0	0
T234	3803	34	0	0
T235	10923	20	0	0
T247	18052	37	0	0
T278	5211	2	0	0
T279	77400	240	0	0
T280	4714	13	0	0
T281	4555	11	0	0
T282	5976	30	0	0

bank0_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2654	0	0
T72	8908	14	0	0
T226	9768	57	0	0
T234	3803	7	0	0
T235	10923	38	0	0
T247	18052	16	0	0
T279	77400	231	0	0
T280	4714	13	0	0
T281	4555	8	0	0
T282	5976	9	0	0
T283	20583	80	0	0

bank0_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2862	0	0
T72	8908	18	0	0
T226	9768	24	0	0
T234	3803	5	0	0
T235	10923	21	0	0
T247	18052	41	0	0
T278	5211	1	0	0
T279	77400	216	0	0
T280	4714	9	0	0
T281	4555	5	0	0
T282	5976	17	0	0

bank0_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1330	0	0
T72	8908	16	0	0
T226	9768	20	0	0
T234	3803	5	0	0
T235	10923	29	0	0
T247	18052	28	0	0
T279	77400	288	0	0
T280	4714	11	0	0
T281	4555	12	0	0
T282	5976	5	0	0
T283	20583	17	0	0

bank0_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1253	0	0
T72	8908	5	0	0
T226	9768	5	0	0
T234	3803	5	0	0
T235	10923	27	0	0
T247	18052	16	0	0
T279	77400	256	0	0
T280	4714	4	0	0
T281	4555	13	0	0
T282	5976	3	0	0
T283	20583	59	0	0

bank0_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1162	0	0
T226	9768	18	0	0
T234	3803	2	0	0
T235	10923	3	0	0
T247	18052	15	0	0
T278	5211	2	0	0
T279	77400	237	0	0
T281	4555	12	0	0
T283	20583	18	0	0
T284	273439	228	0	0
T285	9900	4	0	0

bank0_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1136	0	0
T72	8908	17	0	0
T226	9768	8	0	0
T234	3803	2	0	0
T235	10923	35	0	0
T247	18052	1	0	0
T279	77400	226	0	0
T280	4714	8	0	0
T281	4555	13	0	0
T283	20583	20	0	0
T284	273439	245	0	0

bank0_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	939	0	0
T72	8908	1	0	0
T226	9768	17	0	0
T234	3803	1	0	0
T247	18052	20	0	0
T278	5211	3	0	0
T280	4714	5	0	0
T281	4555	6	0	0
T282	5976	3	0	0
T283	20583	41	0	0
T284	273439	256	0	0

bank0_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1352	0	0
T72	8908	22	0	0
T226	9768	13	0	0
T234	3803	5	0	0
T235	10923	25	0	0
T247	18052	21	0	0
T278	5211	7	0	0
T279	77400	263	0	0
T280	4714	11	0	0
T281	4555	5	0	0
T283	20583	41	0	0

bank0_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1206	0	0
T72	8908	12	0	0
T226	9768	13	0	0
T234	3803	4	0	0
T235	10923	17	0	0
T247	18052	11	0	0
T278	5211	10	0	0
T280	4714	7	0	0
T281	4555	1	0	0
T282	5976	4	0	0
T283	20583	56	0	0

bank0_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1200	0	0
T72	8908	17	0	0
T226	9768	15	0	0
T234	3803	1	0	0
T235	10923	27	0	0
T247	18052	15	0	0
T278	5211	2	0	0
T279	77400	274	0	0
T280	4714	12	0	0
T281	4555	5	0	0
T283	20583	3	0	0

bank0_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1264	0	0
T72	8908	20	0	0
T226	9768	26	0	0
T234	3803	9	0	0
T235	10923	21	0	0
T247	18052	9	0	0
T278	5211	1	0	0
T279	77400	258	0	0
T280	4714	11	0	0
T283	20583	11	0	0
T284	273439	297	0	0

bank0_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1291	0	0
T72	8908	21	0	0
T226	9768	19	0	0
T234	3803	2	0	0
T235	10923	10	0	0
T247	18052	29	0	0
T278	5211	10	0	0
T279	77400	266	0	0
T280	4714	6	0	0
T281	4555	9	0	0
T283	20583	51	0	0

bank0_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2580	0	0
T72	8908	3	0	0
T226	9768	67	0	0
T234	3803	9	0	0
T235	10923	1	0	0
T247	18052	30	0	0
T278	5211	8	0	0
T279	77400	258	0	0
T280	4714	11	0	0
T281	4555	6	0	0
T282	5976	1	0	0

bank0_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	903	0	0
T72	8908	7	0	0
T226	9768	21	0	0
T234	3803	3	0	0
T235	10923	2	0	0
T247	18052	28	0	0
T280	4714	1	0	0
T281	4555	6	0	0
T283	20583	37	0	0
T284	273439	256	0	0
T285	9900	1	0	0

bank0_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	3004	0	0
T72	8908	24	0	0
T226	9768	30	0	0
T234	3803	29	0	0
T235	10923	21	0	0
T247	18052	5	0	0
T278	5211	26	0	0
T279	77400	242	0	0
T280	4714	16	0	0
T281	4555	15	0	0
T282	5976	10	0	0

bank0_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2745	0	0
T72	8908	1	0	0
T226	9768	33	0	0
T234	3803	20	0	0
T235	10923	21	0	0
T247	18052	13	0	0
T279	77400	304	0	0
T280	4714	13	0	0
T281	4555	4	0	0
T282	5976	19	0	0
T283	20583	59	0	0

bank0_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1257	0	0
T72	8908	9	0	0
T226	9768	11	0	0
T234	3803	5	0	0
T235	10923	15	0	0
T247	18052	16	0	0
T278	5211	2	0	0
T279	77400	234	0	0
T280	4714	13	0	0
T281	4555	9	0	0
T283	20583	69	0	0

bank0_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1388	0	0
T72	8908	7	0	0
T226	9768	20	0	0
T234	3803	2	0	0
T235	10923	37	0	0
T278	5211	9	0	0
T279	77400	280	0	0
T280	4714	9	0	0
T281	4555	11	0	0
T282	5976	8	0	0
T283	20583	39	0	0

bank1_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2473	0	0
T72	8908	34	0	0
T226	9768	29	0	0
T234	3803	3	0	0
T235	10923	9	0	0
T247	18052	31	0	0
T278	5211	3	0	0
T280	4714	5	0	0
T281	4555	7	0	0
T282	5976	21	0	0
T283	20583	61	0	0

bank1_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2739	0	0
T72	8908	8	0	0
T226	9768	63	0	0
T234	3803	29	0	0
T235	10923	32	0	0
T247	18052	32	0	0
T278	5211	8	0	0
T279	77400	225	0	0
T280	4714	7	0	0
T281	4555	4	0	0
T282	5976	29	0	0

bank1_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2985	0	0
T72	8908	29	0	0
T226	9768	41	0	0
T234	3803	10	0	0
T235	10923	5	0	0
T247	18052	32	0	0
T278	5211	7	0	0
T279	77400	269	0	0
T280	4714	5	0	0
T281	4555	1	0	0
T282	5976	28	0	0

bank1_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	3135	0	0
T72	8908	35	0	0
T226	9768	65	0	0
T234	3803	28	0	0
T235	10923	42	0	0
T247	18052	10	0	0
T278	5211	21	0	0
T279	77400	328	0	0
T280	4714	4	0	0
T281	4555	10	0	0
T282	5976	38	0	0

bank1_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2827	0	0
T72	8908	9	0	0
T226	9768	37	0	0
T234	3803	5	0	0
T235	10923	33	0	0
T247	18052	19	0	0
T279	77400	270	0	0
T280	4714	3	0	0
T281	4555	6	0	0
T282	5976	6	0	0
T283	20583	63	0	0

bank1_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	3104	0	0
T72	8908	45	0	0
T226	9768	52	0	0
T234	3803	18	0	0
T235	10923	1	0	0
T247	18052	20	0	0
T278	5211	12	0	0
T279	77400	270	0	0
T280	4714	2	0	0
T281	4555	8	0	0
T282	5976	9	0	0

bank1_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2832	0	0
T72	8908	35	0	0
T226	9768	39	0	0
T234	3803	4	0	0
T235	10923	13	0	0
T247	18052	23	0	0
T278	5211	5	0	0
T279	77400	246	0	0
T280	4714	7	0	0
T281	4555	5	0	0
T282	5976	28	0	0

bank1_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2495	0	0
T72	8908	21	0	0
T226	9768	8	0	0
T234	3803	1	0	0
T235	10923	2	0	0
T247	18052	58	0	0
T278	5211	13	0	0
T280	4714	7	0	0
T281	4555	18	0	0
T282	5976	18	0	0
T283	20583	34	0	0

bank1_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	3165	0	0
T72	8908	25	0	0
T226	9768	78	0	0
T234	3803	8	0	0
T247	18052	26	0	0
T278	5211	10	0	0
T279	77400	298	0	0
T280	4714	3	0	0
T281	4555	5	0	0
T282	5976	45	0	0
T283	20583	47	0	0

bank1_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2486	0	0
T72	8908	13	0	0
T226	9768	50	0	0
T234	3803	30	0	0
T235	10923	21	0	0
T247	18052	33	0	0
T278	5211	4	0	0
T280	4714	12	0	0
T281	4555	7	0	0
T282	5976	14	0	0
T283	20583	55	0	0

bank1_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1295	0	0
T72	8908	4	0	0
T226	9768	16	0	0
T234	3803	2	0	0
T235	10923	23	0	0
T247	18052	31	0	0
T278	5211	6	0	0
T279	77400	188	0	0
T280	4714	5	0	0
T281	4555	3	0	0
T283	20583	42	0	0

bank1_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1325	0	0
T72	8908	14	0	0
T226	9768	14	0	0
T234	3803	3	0	0
T235	10923	6	0	0
T247	18052	18	0	0
T278	5211	12	0	0
T279	77400	259	0	0
T280	4714	5	0	0
T281	4555	13	0	0
T282	5976	5	0	0

bank1_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1391	0	0
T72	8908	5	0	0
T226	9768	15	0	0
T234	3803	6	0	0
T235	10923	18	0	0
T247	18052	25	0	0
T278	5211	6	0	0
T279	77400	268	0	0
T280	4714	11	0	0
T281	4555	2	0	0
T282	5976	2	0	0

bank1_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1290	0	0
T72	8908	12	0	0
T226	9768	19	0	0
T234	3803	8	0	0
T235	10923	30	0	0
T247	18052	8	0	0
T278	5211	2	0	0
T279	77400	234	0	0
T280	4714	5	0	0
T281	4555	8	0	0
T282	5976	3	0	0

bank1_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1133	0	0
T226	9768	15	0	0
T234	3803	8	0	0
T235	10923	25	0	0
T247	18052	24	0	0
T278	5211	12	0	0
T280	4714	10	0	0
T281	4555	8	0	0
T282	5976	9	0	0
T283	20583	40	0	0
T284	273439	325	0	0

bank1_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1297	0	0
T72	8908	8	0	0
T226	9768	11	0	0
T235	10923	16	0	0
T247	18052	18	0	0
T278	5211	6	0	0
T279	77400	247	0	0
T280	4714	8	0	0
T281	4555	14	0	0
T283	20583	48	0	0
T284	273439	248	0	0

bank1_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1355	0	0
T72	8908	10	0	0
T226	9768	16	0	0
T234	3803	10	0	0
T235	10923	41	0	0
T247	18052	16	0	0
T278	5211	8	0	0
T279	77400	262	0	0
T280	4714	10	0	0
T281	4555	16	0	0
T282	5976	3	0	0

bank1_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1363	0	0
T72	8908	10	0	0
T226	9768	20	0	0
T234	3803	5	0	0
T235	10923	15	0	0
T247	18052	16	0	0
T278	5211	10	0	0
T279	77400	332	0	0
T280	4714	7	0	0
T281	4555	16	0	0
T283	20583	45	0	0

bank1_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1323	0	0
T226	9768	17	0	0
T234	3803	6	0	0
T235	10923	21	0	0
T247	18052	23	0	0
T278	5211	9	0	0
T279	77400	272	0	0
T280	4714	6	0	0
T281	4555	9	0	0
T282	5976	10	0	0
T283	20583	39	0	0

bank1_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1306	0	0
T72	8908	6	0	0
T226	9768	22	0	0
T234	3803	8	0	0
T235	10923	10	0	0
T247	18052	38	0	0
T278	5211	8	0	0
T279	77400	245	0	0
T280	4714	12	0	0
T281	4555	10	0	0
T282	5976	11	0	0

bank1_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2830	0	0
T72	8908	9	0	0
T226	9768	67	0	0
T234	3803	5	0	0
T235	10923	30	0	0
T247	18052	28	0	0
T279	77400	252	0	0
T280	4714	9	0	0
T281	4555	4	0	0
T282	5976	23	0	0
T283	20583	49	0	0

bank1_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1258	0	0
T72	8908	15	0	0
T226	9768	13	0	0
T234	3803	3	0	0
T235	10923	8	0	0
T278	5211	2	0	0
T279	77400	193	0	0
T280	4714	10	0	0
T281	4555	3	0	0
T282	5976	7	0	0
T283	20583	48	0	0

bank1_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2950	0	0
T72	8908	6	0	0
T226	9768	18	0	0
T234	3803	8	0	0
T235	10923	16	0	0
T247	18052	33	0	0
T278	5211	23	0	0
T279	77400	212	0	0
T280	4714	8	0	0
T281	4555	16	0	0
T282	5976	20	0	0

bank1_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2685	0	0
T72	8908	33	0	0
T226	9768	12	0	0
T234	3803	19	0	0
T235	10923	45	0	0
T247	18052	7	0	0
T278	5211	4	0	0
T279	77400	232	0	0
T280	4714	8	0	0
T281	4555	4	0	0
T282	5976	29	0	0

bank1_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1135	0	0
T72	8908	9	0	0
T226	9768	30	0	0
T234	3803	5	0	0
T235	10923	15	0	0
T247	18052	38	0	0
T278	5211	3	0	0
T280	4714	9	0	0
T281	4555	14	0	0
T282	5976	2	0	0
T283	20583	10	0	0

bank1_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1270	0	0
T72	8908	10	0	0
T226	9768	16	0	0
T235	10923	6	0	0
T247	18052	27	0	0
T279	77400	295	0	0
T280	4714	9	0	0
T281	4555	11	0	0
T282	5976	3	0	0
T283	20583	44	0	0
T284	273439	250	0	0

bank_cfg_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1167	0	0
T72	8908	19	0	0
T226	9768	19	0	0
T234	3803	3	0	0
T235	10923	14	0	0
T247	18052	22	0	0
T278	5211	3	0	0
T280	4714	13	0	0
T281	4555	9	0	0
T283	20583	53	0	0
T284	273439	283	0	0

default_region_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2436	0	0
T72	8908	13	0	0
T226	9768	49	0	0
T234	3803	35	0	0
T235	10923	13	0	0
T278	5211	5	0	0
T279	77400	275	0	0
T280	4714	7	0	0
T281	4555	17	0	0
T282	5976	16	0	0
T283	20583	34	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1133	0	0
T72	8908	8	0	0
T226	9768	10	0	0
T234	3803	4	0	0
T235	10923	35	0	0
T247	18052	47	0	0
T278	5211	6	0	0
T279	77400	210	0	0
T280	4714	6	0	0
T281	4555	11	0	0
T282	5976	5	0	0

fifo_lvl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1501	0	0
T72	8908	20	0	0
T226	9768	27	0	0
T234	3803	12	0	0
T235	10923	24	0	0
T247	18052	37	0	0
T278	5211	9	0	0
T279	77400	220	0	0
T280	4714	9	0	0
T281	4555	5	0	0
T283	20583	32	0	0

fifo_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1266	0	0
T72	8908	8	0	0
T226	9768	17	0	0
T234	3803	3	0	0
T235	10923	53	0	0
T247	18052	12	0	0
T279	77400	210	0	0
T280	4714	8	0	0
T281	4555	4	0	0
T283	20583	24	0	0
T284	273439	277	0	0

hw_info_cfg_override_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1533	0	0
T72	8908	10	0	0
T226	9768	24	0	0
T234	3803	7	0	0
T235	10923	24	0	0
T247	18052	36	0	0
T278	5211	2	0	0
T279	77400	280	0	0
T280	4714	9	0	0
T281	4555	10	0	0
T283	20583	71	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2409	0	0
T72	8908	15	0	0
T226	9768	71	0	0
T234	3803	2	0	0
T235	10923	16	0	0
T247	18052	24	0	0
T280	4714	6	0	0
T281	4555	11	0	0
T282	5976	27	0	0
T283	20583	78	0	0
T284	273439	267	0	0

mp_region_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1301	0	0
T72	8908	11	0	0
T226	9768	15	0	0
T234	3803	9	0	0
T235	10923	21	0	0
T247	18052	30	0	0
T280	4714	8	0	0
T281	4555	7	0	0
T282	5976	4	0	0
T283	20583	51	0	0
T284	273439	223	0	0

mp_region_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1539	0	0
T72	8908	22	0	0
T226	9768	24	0	0
T234	3803	12	0	0
T235	10923	10	0	0
T247	18052	16	0	0
T278	5211	14	0	0
T279	77400	226	0	0
T280	4714	6	0	0
T281	4555	16	0	0
T282	5976	7	0	0

mp_region_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1567	0	0
T72	8908	20	0	0
T226	9768	16	0	0
T234	3803	9	0	0
T235	10923	17	0	0
T247	18052	25	0	0
T279	77400	260	0	0
T280	4714	8	0	0
T281	4555	7	0	0
T282	5976	7	0	0
T283	20583	64	0	0

mp_region_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1485	0	0
T72	8908	4	0	0
T226	9768	9	0	0
T234	3803	2	0	0
T235	10923	29	0	0
T247	18052	16	0	0
T279	77400	247	0	0
T280	4714	11	0	0
T281	4555	4	0	0
T282	5976	5	0	0
T283	20583	49	0	0

mp_region_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1339	0	0
T72	8908	6	0	0
T226	9768	33	0	0
T234	3803	12	0	0
T235	10923	26	0	0
T247	18052	10	0	0
T278	5211	11	0	0
T279	77400	200	0	0
T280	4714	7	0	0
T281	4555	16	0	0
T283	20583	35	0	0

mp_region_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1512	0	0
T72	8908	18	0	0
T226	9768	35	0	0
T234	3803	4	0	0
T235	10923	9	0	0
T247	18052	35	0	0
T278	5211	13	0	0
T279	77400	267	0	0
T280	4714	14	0	0
T281	4555	8	0	0
T282	5976	14	0	0

mp_region_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1444	0	0
T72	8908	13	0	0
T226	9768	32	0	0
T234	3803	18	0	0
T235	10923	14	0	0
T247	18052	32	0	0
T278	5211	11	0	0
T279	77400	253	0	0
T280	4714	6	0	0
T281	4555	10	0	0
T282	5976	8	0	0

mp_region_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1628	0	0
T72	8908	20	0	0
T226	9768	16	0	0
T234	3803	8	0	0
T235	10923	41	0	0
T247	18052	25	0	0
T278	5211	10	0	0
T279	77400	224	0	0
T280	4714	7	0	0
T281	4555	9	0	0
T282	5976	1	0	0

mp_region_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2765	0	0
T72	8908	33	0	0
T226	9768	23	0	0
T234	3803	29	0	0
T235	10923	2	0	0
T247	18052	36	0	0
T279	77400	245	0	0
T280	4714	11	0	0
T281	4555	12	0	0
T282	5976	9	0	0
T283	20583	29	0	0

mp_region_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2748	0	0
T72	8908	22	0	0
T226	9768	26	0	0
T234	3803	37	0	0
T235	10923	29	0	0
T247	18052	2	0	0
T278	5211	1	0	0
T279	77400	241	0	0
T280	4714	7	0	0
T281	4555	12	0	0
T282	5976	26	0	0

mp_region_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2608	0	0
T72	8908	21	0	0
T226	9768	16	0	0
T234	3803	22	0	0
T235	10923	52	0	0
T247	18052	12	0	0
T278	5211	25	0	0
T280	4714	8	0	0
T281	4555	6	0	0
T282	5976	29	0	0
T283	20583	56	0	0

mp_region_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2629	0	0
T72	8908	16	0	0
T226	9768	35	0	0
T234	3803	5	0	0
T235	10923	23	0	0
T247	18052	24	0	0
T278	5211	33	0	0
T280	4714	17	0	0
T281	4555	10	0	0
T282	5976	8	0	0
T283	20583	42	0	0

mp_region_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	3000	0	0
T72	8908	57	0	0
T226	9768	42	0	0
T234	3803	29	0	0
T235	10923	35	0	0
T247	18052	1	0	0
T278	5211	2	0	0
T279	77400	304	0	0
T280	4714	13	0	0
T281	4555	4	0	0
T282	5976	18	0	0

mp_region_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2805	0	0
T72	8908	32	0	0
T226	9768	64	0	0
T234	3803	25	0	0
T235	10923	19	0	0
T247	18052	38	0	0
T278	5211	4	0	0
T279	77400	241	0	0
T280	4714	3	0	0
T281	4555	3	0	0
T283	20583	38	0	0

mp_region_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2667	0	0
T72	8908	30	0	0
T226	9768	47	0	0
T234	3803	3	0	0
T235	10923	6	0	0
T247	18052	9	0	0
T278	5211	1	0	0
T279	77400	231	0	0
T280	4714	9	0	0
T281	4555	2	0	0
T282	5976	29	0	0

mp_region_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	2821	0	0
T72	8908	9	0	0
T226	9768	17	0	0
T234	3803	25	0	0
T235	10923	8	0	0
T247	18052	26	0	0
T278	5211	8	0	0
T279	77400	264	0	0
T280	4714	8	0	0
T281	4555	9	0	0
T282	5976	22	0	0

phy_alert_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	464	0	0
T226	9768	8	0	0
T235	10923	17	0	0
T247	18052	12	0	0
T278	5211	5	0	0
T279	77400	239	0	0
T280	4714	6	0	0
T281	4555	12	0	0
T283	20583	9	0	0
T285	9900	10	0	0
T286	18451	32	0	0

region_cfg_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1250	0	0
T72	8908	8	0	0
T226	9768	1	0	0
T234	3803	8	0	0
T235	10923	9	0	0
T247	18052	17	0	0
T278	5211	4	0	0
T279	77400	246	0	0
T280	4714	5	0	0
T281	4555	4	0	0
T282	5976	1	0	0

region_cfg_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1336	0	0
T72	8908	22	0	0
T226	9768	23	0	0
T234	3803	5	0	0
T235	10923	37	0	0
T247	18052	76	0	0
T279	77400	265	0	0
T280	4714	12	0	0
T281	4555	5	0	0
T282	5976	3	0	0
T283	20583	14	0	0

region_cfg_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1307	0	0
T72	8908	9	0	0
T226	9768	14	0	0
T234	3803	1	0	0
T235	10923	21	0	0
T247	18052	31	0	0
T278	5211	1	0	0
T279	77400	235	0	0
T280	4714	7	0	0
T281	4555	6	0	0
T282	5976	4	0	0

region_cfg_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1042	0	0
T72	8908	14	0	0
T226	9768	16	0	0
T235	10923	26	0	0
T247	18052	46	0	0
T278	5211	1	0	0
T280	4714	5	0	0
T281	4555	10	0	0
T282	5976	9	0	0
T283	20583	61	0	0
T284	273439	253	0	0

region_cfg_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1353	0	0
T72	8908	2	0	0
T226	9768	11	0	0
T235	10923	23	0	0
T247	18052	24	0	0
T278	5211	8	0	0
T279	77400	256	0	0
T280	4714	13	0	0
T281	4555	10	0	0
T282	5976	3	0	0
T283	20583	83	0	0

region_cfg_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1240	0	0
T72	8908	9	0	0
T226	9768	27	0	0
T235	10923	38	0	0
T247	18052	16	0	0
T278	5211	4	0	0
T279	77400	274	0	0
T280	4714	7	0	0
T281	4555	8	0	0
T282	5976	3	0	0
T283	20583	36	0	0

region_cfg_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	903	0	0
T226	9768	6	0	0
T234	3803	6	0	0
T235	10923	29	0	0
T247	18052	29	0	0
T278	5211	1	0	0
T280	4714	4	0	0
T281	4555	18	0	0
T283	20583	12	0	0
T284	273439	234	0	0
T285	9900	7	0	0

region_cfg_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	1283	0	0
T72	8908	7	0	0
T226	9768	16	0	0
T234	3803	3	0	0
T235	10923	22	0	0
T247	18052	26	0	0
T279	77400	327	0	0
T280	4714	7	0	0
T281	4555	4	0	0
T283	20583	30	0	0
T284	273439	220	0	0

scratch_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396824248	987	0	0
T72	8908	8	0	0
T226	9768	12	0	0
T234	3803	2	0	0
T235	10923	23	0	0
T247	18052	15	0	0
T280	4714	7	0	0
T281	4555	7	0	0
T282	5976	9	0	0
T283	20583	37	0	0
T284	273439	286	0	0