Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	27039747	1		T1	57		T2	86		T3	1267
full_word	7587349	1		T1	4		T2	57		T3	3461

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34626796	1		T1	61		T2	143		T3	4728
auto[TlIntgErrCmd]	111	1		T239	2		T240	3		T241	4
auto[TlIntgErrData]	102	1		T239	4		T240	5		T241	2
auto[TlIntgErrBoth]	87	1		T239	4		T240	2		T241	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30245435	1		T1	57		T2	102		T3	1786
auto[1]	4381661	1		T1	4		T2	41		T3	2942

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	26372262	1		T1	57		T2	80		T3	1011
auto[TlIntgErrNone]	partial	auto[1]	667207	1		T2	6		T3	256		T10	1270
auto[TlIntgErrNone]	full_word	auto[0]	3873018	1		T2	22		T3	775		T10	4404
auto[TlIntgErrNone]	full_word	auto[1]	3714309	1		T1	4		T2	35		T3	2686
auto[TlIntgErrCmd]	partial	auto[0]	45	1		T239	1		T240	1		T241	2
auto[TlIntgErrCmd]	partial	auto[1]	58	1		T239	1		T240	2		T241	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T354	1		T358	1		T361	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T362	1		T364	1		T365	1
auto[TlIntgErrData]	partial	auto[0]	57	1		T239	1		T240	3		T241	1
auto[TlIntgErrData]	partial	auto[1]	33	1		T239	3		T240	2		T241	1
auto[TlIntgErrData]	full_word	auto[0]	7	1		T361	1		T366	1		T367	2
auto[TlIntgErrData]	full_word	auto[1]	5	1		T364	1		T356	1		T361	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1		T239	1		T240	1		T241	1
auto[TlIntgErrBoth]	partial	auto[1]	45	1		T239	3		T240	1		T241	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T359	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1		T356	1		-	-		-	-

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	17609	1		T124	432		T72	162		T127	1425
full_word	3674672	1		T1	10		T3	496		T11	212

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3692000	1		T1	10		T3	496		T11	212
auto[TlIntgErrCmd]	93	1		T239	4		T240	5		T241	3
auto[TlIntgErrData]	99	1		T239	4		T240	2		T241	5
auto[TlIntgErrBoth]	89	1		T239	1		T240	3		T241	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3670216	1		T1	10		T3	496		T11	212
auto[1]	22065	1		T124	537		T72	175		T127	1555

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1142	1		T124	35		T72	10		T127	54
auto[TlIntgErrNone]	partial	auto[1]	16206	1		T124	397		T72	152		T127	1371
auto[TlIntgErrNone]	full_word	auto[0]	3668962	1		T1	10		T3	496		T11	212
auto[TlIntgErrNone]	full_word	auto[1]	5690	1		T124	140		T72	23		T127	184
auto[TlIntgErrCmd]	partial	auto[0]	33	1		T239	2		T240	4		T241	1
auto[TlIntgErrCmd]	partial	auto[1]	54	1		T239	2		T240	1		T241	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T359	1		T368	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T362	1		T365	1		T367	2
auto[TlIntgErrData]	partial	auto[0]	45	1		T239	3		T240	1		T241	4
auto[TlIntgErrData]	partial	auto[1]	44	1		T239	1		T240	1		T241	1
auto[TlIntgErrData]	full_word	auto[0]	5	1		T354	1		T369	2		T363	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T360	1		T365	2		T367	1
auto[TlIntgErrBoth]	partial	auto[0]	26	1		T239	1		T241	1		T362	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1		T240	2		T354	1		T358	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T366	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T240	1		T360	1		T368	1