Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T10 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T11

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T11

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T11
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T12
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T11

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T11

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1577003436	1573516292	0	0
CheckNGreaterZero_A	4172	4172	0	0
GntImpliesReady_A	1577003436	400205723	0	0
GntImpliesValid_A	1577003436	400205723	0	0
GrantKnown_A	1577003436	1573516292	0	0
IdxKnown_A	1577003436	1573516292	0	0
IndexIsCorrect_A	1577003436	400205723	0	0
NoReadyValidNoGrant_A	1577003436	171220808	0	0
Priority_A	1577003436	424070393	0	0
ReadyAndValidImplyGrant_A	1577003436	400205723	0	0
ReqAndReadyImplyGrant_A	1577003436	400205723	0	0
ReqImpliesValid_A	1577003436	424070393	0	0
ValidKnown_A	1577003436	1573516292	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577003436	1573516292	0	0
T1	4776	4420	0	0
T2	10032	9808	0	0
T3	58312	58032	0	0
T4	13972	11052	0	0
T10	1334892	1285836	0	0
T11	25580	25360	0	0
T16	289872	289524	0	0
T17	6048	5816	0	0
T18	348036	347792	0	0
T19	258584	257924	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4172	4172	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T10	4	4	0	0
T11	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577003436	400205723	0	0
T1	2388	84	0	0
T2	5016	1158	0	0
T3	58312	2464	0	0
T4	13972	280	0	0
T10	1334892	216714	0	0
T11	25580	7170	0	0
T12	0	23000	0	0
T16	289872	135402	0	0
T17	6048	384	0	0
T18	348036	105852	0	0
T19	258584	43260	0	0
T26	0	3576	0	0
T28	0	4886	0	0
T45	0	12654	0	0
T58	4416	0	0	0
T59	7702	0	0	0
T67	0	123984	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577003436	400205723	0	0
T1	2388	84	0	0
T2	5016	1158	0	0
T3	58312	2464	0	0
T4	13972	280	0	0
T10	1334892	216714	0	0
T11	25580	7170	0	0
T12	0	23000	0	0
T16	289872	135402	0	0
T17	6048	384	0	0
T18	348036	105852	0	0
T19	258584	43260	0	0
T26	0	3576	0	0
T28	0	4886	0	0
T45	0	12654	0	0
T58	4416	0	0	0
T59	7702	0	0	0
T67	0	123984	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577003436	1573516292	0	0
T1	4776	4420	0	0
T2	10032	9808	0	0
T3	58312	58032	0	0
T4	13972	11052	0	0
T10	1334892	1285836	0	0
T11	25580	25360	0	0
T16	289872	289524	0	0
T17	6048	5816	0	0
T18	348036	347792	0	0
T19	258584	257924	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577003436	1573516292	0	0
T1	4776	4420	0	0
T2	10032	9808	0	0
T3	58312	58032	0	0
T4	13972	11052	0	0
T10	1334892	1285836	0	0
T11	25580	25360	0	0
T16	289872	289524	0	0
T17	6048	5816	0	0
T18	348036	347792	0	0
T19	258584	257924	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577003436	400205723	0	0
T1	2388	84	0	0
T2	5016	1158	0	0
T3	58312	2464	0	0
T4	13972	280	0	0
T10	1334892	216714	0	0
T11	25580	7170	0	0
T12	0	23000	0	0
T16	289872	135402	0	0
T17	6048	384	0	0
T18	348036	105852	0	0
T19	258584	43260	0	0
T26	0	3576	0	0
T28	0	4886	0	0
T45	0	12654	0	0
T58	4416	0	0	0
T59	7702	0	0	0
T67	0	123984	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577003436	171220808	0	0
T1	2388	286	0	0
T2	5016	316	0	0
T3	58312	3842	0	0
T4	13972	1120	0	0
T10	1334892	61016	0	0
T11	25580	834	0	0
T12	0	27124	0	0
T16	289872	852	0	0
T17	6048	398	0	0
T18	348036	7468	0	0
T19	258584	424	0	0
T26	0	456	0	0
T28	0	214	0	0
T45	0	1624	0	0
T58	4416	0	0	0
T59	7702	0	0	0
T64	0	736	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577003436	424070393	0	0
T1	2388	84	0	0
T2	5016	1158	0	0
T3	58312	2466	0	0
T4	13972	280	0	0
T10	1334892	216714	0	0
T11	25580	7186	0	0
T12	0	39008	0	0
T16	289872	135402	0	0
T17	6048	384	0	0
T18	348036	105852	0	0
T19	258584	43260	0	0
T26	0	3576	0	0
T28	0	4886	0	0
T45	0	12698	0	0
T58	4416	0	0	0
T59	7702	0	0	0
T67	0	123984	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577003436	400205723	0	0
T1	2388	84	0	0
T2	5016	1158	0	0
T3	58312	2464	0	0
T4	13972	280	0	0
T10	1334892	216714	0	0
T11	25580	7170	0	0
T12	0	23000	0	0
T16	289872	135402	0	0
T17	6048	384	0	0
T18	348036	105852	0	0
T19	258584	43260	0	0
T26	0	3576	0	0
T28	0	4886	0	0
T45	0	12654	0	0
T58	4416	0	0	0
T59	7702	0	0	0
T67	0	123984	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577003436	400205723	0	0
T1	2388	84	0	0
T2	5016	1158	0	0
T3	58312	2464	0	0
T4	13972	280	0	0
T10	1334892	216714	0	0
T11	25580	7170	0	0
T12	0	23000	0	0
T16	289872	135402	0	0
T17	6048	384	0	0
T18	348036	105852	0	0
T19	258584	43260	0	0
T26	0	3576	0	0
T28	0	4886	0	0
T45	0	12654	0	0
T58	4416	0	0	0
T59	7702	0	0	0
T67	0	123984	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577003436	424070393	0	0
T1	2388	84	0	0
T2	5016	1158	0	0
T3	58312	2466	0	0
T4	13972	280	0	0
T10	1334892	216714	0	0
T11	25580	7186	0	0
T12	0	39008	0	0
T16	289872	135402	0	0
T17	6048	384	0	0
T18	348036	105852	0	0
T19	258584	43260	0	0
T26	0	3576	0	0
T28	0	4886	0	0
T45	0	12698	0	0
T58	4416	0	0	0
T59	7702	0	0	0
T67	0	123984	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577003436	1573516292	0	0
T1	4776	4420	0	0
T2	10032	9808	0	0
T3	58312	58032	0	0
T4	13972	11052	0	0
T10	1334892	1285836	0	0
T11	25580	25360	0	0
T16	289872	289524	0	0
T17	6048	5816	0	0
T18	348036	347792	0	0
T19	258584	257924	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T10 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T11

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T45
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T11

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T11
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T12,T45
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T11

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T11

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394250859	393379073	0	0
CheckNGreaterZero_A	1043	1043	0	0
GntImpliesReady_A	394250859	106585916	0	0
GntImpliesValid_A	394250859	106585916	0	0
GrantKnown_A	394250859	393379073	0	0
IdxKnown_A	394250859	393379073	0	0
IndexIsCorrect_A	394250859	106585916	0	0
NoReadyValidNoGrant_A	394250859	44676055	0	0
Priority_A	394250859	112530378	0	0
ReadyAndValidImplyGrant_A	394250859	106585916	0	0
ReqAndReadyImplyGrant_A	394250859	106585916	0	0
ReqImpliesValid_A	394250859	112530378	0	0
ValidKnown_A	394250859	393379073	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	393379073	0	0
T1	1194	1105	0	0
T2	2508	2452	0	0
T3	14578	14508	0	0
T4	3493	2763	0	0
T10	333723	321459	0	0
T11	6395	6340	0	0
T16	72468	72381	0	0
T17	1512	1454	0	0
T18	87009	86948	0	0
T19	64646	64481	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	106585916	0	0
T1	1194	42	0	0
T2	2508	579	0	0
T3	14578	623	0	0
T4	3493	140	0	0
T10	333723	108357	0	0
T11	6395	2438	0	0
T16	72468	67701	0	0
T17	1512	162	0	0
T18	87009	28368	0	0
T19	64646	10455	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	106585916	0	0
T1	1194	42	0	0
T2	2508	579	0	0
T3	14578	623	0	0
T4	3493	140	0	0
T10	333723	108357	0	0
T11	6395	2438	0	0
T16	72468	67701	0	0
T17	1512	162	0	0
T18	87009	28368	0	0
T19	64646	10455	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	393379073	0	0
T1	1194	1105	0	0
T2	2508	2452	0	0
T3	14578	14508	0	0
T4	3493	2763	0	0
T10	333723	321459	0	0
T11	6395	6340	0	0
T16	72468	72381	0	0
T17	1512	1454	0	0
T18	87009	86948	0	0
T19	64646	64481	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	393379073	0	0
T1	1194	1105	0	0
T2	2508	2452	0	0
T3	14578	14508	0	0
T4	3493	2763	0	0
T10	333723	321459	0	0
T11	6395	6340	0	0
T16	72468	72381	0	0
T17	1512	1454	0	0
T18	87009	86948	0	0
T19	64646	64481	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	106585916	0	0
T1	1194	42	0	0
T2	2508	579	0	0
T3	14578	623	0	0
T4	3493	140	0	0
T10	333723	108357	0	0
T11	6395	2438	0	0
T16	72468	67701	0	0
T17	1512	162	0	0
T18	87009	28368	0	0
T19	64646	10455	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	44676055	0	0
T1	1194	143	0	0
T2	2508	158	0	0
T3	14578	1012	0	0
T4	3493	560	0	0
T10	333723	30508	0	0
T11	6395	323	0	0
T16	72468	426	0	0
T17	1512	153	0	0
T18	87009	1994	0	0
T19	64646	164	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	112530378	0	0
T1	1194	42	0	0
T2	2508	579	0	0
T3	14578	623	0	0
T4	3493	140	0	0
T10	333723	108357	0	0
T11	6395	2444	0	0
T16	72468	67701	0	0
T17	1512	162	0	0
T18	87009	28368	0	0
T19	64646	10455	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	106585916	0	0
T1	1194	42	0	0
T2	2508	579	0	0
T3	14578	623	0	0
T4	3493	140	0	0
T10	333723	108357	0	0
T11	6395	2438	0	0
T16	72468	67701	0	0
T17	1512	162	0	0
T18	87009	28368	0	0
T19	64646	10455	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	106585916	0	0
T1	1194	42	0	0
T2	2508	579	0	0
T3	14578	623	0	0
T4	3493	140	0	0
T10	333723	108357	0	0
T11	6395	2438	0	0
T16	72468	67701	0	0
T17	1512	162	0	0
T18	87009	28368	0	0
T19	64646	10455	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	112530378	0	0
T1	1194	42	0	0
T2	2508	579	0	0
T3	14578	623	0	0
T4	3493	140	0	0
T10	333723	108357	0	0
T11	6395	2444	0	0
T16	72468	67701	0	0
T17	1512	162	0	0
T18	87009	28368	0	0
T19	64646	10455	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	393379073	0	0
T1	1194	1105	0	0
T2	2508	2452	0	0
T3	14578	14508	0	0
T4	3493	2763	0	0
T10	333723	321459	0	0
T11	6395	6340	0	0
T16	72468	72381	0	0
T17	1512	1454	0	0
T18	87009	86948	0	0
T19	64646	64481	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T10 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T11

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T45
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T11

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T11
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T12,T45
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T11

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T11

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394250859	393379073	0	0
CheckNGreaterZero_A	1043	1043	0	0
GntImpliesReady_A	394250859	106585916	0	0
GntImpliesValid_A	394250859	106585916	0	0
GrantKnown_A	394250859	393379073	0	0
IdxKnown_A	394250859	393379073	0	0
IndexIsCorrect_A	394250859	106585916	0	0
NoReadyValidNoGrant_A	394250859	44676055	0	0
Priority_A	394250859	112530378	0	0
ReadyAndValidImplyGrant_A	394250859	106585916	0	0
ReqAndReadyImplyGrant_A	394250859	106585916	0	0
ReqImpliesValid_A	394250859	112530378	0	0
ValidKnown_A	394250859	393379073	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	393379073	0	0
T1	1194	1105	0	0
T2	2508	2452	0	0
T3	14578	14508	0	0
T4	3493	2763	0	0
T10	333723	321459	0	0
T11	6395	6340	0	0
T16	72468	72381	0	0
T17	1512	1454	0	0
T18	87009	86948	0	0
T19	64646	64481	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	106585916	0	0
T1	1194	42	0	0
T2	2508	579	0	0
T3	14578	623	0	0
T4	3493	140	0	0
T10	333723	108357	0	0
T11	6395	2438	0	0
T16	72468	67701	0	0
T17	1512	162	0	0
T18	87009	28368	0	0
T19	64646	10455	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	106585916	0	0
T1	1194	42	0	0
T2	2508	579	0	0
T3	14578	623	0	0
T4	3493	140	0	0
T10	333723	108357	0	0
T11	6395	2438	0	0
T16	72468	67701	0	0
T17	1512	162	0	0
T18	87009	28368	0	0
T19	64646	10455	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	393379073	0	0
T1	1194	1105	0	0
T2	2508	2452	0	0
T3	14578	14508	0	0
T4	3493	2763	0	0
T10	333723	321459	0	0
T11	6395	6340	0	0
T16	72468	72381	0	0
T17	1512	1454	0	0
T18	87009	86948	0	0
T19	64646	64481	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	393379073	0	0
T1	1194	1105	0	0
T2	2508	2452	0	0
T3	14578	14508	0	0
T4	3493	2763	0	0
T10	333723	321459	0	0
T11	6395	6340	0	0
T16	72468	72381	0	0
T17	1512	1454	0	0
T18	87009	86948	0	0
T19	64646	64481	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	106585916	0	0
T1	1194	42	0	0
T2	2508	579	0	0
T3	14578	623	0	0
T4	3493	140	0	0
T10	333723	108357	0	0
T11	6395	2438	0	0
T16	72468	67701	0	0
T17	1512	162	0	0
T18	87009	28368	0	0
T19	64646	10455	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	44676055	0	0
T1	1194	143	0	0
T2	2508	158	0	0
T3	14578	1012	0	0
T4	3493	560	0	0
T10	333723	30508	0	0
T11	6395	323	0	0
T16	72468	426	0	0
T17	1512	153	0	0
T18	87009	1994	0	0
T19	64646	164	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	112530378	0	0
T1	1194	42	0	0
T2	2508	579	0	0
T3	14578	623	0	0
T4	3493	140	0	0
T10	333723	108357	0	0
T11	6395	2444	0	0
T16	72468	67701	0	0
T17	1512	162	0	0
T18	87009	28368	0	0
T19	64646	10455	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	106585916	0	0
T1	1194	42	0	0
T2	2508	579	0	0
T3	14578	623	0	0
T4	3493	140	0	0
T10	333723	108357	0	0
T11	6395	2438	0	0
T16	72468	67701	0	0
T17	1512	162	0	0
T18	87009	28368	0	0
T19	64646	10455	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	106585916	0	0
T1	1194	42	0	0
T2	2508	579	0	0
T3	14578	623	0	0
T4	3493	140	0	0
T10	333723	108357	0	0
T11	6395	2438	0	0
T16	72468	67701	0	0
T17	1512	162	0	0
T18	87009	28368	0	0
T19	64646	10455	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	112530378	0	0
T1	1194	42	0	0
T2	2508	579	0	0
T3	14578	623	0	0
T4	3493	140	0	0
T10	333723	108357	0	0
T11	6395	2444	0	0
T16	72468	67701	0	0
T17	1512	162	0	0
T18	87009	28368	0	0
T19	64646	10455	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	393379073	0	0
T1	1194	1105	0	0
T2	2508	2452	0	0
T3	14578	14508	0	0
T4	3493	2763	0	0
T10	333723	321459	0	0
T11	6395	6340	0	0
T16	72468	72381	0	0
T17	1512	1454	0	0
T18	87009	86948	0	0
T19	64646	64481	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T10 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T11,T17
1	0	Covered	T3,T11,T12

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Covered	T3,T11,T17
1	1	Covered	T3,T11,T12

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T11,T17

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T11,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T11,T12

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T11,T12

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394250859	393379073	0	0
CheckNGreaterZero_A	1043	1043	0	0
GntImpliesReady_A	394250859	93516941	0	0
GntImpliesValid_A	394250859	93516941	0	0
GrantKnown_A	394250859	393379073	0	0
IdxKnown_A	394250859	393379073	0	0
IndexIsCorrect_A	394250859	93516941	0	0
NoReadyValidNoGrant_A	394250859	40934377	0	0
Priority_A	394250859	99504786	0	0
ReadyAndValidImplyGrant_A	394250859	93516941	0	0
ReqAndReadyImplyGrant_A	394250859	93516941	0	0
ReqImpliesValid_A	394250859	99504786	0	0
ValidKnown_A	394250859	393379073	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	393379073	0	0
T1	1194	1105	0	0
T2	2508	2452	0	0
T3	14578	14508	0	0
T4	3493	2763	0	0
T10	333723	321459	0	0
T11	6395	6340	0	0
T16	72468	72381	0	0
T17	1512	1454	0	0
T18	87009	86948	0	0
T19	64646	64481	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	93516941	0	0
T3	14578	609	0	0
T4	3493	0	0	0
T10	333723	0	0	0
T11	6395	1147	0	0
T12	0	11500	0	0
T16	72468	0	0	0
T17	1512	30	0	0
T18	87009	24558	0	0
T19	64646	11175	0	0
T26	0	1788	0	0
T28	0	2443	0	0
T45	0	6327	0	0
T58	2208	0	0	0
T59	3851	0	0	0
T67	0	61992	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	93516941	0	0
T3	14578	609	0	0
T4	3493	0	0	0
T10	333723	0	0	0
T11	6395	1147	0	0
T12	0	11500	0	0
T16	72468	0	0	0
T17	1512	30	0	0
T18	87009	24558	0	0
T19	64646	11175	0	0
T26	0	1788	0	0
T28	0	2443	0	0
T45	0	6327	0	0
T58	2208	0	0	0
T59	3851	0	0	0
T67	0	61992	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	393379073	0	0
T1	1194	1105	0	0
T2	2508	2452	0	0
T3	14578	14508	0	0
T4	3493	2763	0	0
T10	333723	321459	0	0
T11	6395	6340	0	0
T16	72468	72381	0	0
T17	1512	1454	0	0
T18	87009	86948	0	0
T19	64646	64481	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	393379073	0	0
T1	1194	1105	0	0
T2	2508	2452	0	0
T3	14578	14508	0	0
T4	3493	2763	0	0
T10	333723	321459	0	0
T11	6395	6340	0	0
T16	72468	72381	0	0
T17	1512	1454	0	0
T18	87009	86948	0	0
T19	64646	64481	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	93516941	0	0
T3	14578	609	0	0
T4	3493	0	0	0
T10	333723	0	0	0
T11	6395	1147	0	0
T12	0	11500	0	0
T16	72468	0	0	0
T17	1512	30	0	0
T18	87009	24558	0	0
T19	64646	11175	0	0
T26	0	1788	0	0
T28	0	2443	0	0
T45	0	6327	0	0
T58	2208	0	0	0
T59	3851	0	0	0
T67	0	61992	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	40934377	0	0
T3	14578	909	0	0
T4	3493	0	0	0
T10	333723	0	0	0
T11	6395	94	0	0
T12	0	13562	0	0
T16	72468	0	0	0
T17	1512	46	0	0
T18	87009	1740	0	0
T19	64646	48	0	0
T26	0	228	0	0
T28	0	107	0	0
T45	0	812	0	0
T58	2208	0	0	0
T59	3851	0	0	0
T64	0	368	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	99504786	0	0
T3	14578	610	0	0
T4	3493	0	0	0
T10	333723	0	0	0
T11	6395	1149	0	0
T12	0	19504	0	0
T16	72468	0	0	0
T17	1512	30	0	0
T18	87009	24558	0	0
T19	64646	11175	0	0
T26	0	1788	0	0
T28	0	2443	0	0
T45	0	6349	0	0
T58	2208	0	0	0
T59	3851	0	0	0
T67	0	61992	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	93516941	0	0
T3	14578	609	0	0
T4	3493	0	0	0
T10	333723	0	0	0
T11	6395	1147	0	0
T12	0	11500	0	0
T16	72468	0	0	0
T17	1512	30	0	0
T18	87009	24558	0	0
T19	64646	11175	0	0
T26	0	1788	0	0
T28	0	2443	0	0
T45	0	6327	0	0
T58	2208	0	0	0
T59	3851	0	0	0
T67	0	61992	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	93516941	0	0
T3	14578	609	0	0
T4	3493	0	0	0
T10	333723	0	0	0
T11	6395	1147	0	0
T12	0	11500	0	0
T16	72468	0	0	0
T17	1512	30	0	0
T18	87009	24558	0	0
T19	64646	11175	0	0
T26	0	1788	0	0
T28	0	2443	0	0
T45	0	6327	0	0
T58	2208	0	0	0
T59	3851	0	0	0
T67	0	61992	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	99504786	0	0
T3	14578	610	0	0
T4	3493	0	0	0
T10	333723	0	0	0
T11	6395	1149	0	0
T12	0	19504	0	0
T16	72468	0	0	0
T17	1512	30	0	0
T18	87009	24558	0	0
T19	64646	11175	0	0
T26	0	1788	0	0
T28	0	2443	0	0
T45	0	6349	0	0
T58	2208	0	0	0
T59	3851	0	0	0
T67	0	61992	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	393379073	0	0
T1	1194	1105	0	0
T2	2508	2452	0	0
T3	14578	14508	0	0
T4	3493	2763	0	0
T10	333723	321459	0	0
T11	6395	6340	0	0
T16	72468	72381	0	0
T17	1512	1454	0	0
T18	87009	86948	0	0
T19	64646	64481	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T10 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T11,T17
1	0	Covered	T3,T11,T12

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Covered	T3,T11,T17
1	1	Covered	T3,T11,T12

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T11,T17

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T12
1	1	Covered	T3,T11,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T11,T12

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T11,T12

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394250859	393379073	0	0
CheckNGreaterZero_A	1043	1043	0	0
GntImpliesReady_A	394250859	93516950	0	0
GntImpliesValid_A	394250859	93516950	0	0
GrantKnown_A	394250859	393379073	0	0
IdxKnown_A	394250859	393379073	0	0
IndexIsCorrect_A	394250859	93516950	0	0
NoReadyValidNoGrant_A	394250859	40934321	0	0
Priority_A	394250859	99504851	0	0
ReadyAndValidImplyGrant_A	394250859	93516950	0	0
ReqAndReadyImplyGrant_A	394250859	93516950	0	0
ReqImpliesValid_A	394250859	99504851	0	0
ValidKnown_A	394250859	393379073	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	393379073	0	0
T1	1194	1105	0	0
T2	2508	2452	0	0
T3	14578	14508	0	0
T4	3493	2763	0	0
T10	333723	321459	0	0
T11	6395	6340	0	0
T16	72468	72381	0	0
T17	1512	1454	0	0
T18	87009	86948	0	0
T19	64646	64481	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	93516950	0	0
T3	14578	609	0	0
T4	3493	0	0	0
T10	333723	0	0	0
T11	6395	1147	0	0
T12	0	11500	0	0
T16	72468	0	0	0
T17	1512	30	0	0
T18	87009	24558	0	0
T19	64646	11175	0	0
T26	0	1788	0	0
T28	0	2443	0	0
T45	0	6327	0	0
T58	2208	0	0	0
T59	3851	0	0	0
T67	0	61992	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	93516950	0	0
T3	14578	609	0	0
T4	3493	0	0	0
T10	333723	0	0	0
T11	6395	1147	0	0
T12	0	11500	0	0
T16	72468	0	0	0
T17	1512	30	0	0
T18	87009	24558	0	0
T19	64646	11175	0	0
T26	0	1788	0	0
T28	0	2443	0	0
T45	0	6327	0	0
T58	2208	0	0	0
T59	3851	0	0	0
T67	0	61992	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	393379073	0	0
T1	1194	1105	0	0
T2	2508	2452	0	0
T3	14578	14508	0	0
T4	3493	2763	0	0
T10	333723	321459	0	0
T11	6395	6340	0	0
T16	72468	72381	0	0
T17	1512	1454	0	0
T18	87009	86948	0	0
T19	64646	64481	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	393379073	0	0
T1	1194	1105	0	0
T2	2508	2452	0	0
T3	14578	14508	0	0
T4	3493	2763	0	0
T10	333723	321459	0	0
T11	6395	6340	0	0
T16	72468	72381	0	0
T17	1512	1454	0	0
T18	87009	86948	0	0
T19	64646	64481	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	93516950	0	0
T3	14578	609	0	0
T4	3493	0	0	0
T10	333723	0	0	0
T11	6395	1147	0	0
T12	0	11500	0	0
T16	72468	0	0	0
T17	1512	30	0	0
T18	87009	24558	0	0
T19	64646	11175	0	0
T26	0	1788	0	0
T28	0	2443	0	0
T45	0	6327	0	0
T58	2208	0	0	0
T59	3851	0	0	0
T67	0	61992	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	40934321	0	0
T3	14578	909	0	0
T4	3493	0	0	0
T10	333723	0	0	0
T11	6395	94	0	0
T12	0	13562	0	0
T16	72468	0	0	0
T17	1512	46	0	0
T18	87009	1740	0	0
T19	64646	48	0	0
T26	0	228	0	0
T28	0	107	0	0
T45	0	812	0	0
T58	2208	0	0	0
T59	3851	0	0	0
T64	0	368	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	99504851	0	0
T3	14578	610	0	0
T4	3493	0	0	0
T10	333723	0	0	0
T11	6395	1149	0	0
T12	0	19504	0	0
T16	72468	0	0	0
T17	1512	30	0	0
T18	87009	24558	0	0
T19	64646	11175	0	0
T26	0	1788	0	0
T28	0	2443	0	0
T45	0	6349	0	0
T58	2208	0	0	0
T59	3851	0	0	0
T67	0	61992	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	93516950	0	0
T3	14578	609	0	0
T4	3493	0	0	0
T10	333723	0	0	0
T11	6395	1147	0	0
T12	0	11500	0	0
T16	72468	0	0	0
T17	1512	30	0	0
T18	87009	24558	0	0
T19	64646	11175	0	0
T26	0	1788	0	0
T28	0	2443	0	0
T45	0	6327	0	0
T58	2208	0	0	0
T59	3851	0	0	0
T67	0	61992	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	93516950	0	0
T3	14578	609	0	0
T4	3493	0	0	0
T10	333723	0	0	0
T11	6395	1147	0	0
T12	0	11500	0	0
T16	72468	0	0	0
T17	1512	30	0	0
T18	87009	24558	0	0
T19	64646	11175	0	0
T26	0	1788	0	0
T28	0	2443	0	0
T45	0	6327	0	0
T58	2208	0	0	0
T59	3851	0	0	0
T67	0	61992	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	99504851	0	0
T3	14578	610	0	0
T4	3493	0	0	0
T10	333723	0	0	0
T11	6395	1149	0	0
T12	0	19504	0	0
T16	72468	0	0	0
T17	1512	30	0	0
T18	87009	24558	0	0
T19	64646	11175	0	0
T26	0	1788	0	0
T28	0	2443	0	0
T45	0	6349	0	0
T58	2208	0	0	0
T59	3851	0	0	0
T67	0	61992	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394250859	393379073	0	0
T1	1194	1105	0	0
T2	2508	2452	0	0
T3	14578	14508	0	0
T4	3493	2763	0	0
T10	333723	321459	0	0
T11	6395	6340	0	0
T16	72468	72381	0	0
T17	1512	1454	0	0
T18	87009	86948	0	0
T19	64646	64481	0	0