Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	27281821	1		T1	56		T2	308		T3	262
full_word	7535423	1		T1	5		T2	56		T3	64

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34816944	1		T1	61		T2	364		T3	326
auto[TlIntgErrCmd]	93	1		T222	2		T223	1		T224	4
auto[TlIntgErrData]	111	1		T222	6		T223	8		T224	4
auto[TlIntgErrBoth]	96	1		T222	2		T223	1		T224	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30489386	1		T1	57		T2	323		T3	271
auto[1]	4327858	1		T1	4		T2	41		T3	55

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	26633057	1		T1	56		T2	301		T3	257
auto[TlIntgErrNone]	partial	auto[1]	648488	1		T2	7		T3	5		T9	463
auto[TlIntgErrNone]	full_word	auto[0]	3856207	1		T1	1		T2	22		T3	14
auto[TlIntgErrNone]	full_word	auto[1]	3679192	1		T1	4		T2	34		T3	50
auto[TlIntgErrCmd]	partial	auto[0]	34	1		T340	4		T337	3		T338	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1		T222	2		T223	1		T224	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T344	1		T346	3		T347	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T342	1		T243	1		T348	1
auto[TlIntgErrData]	partial	auto[0]	46	1		T222	2		T223	1		T224	1
auto[TlIntgErrData]	partial	auto[1]	58	1		T222	4		T223	7		T224	3
auto[TlIntgErrData]	full_word	auto[0]	2	1		T340	1		T246	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1		T345	1		T346	1		T349	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1		T222	1		T223	1		T224	1
auto[TlIntgErrBoth]	partial	auto[1]	57	1		T222	1		T224	1		T340	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T338	1		T350	1		T244	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T346	1		T243	3		-	-

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20859	1		T125	1033		T128	494		T77	159
full_word	3769195	1		T1	10		T3	26		T12	312

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3789773	1		T1	10		T3	26		T12	312
auto[TlIntgErrCmd]	79	1		T222	1		T223	4		T224	2
auto[TlIntgErrData]	119	1		T222	7		T223	4		T224	5
auto[TlIntgErrBoth]	83	1		T222	1		T223	2		T224	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3764646	1		T1	10		T3	26		T12	312
auto[1]	25408	1		T125	1201		T128	604		T77	174

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1332	1		T125	93		T128	33		T77	9
auto[TlIntgErrNone]	partial	auto[1]	19278	1		T125	940		T128	461		T77	150
auto[TlIntgErrNone]	full_word	auto[0]	3763196	1		T1	10		T3	26		T12	312
auto[TlIntgErrNone]	full_word	auto[1]	5967	1		T125	261		T128	143		T77	24
auto[TlIntgErrCmd]	partial	auto[0]	27	1		T222	1		T223	1		T224	1
auto[TlIntgErrCmd]	partial	auto[1]	43	1		T223	3		T340	1		T337	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T347	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1		T224	1		T337	1		T338	1
auto[TlIntgErrData]	partial	auto[0]	52	1		T222	4		T223	2		T224	2
auto[TlIntgErrData]	partial	auto[1]	55	1		T222	3		T223	1		T224	3
auto[TlIntgErrData]	full_word	auto[0]	9	1		T223	1		T344	1		T345	2
auto[TlIntgErrData]	full_word	auto[1]	3	1		T349	2		T243	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	27	1		T344	1		T341	2		T343	1
auto[TlIntgErrBoth]	partial	auto[1]	45	1		T222	1		T223	1		T224	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T346	2		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1		T223	1		T224	1		T343	1