PWRMGR Simulation Results

Sunday December 24 2023 20:02:26 UTC

GitHub Revision: 671f2b57e2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96716765175854174075659971574604807242747408006700796360560480210023744343645

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.750s	30.675us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.690s	33.818us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.660s	71.767us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.470s	321.796us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.010s	44.143us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.480s	56.410us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.660s	71.767us	20	20	100.00
		pwrmgr_csr_aliasing	1.010s	44.143us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.590s	233.187us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.590s	233.187us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.840s	68.221us	50	50	100.00
		pwrmgr_lowpower_invalid	0.800s	37.953us	50	50	100.00
V2	reset	pwrmgr_reset	1.450s	80.931us	50	50	100.00
		pwrmgr_reset_invalid	1.090s	108.386us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.450s	80.931us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.790s	318.538us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.910s	314.057us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.980s	54.836us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	8.710s	1.677ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.690s	20.100us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.760s	330.927us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.760s	330.927us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.690s	33.818us	5	5	100.00
		pwrmgr_csr_rw	0.660s	71.767us	20	20	100.00
		pwrmgr_csr_aliasing	1.010s	44.143us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.920s	47.290us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.690s	33.818us	5	5	100.00
		pwrmgr_csr_rw	0.660s	71.767us	20	20	100.00
		pwrmgr_csr_aliasing	1.010s	44.143us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.920s	47.290us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.710s	454.477us	20	20	100.00
		pwrmgr_sec_cm	1.770s	720.228us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.770s	720.228us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.770s	720.228us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.710s	454.477us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.200s	851.564us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.360s	835.573us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.020s	54.176us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.700s	30.596us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.770s	720.228us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.770s	720.228us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.770s	720.228us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.710s	44.704us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.710s	63.214us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.730s	248.031us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.660s	71.767us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.660s	71.767us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.530s	234.724us	0	50	0.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	45.990s	9.059ms	50	50	100.00
V3		TOTAL			50	100	50.00
		TOTAL			1070	1120	95.54

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.94	98.22	96.58	99.44	96.00	96.32	100.00	99.02

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 44 failures:
  • Test pwrmgr_escalation_timeout has 44 failures.

    • 0.pwrmgr_escalation_timeout.51917527562102979384756558237428637252538938645319737807672596154022856436359
      Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_escalation_timeout/latest/run.log

        UVM_ERROR @  13194847 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:500
        UVM_INFO @  13194847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.pwrmgr_escalation_timeout.76448732921123603291326514148832768246978641132098968804163102489422439391318
      Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_escalation_timeout/latest/run.log

        UVM_ERROR @  24318732 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:500
        UVM_INFO @  24318732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 42 more failures.

• UVM_FATAL (pwrmgr_escalation_timeout_vseq.sv:30) [pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable has 6 failures:
  • Test pwrmgr_escalation_timeout has 6 failures.

    • 1.pwrmgr_escalation_timeout.31308208141031523290936961955395011819780419507187523071410689523336689324367
      Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_escalation_timeout/latest/run.log

        UVM_FATAL @ 274285375 ps: (pwrmgr_escalation_timeout_vseq.sv:30) [uvm_test_top.env.virtual_sequencer.pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable
        UVM_INFO @ 274285375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.pwrmgr_escalation_timeout.105571015715607164266828231681638111663210878551346492795891048645451592621658
      Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_escalation_timeout/latest/run.log

        UVM_FATAL @ 988106457 ps: (pwrmgr_escalation_timeout_vseq.sv:30) [uvm_test_top.env.virtual_sequencer.pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable
        UVM_INFO @ 988106457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

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