Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	18969763	15476	0	0
intr_enable_rd_A	18969763	22694	0	0
reset_en_rd_A	18969763	1262	0	0
reset_en_regwen_rd_A	18969763	886	0	0
wake_info_capture_dis_rd_A	18969763	1040	0	0
wakeup_en_rd_A	18969763	2010	0	0
wakeup_en_regwen_rd_A	18969763	1097	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18969763	15476	0	0
T14	395238	31	0	0
T15	7783	0	0	0
T16	1630	0	0	0
T23	0	4	0	0
T24	0	67	0	0
T26	57733	0	0	0
T27	5832	0	0	0
T39	56262	0	0	0
T40	18505	0	0	0
T47	1895	0	0	0
T63	4991	0	0	0
T76	0	5	0	0
T84	4162	0	0	0
T113	0	40	0	0
T114	0	33	0	0
T115	0	16	0	0
T116	0	9	0	0
T117	0	39	0	0
T118	0	58	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18969763	22694	0	0
T3	2588	4	0	0
T4	4257	11	0	0
T5	2832	0	0	0
T6	14165	0	0	0
T7	10154	0	0	0
T8	5489	0	0	0
T9	1192	0	0	0
T10	60197	185	0	0
T25	0	51	0	0
T42	3619	0	0	0
T43	10590	0	0	0
T49	0	12	0	0
T53	0	175	0	0
T84	0	100	0	0
T119	0	12	0	0
T120	0	3	0	0
T121	0	52	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18969763	1262	0	0
T55	0	17	0	0
T61	0	87	0	0
T77	0	12	0	0
T89	0	115	0	0
T94	0	15	0	0
T115	362858	4	0	0
T116	88873	0	0	0
T122	0	9	0	0
T123	0	6	0	0
T124	0	11	0	0
T125	0	14	0	0
T126	1142	0	0	0
T127	1623	0	0	0
T128	8113	0	0	0
T129	2043	0	0	0
T130	13229	0	0	0
T131	1969	0	0	0
T132	57286	0	0	0
T133	1726	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18969763	886	0	0
T55	0	21	0	0
T59	316632	3	0	0
T61	0	80	0	0
T77	0	8	0	0
T89	0	95	0	0
T95	0	6	0	0
T122	0	6	0	0
T123	0	2	0	0
T124	0	18	0	0
T125	0	2	0	0
T134	15329	0	0	0
T135	3155	0	0	0
T136	2145	0	0	0
T137	7511	0	0	0
T138	5176	0	0	0
T139	804	0	0	0
T140	2570	0	0	0
T141	2402	0	0	0
T142	3357	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18969763	1040	0	0
T55	0	25	0	0
T59	0	4	0	0
T61	0	76	0	0
T77	0	11	0	0
T89	0	114	0	0
T115	362858	5	0	0
T116	88873	0	0	0
T122	0	9	0	0
T123	0	3	0	0
T124	0	26	0	0
T125	0	15	0	0
T126	1142	0	0	0
T127	1623	0	0	0
T128	8113	0	0	0
T129	2043	0	0	0
T130	13229	0	0	0
T131	1969	0	0	0
T132	57286	0	0	0
T133	1726	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18969763	2010	0	0
T55	0	26	0	0
T61	0	208	0	0
T77	0	4	0	0
T89	0	114	0	0
T94	0	13	0	0
T95	0	8	0	0
T115	362858	6	0	0
T116	88873	0	0	0
T122	0	5	0	0
T124	0	20	0	0
T126	1142	0	0	0
T127	1623	0	0	0
T128	8113	0	0	0
T129	2043	0	0	0
T130	13229	0	0	0
T131	1969	0	0	0
T132	57286	0	0	0
T133	1726	0	0	0
T143	0	104	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18969763	1097	0	0
T55	0	15	0	0
T59	0	4	0	0
T61	0	88	0	0
T89	0	80	0	0
T95	0	11	0	0
T115	362858	1	0	0
T116	88873	0	0	0
T122	0	15	0	0
T123	0	2	0	0
T124	0	20	0	0
T125	0	14	0	0
T126	1142	0	0	0
T127	1623	0	0	0
T128	8113	0	0	0
T129	2043	0	0	0
T130	13229	0	0	0
T131	1969	0	0	0
T132	57286	0	0	0
T133	1726	0	0	0